Dt ela ners Pree t] Cee+ contains only CPU [Memory, 10, timers ae separately provided.| Designer decides size of ROM, RAM & 10 handling, © Wtis better in Multi-Tasking, General Purpose. ‘© Architecture : Von numen (Mosty) High speed and High Cost. 4 ttrequires more hardware to be interfaced, + Does not support bit addressabilty [Mosty] 4 CPU, Memory, 1, Timer are on single chip. ‘© Fixed site of ROM, RAM & 10 handling. © Relatively weak in Multi-Tasking. © specific Purpose. © Architecture : Harvard [Mostly]. © Relatively Low speed and low cost. ie requires les hardware tobe interfaced. Support bit addressabilty [Mosty]. + Examples : 8085, 8086, Core i3, Core, Corei7, AMD Examples : 8051, AVR, PIC, ARM Processor.jow to Count Memory? © Byte: It is 8 bits Binary number. It is aso 2 digit Hex number. “& Word : tis 16 bits Binary number. It is also 4 digit Hex number. + Why we prefer HEX number system over decimal number system? Cl With decimal digits (0-9), needs 4 bits to represents each digits (0 = 0000 to 9 = 1001). 2 With hexadecimal digits (0-F), it needs 4 bits to represents each digits (0 = 0000 to F = 1111). So by decimal number system, we don’t use 6 code of binary (1010 to 1111) Also decimal to binary conversion is required in computer system for different arithmetic operation, which is not required in Hexadecimal system. For 30 Address lines total address. 4 For40 Address lines total address = 2"%= 2° x 2! = 17 prez We siz pr=4 2"= 1024 p-8 2!= 2048 Bi=16 = 2"= 4096 bi=32 0 2%= 8192 bi=6 = -2"= 16384 br=128 9 2"= 32768 bt =256 _2*= 65536.iecetereea Eire ees ree isd Treat) Address Bus Control Bus © Data Bus There are AO-AIS Address CD There four control signals in Cl There are 00.07 Data buses with buses in 8085, ‘general from 8085. 08s. A These busses are used to Cl Memory Read, Memory write, Its bidirectional buses. Direction Identity the address of 10 Read & 10 write. ‘of buses is based on read and Memory and 10 peripherals. ‘write operation.Architecture of 8085 ii = g| —Bimee)s | cines)8 | ra aS a = 2 Coe aoe peeredArchitecture of 8085 | twee TNTA RSTSS RSIS RST7S TRAP oot + an aeeeeertes (Reg) ar D or er Cente) ermal peered ‘Address Buffer Data/Address Buffer ow “henet OUT AIS-AB Address bus _ADT-ADO Address/Data bus0 w— WR os Microprocessor 8085 PIN Diagram —si0 — rss lasts, inte > INTA How © Buses in 8085, Bus « ¥ Power Supply and Clock Frequency © Power Supply 2 8085 has Vec = +5V and Gnd = Reference 4 Xtand x2 2 Crystal is connected in between these two pins. Frequency is internally divided by two. O So to operate at 3MHz we should give 6MHs clock 1, 2 with higher hen 50% duty cycle Times {E112 with Lower ten Som uty ce Tiroprocesior 98 50% duty eye Time # axour O Clock output is used to provide clock for other devices.0 we WR co a nd —e| Microprocessor 8085 PIN Diagram — soo —sio — last? —rst6s lasts, Line > INTA Hoa How Address Bus {8085 has 16 lines for Address bus. These lines are split into two segments: AIS-AB and AD7-ADO, C1 Here A1S-AB holds higher Byte of Address and AD7 ‘ADO has address and data lines. © Data Bus 8085 has 8 lines for Data bus AD7-ADO. In executing an instruction, during earlier part of the cycle, these lines are Address lines and later part of cycle it holds data bus. © ALE— Address Latch Enable Wt is a positive going pulse generated every time in ‘machine eye. Its used to latch Lower address from AD7-ADO. Ol When itis 2er it indicates Data on AD7-ADO.RESET reser OUTS easy —e| we WR a Microprocessor 8085 PIN Diagram —sio tp rss lasts inte > INTA How ¥ Control signals (Ate, RD, WR, 10/1, $0 and 51) % RD = Read 1 Its Active Low signal which indicates read operation to be performed by 8085 ove data lines This read operation may be there wth memory or 10 devices © WR=wrte CIR te Actve Low signal which indleates write operation tobe performed by 8085 over data ines This write operation may be there with memory ot devices. + 10/H1 = Input-Output oF Memory ities loge“, 10 operations shouldbe done by 8085. Htitistogic 0; Memory operations should be done by 08s.a map as-is % SOand st oma Cl Tes rsa sas > s00-407 axoure ne E RESETIN Opcode Fetch o 1 1 RD=0 —-| oes = — ae MemoryResd | 0 | 1 | 0 | RD=0 = ‘Memorywrte | 0 | 0 | 3 | WR=o0 Microprocessor ae 10 Read 1 [1] 0 RD=0 on 8085 em, [owe 1 [0] 1 | WR=0 0 —— er — "+3 | rere stood |_| t| sera =0 wre lasts NTR T RD =WR=z — NTA = ZK NTA = 1 Reset anon nde! Howaxoure RESET reser ours] easy —e| 0 we WR oF nd —e} Microprocessor 8085 PIN Diagram te ists, —rsr6s be inn —-iNra I nor — of 8 ¥ Reset and Ready © RESETIN When it goes low, 8085 i getting reset Pc= 00004 RESET OUT Cit indicates that the MPU is being reset. It can be 2 The Buses are tristate during that. Used to reset other devices Ready (This signal is used to delay the microprocessor read. Cor write cycles until a slow responding peripheral is ready to send or receive data, © When it goes low 8085 will walt for integer numbers of cytes nti 0s high,axoure RESET reser ours) Ready —e| 0 we WR om nd —e| Microprocessor 8085 PIN Diagram Lap sas te a Commi 3 50st fase ene Ee ert dl ¢ 100" stoner = ie ores = = = a HowRESET —o! reser ours Ready —e| 0 wD wR os nd —e} Microprocessor 8085 PIN Diagram —rsr7s rss lasts inte > INTA hor How ¥ 8085 Interrupt % INTR~ interrupt request 1 Its used for general purpose interrupt. + INTA Interrupt Acknowledge itis used for interrupt acknowledge RST, RST 6S and RSTS.S These are vectored interrupts that transfer program control to specie memory locations. A They have higher priorities than the INTR interrupt. oP 1 Its non maskable interrupt 1 Ithas highest priority.ax our RESET reser ours) Ready —e 0 wD wre oo a Microprocessor 8085 PIN Diagram —si0 — —rst6s lasts, bine —-iNra 1m of 8085 ¥ DMA signals HOLD This signal indicates that a peripheral such as DMA controller is requesting the use of the address and data bus. © HUDA O Itis Hold Acknowledge. Ottis giving acknowledgment to hold signal of OMA.Sa Ze ee (AG) ee Pe ieee ICY D7 D6 DS D4 D3 D2 Di DO 1 Cy= 4, Carry is generated in execution of instruction. Example: maa i cy=0, carryis not generated in execution of instruction. MVIA,CCH | --ASCCH 1100 1100 © P= parity Fog MViB.e6H | B= E6H 1210 0110 1 P= 4, Result has even numbers of 1s A008 ‘A= 82H 1011 0010 1 Po, Result has Odd numbers of 1's {2 AC» 1, Result has carry from 03 to D4 bt, thats referred Nibble to Nibble cary. 1 AC=0, Result has no carry from 03 to Dé bt thats referred zero Nibble to Nibble cary. 2- zero Fag 1 Ze 1, Result is Zero ater execution of instruction. 20, Results Non Zero ater execution of instruction. S=Sign Fag 1 S1, Result has 07 «1 1D $=, Result has 07 «0.6 acm i fantmtnrpe of SHS, xt fa oped ot AL MUM | 3 scergcvsten tune onzcoomwan ener corn MMT & rac terner ss C8085 has Five essential flag in flag register (5, Z, AC, P & Cy) PCT 2 erence titers PE | Sarton errr retenia 0.6.00 2 seeernpan Se csel png on ‘Address Bus © Program Counter (16 bits) ‘onnis Fons ne Pt sguence the neton of pros Uarciont| tee hncion of Pea pout te edaws tow eich the nt byte is to be fetched, when a byte is being fetched, the PC is incremented by one to point next instruction. + Stack Pointer (16 bits) 5 8085 uses $P as memory pointer. it paints R/W memory, called as Stack. 1 Top of stack memory address is indicated by SP.© Using 10/M, BI Memory Read, emory + 10/M = input-output or Memory itt is loge“ 10 operations should be done by 8085. 2 ifitis logic‘; Memory operations shouldbe done by 8085. © RD = Read its Active Low signal which Indicates read operation to be performed by 8085 over data lines. <2 This read operation may be there with memory oF 10 devices. Microprocessor © WR= Write 8085 iets Active Low signal which i performed by 8085 over data lines. 2 This write operation may be there with memory or 10 devices. ieates write operation to be} ‘Memory Read - MEMR Memory write - MEMW Input Output Read - TOR Input Output Write - TOWR0R 10/M, RD and WR we can generate Memory Read, Memory Write, 10 Read and 10 + 10/M1 = Input-Output or Memory 10/8 MEMR "Hits ogic'Y, 10 operations should be done by 8085. a O Hits to ‘07, Memory operations should be done by 8085. © RD =Read WR MEMW —_QI'It Is Active Low signal which indicates read operation to be| eI performed by 8085 over data lines. 1 This read operation may be there with memory or 10 devices. Microprocessor, WR we 8085 TOR It is Active Low signal which indicates write operation to be} perormed by B08 ove sts tes C ca Firs operon ay earth mor ot dees ww — = ‘Memory Read - MEMR Memory write - MEMW Input Output Read - TOR Input Output write - TOWae : Aa ee seer, Address / Data Lines of 8085 b tye © 8005 has 16 tines for Address and Data fe G Higher Byte of addres is there on A1S-AB uP i D tower Byte of address is time multiplexed with 8085 data lines which is given by AD7-ADO oo Je a aoa O To separate address and data we use ALE terminal. Ap, ‘Ay Gl When positive going pulse is glven by ALE at that or Ae time AD7-ADO represents address. at 45 | ower When ALE is ecve low at that time ADT-ADO 40, At [Address works as data inesAs Aw aa ie —— |_wenee fa Mapes Address / Data ins of 8085 ie cress S08 has 16 lines for Address and Data, a» Higher Byte of adress thereon A1S-AB. woe : tower tye of adress eine mulled wh 8085 data lines which ven by ADT ADO. aus. |S = Enable To separate address and data we use ALE terminal. 40, " {2 When postive gung pls sven by ALE ot that aa 4 time AD7-ADO represents address. ae 4 | ower When ALE is active low at that time AD?-ADO a te Lares, works as data lines AD; ‘a, | BreMachine Language, Assembly Language & Higher Level Language % Higher Level Language Assembly Language Assembly Language (Gere, ete) Mov as +c ‘apo c Mov 8A Compiler Assembler Lower Level Language / Machine Language [Obj / Hex / Bin} Higher Level Language Commonly used higher level language for microprocessor 3 microcontroller is C, C++. in Assembly Language, programing is done with use Mnemonics of given processor or controller 4 Mnemonics Gin Assembly Language programing instructions are written terms of Mnemonics. Example of 8085: ADD B and MOV B.C Complies Main task of complier isto convert HLL into Machine Language. it syntax errors there then it also indicate error in given lines. © Assembler | Main task of Assemblers to convert AL into Machine Language. O teyntax errors there then it also indicate error in given lines. & Machine Language {Machine Language is there in terms of binary which can be eas endentands by precemerercontealien.Here 10 devices treated as Memory % 16 bits addressing (Ap ~ Ays) % team address = 2"* = 64K Address + Number of devices = 64K = 65536 + Due to many devices we need more decoder hardware in Memory Mapped 10. 4 Due to limited Address lines (16) with 8085 available memory less with memory mapped 10. & Here we use MEMR and MEMW control signals. ‘© Data transfer happens between any registers and 10. ‘© ALU operation is done with al registers. + Instructions Example: LDA 00XKH, STA 1000XH, MOV A.M © Here 10 devices treated as 10. ‘© Bbits addressing (Ap — Az) © Reanaddress = 2" = 256 Address + Number of devices = 256 4 Due to less devices we need less decoder hardware in 10 Mapped 10. © Auailable memory more with 10 mapped 10 as number of devices ae less in 10 mapped 10. Here we use TOR and TOW control signals. ‘© Data transfer only between Accumulator and 10. © Not Available. * Instructions Example: IN )0000H, OUT 00H_ ssa ae Pe = 10008 = aes 085 7 in opcode c= 20H 07-400 00 3a Opcod & MOV 8 executions needs only a | opcode etch machine cyte. FULL) © So, Ater instruction, B= 24Hap7-ao0 | 00H _}~~(paea rom } F Memory00H }~—~("“Data trom Memory‘© OUT (8 bit Port Address = OSH) [Opcode =03H) PC = 10008] © OUT OSH executions needs opcode fetch, Memory Read & 10 Write 8085 machine cycle. an 24h % So, After instruction, A= 24H wil get display at OSH port Address. © OUT OSH [Opcode Fetch = 03H) _% Me 8 OSH Out ry Read OSH from 1001H % 10 Write A ax asa Y 78 Youn X 1 rent ncares oon nor.avo Yeon )—( 03H Opeod aan )—{_ om = an Pon OH wR=1Stesage Setenabery Memory Memeg Seeni Radon Aheats >, Serta Aexets Rom, Ram se Eoncable Dram Pormenod3 4K eeeern Addvaas Ue = Daan’ = tae <0, 2 Mablvess tines acre Ben’? _ Dade Vines > 8 Corbel Syml = Memory Ped fri Thee er ee SS ee Memerg ChMemory Interfacing in Microprocessor 8085 Draw the interfacing of a 4K EPROM having a starting address 2000H with 8085 microprocessor. Use demultiplexed address/data lines and 3-to-8 decoder (7415138). oF Tn mevorry Whorfacing fous types of Sams enc sett 4) widvas lives 2) Daly tines 3} Genbel Noes ay chip het > 4 Ereem Addvas \wes dan - axe atxt-d 60, 12 rblveas Lines are Ten’? Dada Vines 2 N3 4k Ere Addvas lines Dan ann -axd 2 go, 12 reblveas tines ene ent” £ Ae And Dada Vines 2 Cerbel Syrnt = Mernery Pend Memeg Mapping Bet ooo See OCIS EOE Soe198Memerg Chip | Aw Mw Min Ara] Au fhe hy Ag [Ag Mg Me Ag] Me Aa My Me] Address O68 16 Pa acaalanint BO OST toca n EProm aK oo tofu ce fuvttfetit| aren heed (DEB) “F, [-——> rte, | ! Ae auc -——+* Ate fal bh oF ao rsMemory Interfacing in Microprocessor 8085 Interface 4K EPROM and 16K RAM with 8085 processor. Write address range for both the memory chips and also shew the address decoding logic. oF In mooery Whorbing Nous tyres of Symele one sett 4) midvas lines 2] Daly tines 3) Gonbel Nes a} Chip Slat For 4% EPReMm Addis Nines pan 4axK axe? a2” So Foal 12 fklrest tineg ave em" C Rom And dy Vines ~ 2 Conbel Mines + Merneeg RandMemory Interfacing in Microprocessor 8085 Interface 4K EPROM and 16K RAM with 8085 processor. Write address range for both the memory chips and also show the address decoding logic. CF In mevorry Whorfeeing fous types of Sqmle ene u 2} Daly tines 3) Gobel Nees Select aves Unes ay chip > Fer 4% EPrem duress tines DAK 4KK x22 So total 12 Alves tines ave Yom C Ro“ And) dy Vines = 2 Gombel Mines = Memery Rend pet > we 2AM seed ge. 2% Sea Dede lines BOD> Few 4k Eprom Address Nhaes i <> ee Fam PAK 4K Kae Ke a2 = amor ree e sureedtez*. 2 © foal 12 Adkdvest Umeg ave vem” C Ro An) Daly Vines = 2 (D- Dy) Combel line = Memery Rend Addrag lines = 14 Che Ma) Dede ting = @ © D,-0) lombol Vines = Newer fad > Memory © Memory Mapping a Memery Memerg Chip | Ay Mm My An] Au fhe ty al my Me Ae Ad Addvers Coren XeMemevy Memerg Chip 4 Aa hy Mo] Addrees EPROM Coton 4k rrr eam 5Memerg Chip Memery Address EPROM z as z Saad 4 °° of: 1424/12 2141111] ofeee em OTTO co] oo So] OS COlOS OO] t000n KE ogfs 2/22 22/ 2222/22 22] sere Lato Eprom Ca¥) 3 am cee) aae a) G0, tehed 12 Abdrac tines seq? Ae Aud ots zcD.-d1 whe Meme Pend Mena enite > Deke tee F CD%DI > Goube) sgn > emery fend Memeg Mapping a ~ Add vets, ana A care omen ae Sor =a arrtn BFFF 2Starting and Ending Address Calculation with OFFSET For 1KB memory, if starting address is 0344H then find ending address of memory. > Fetal Adverts ee 2¥8 memosy, N= 2” o3aah -itd era - 4004 7a A 3 > Ending hides Starting Miss + N-4 rin 0344H + 400-1 +431 SsDetermine the starting address of 4KB memory with ending address BABFH. toe Tek Addsss with 4kB wemag , N= 2x2! te ao" ener ~ 222" - FFF = 000M aacO » Stavting Aldvess = Ending Aidvess — (N-1) = BABEH— CEFF ND - ft1, 2KX8 memory IC 2. 4K X8 memory IC 3. 8KX4 memory IC 5 wity 2085 bebe) te Aileew Mee CMe-Awd ¥ « CD-D/I > Teh) memeg omy 2625 = 2 xg aexe ae Total ids = Rott memey — cant ck — a9 qe Meneny 2ROKE 2) Tohl ke! past Berth cmegl crea este lt 4 ghar Memeny x2 xe ) Total Mc's Pay? Memesy 64 xox8 bits of microprocessor has 16 bits address lines with 1KB memory chip interfaced as shown in figure. The address for the chip is* Here IO Devices are treated as 10 [Input Output Devices). It needs 8 bits addressing by AO to A7 address lines of microprocessor 8085. So, it can address = 2° = 256 10 devices or Addresses. Compared to memory mapped IO, it needs less hardware for decoding of 10. The reason is memory mapped IO have 16 address lines for address and selection of 10. With 10 mapped IO, read and write of 10 is done by JOR and [OW control signals. In 10 mapped 10, Data transfer is only possible with Accumulator and 10 devices. + With Microprocessor 8085, we have only IN and OUT instructions for IO mapped IO.40 [10 Address] 8 bits port Address OUTPUT Interface Q For OUTPUT of data we use OUT Instruction with 8085. Example : OUT [8 bits port] Q Accumulator content will get displayed on Data lines D0 to D7. Pere 10 Address Pulse Device Select 10 Write TOW = Pulse e with 8085 | fo | Peripheral]% INPUT Interface O For INPUT of data we use IN Instruction with 8085. Example : IN (8 bits port} Q Accumulator will get content of Data lines D0 to D7 from Input Devices. Tri State crc Device Select Pulse.Absolute and Partial Decoding in 8085 With Absolute decoding, we use all the address lines [A0-A7] for decoding of IO devices. With Partial decoding, few address lines are not used for decoding 10 devices. “+ With Absolute decoding, we have fixed address for decoding 10. With Partial decoding, multiple address may decode 10. “+ Absolute and partial decoding may happen in case of Memory interface. 2 Example of Absolute decoding. Q Example of Partial decoding. C2 Port address is there with IN and OUT | O Port address is there with IN and OUT instruction as per all AO to A7 lines. instruction as AO to A7 lines, but few Q SCH =0101 1100 b address lines are not used. O Here, A7, AS, Al, AO =0 and A6, Aa, | O) 0101 11Xx b= SCH, SDH, SEH and SFH. 3, A2=1. O Here, A1 and AO are unused, so total So, device has fixed address. four address may decode given 10.LED Interfacing in 8085 + Interface 8 Common Anode CA LEDs to 8085 connected at port address 01H and write a program to turn ON all LEDs. O Program * MVIA,OOH ; for all LED A = 00H * OUTOIH = ; Awill get displayed at 01H port + HUT ; Terminate program Vec = SV 10 Address Pulse Device Select Pulse BEREERRE [10 Address 01H}