BWD ELECTRONICS PTY LTD MILES STREET MULGRAVE vic 3170 AUSTRALIA PO BOx 325 SPRINGVALE 3171 PHONE (03) 561 2888 (3 LINES) CABLES ‘OSCILLOSCOPE’ TELEX AAg5115 540 Dc to 100MHz OSCILLOSCOPE ISSUE 15PAGE 2-6 7-12 12 13-16 16-24 24-25 25 26-42 43-52 52 52 AI-A25 bwd 540 DUAL TRACE OSCILLOSCOPE INDEX SECTION DESCRIPTION INTRODUCTION PERFORMANCE FUNCTION OF CONTROLS INITIAL CHECKING FIRST TIME OPERATION MEASUREMENT OF VOLTAGE & TIME DC and BATTERY OPERATION PROBE ALIGNMENT CIRCUIT DESCRIPTION ALIGNMENT AND MAINTENANCE REPLACEMENT PARTS WARRANTY PARTS LIST CIRCUITS 540 546B.W.D. ELECTRONICS PTY MANUAL CHANGE INFORMATION FOR MODEL BWO 540 FROM SERIAL NO. ISSUE D4TE FROM SERIAL NO. ISSUE DATE 30000 3 18.3.76 33300 4 12.4.76 34600 5 4.8.76 35610 6 1.11.76 I - Issue Page Sect. ere AMENDMENT 3 22 6-16 Lines 1 and 2 should read: - "three types of displays are available to view a waveform delayed in e by the 540 time base. 4 1A 13 1120 ADD R8 10MQ 10% CC 4 1A 13 1120 ADD R58 10MQ 10% CC 4 13A | 13 | 1120 | ADD C16 3p3 630V+.5pF NPO CER 4 13A | 13 1120 ADD C17 3p3 630V 4.5pF NPO CER 4 13A | 13 1120 ADD C67 3p3. 630V_s+.5pF NPO CER 4 244 | 13 | 1120 | ADD S2CR PART OF R123, 4 2A | 13 1120 ADD S52CR PART OF SR123 4 1A 13 1120 R4 Changed from 8,2Q to 10Q 4 1A | 13 | 1120. | R54 Changed from 4.79 to 1502 4 2A | 13 | 1121 | R128 Removed (wos from gate G102 to GND) 4 13A | 13 1121 C109 Removed ( was from point A to GND) 4 2A | 13 | 1121 | R150 Changed from 220 to 33 4 24 | 13 1121 | R151 Changed from 229 to 33Q 4 2a mi N21 R152 Changed from 33Q to 22Q 4 2A 13 21 R153 Changed from 33Q to 22Q 4 21A | 13 1121 G105-G108 INCL. Changed from 2N5770 to BFY90 4 21a | 13 1121 | @145-@148 INCL. Changed from 2N5770 to BEY90 4 4A [13 1122 |C184 Changed from 4p7 to 3p3 4 14A | 13 | 1122 | C185 Changed from 4-20pf var. to 3p3 fixed 4 4A | 13 1122 ADD C186 IpF 630V 10% NPO CER 4 3A | 13 | 1122 [Replace R183. 470 with a link 4 4A | 13 | 1123 [R265 Changed from 2K7 to 2K2 4 4A 13 1123 R266 Changed from 8K2 to 5K6 4 4A 13 1123 R267 Changed from 12K to 10K 4 5A 113 | 1123 | ADD R294, R295 3302 1/4W MG IRH RG 1/4 4 4A | 13 | 1123 | C252 Changed from SépF to 68pF 4 4A | 13 | 1123 | C253 Changed from 4p7 to InF 4 4A | 13 | 1123 |C256-Changed from 27pF to 33pF 4 21A 113 | 1123 | Q251, 252 Changed from 2N5770 to BFY9O. ” 4 5A 13 1124 R320 Changed from 5K6 to 1KO : 4 6A 113 | 1124 |R331 Changed from 4702 to 332 4 6A | 13 | 1124 |R332 Changed from 102 to 339 4 6A 113 1124 |R341 Changed from 1KO to 4702 : 4 6A | 13 1124 | ADD R345.2K2 1/4W MG IRH RG 1/4 4 154 | 13 1124 C307 Changed from 6p8 to 3p3 4 194 | 13 [1126 | ADD D315 IN4148 F75A/648/mb eeeB.W.D. ELECTRONICS PTY. LTD. MANUAL CHANGE {iNFORMATION FOR MODEL BWD 540 FROM SERIAL NO. ISSUE DATE I FROM SERIAL NO. ISSUE DATE 30000 3 18.3.76 33300 4 12.4.76 34600 5 4.8.76 | 135610 6 T1176 Issue Page Sect. Cet. AMENDMENT 4 15A | 13 1124 C317 Changed from In to 10n and re-located (was from wiper of RV304 to GND) 4 5A 13 1124 R309 Changed from 39K to 10K and re-located (was from wiper of RV304 to $251A) 4 - - 1124 C369 Circuit error only should be 0.68 4 2A | 13 1124 U302 Changed from 95HO2 to 10109, For alternative pin connections refer below: 29 2SHO2 von £ [upper 1% GND 2 SH = AGES: GND 8 45.4 ‘ Laveh bid 45.41 EOHIN = * 6 4 22A | 13 1125, @401 Changed from 2N5770 to 2N3694 4 8A 13 1126 R540 Changed from 8K2 to 10K 4 22A | 13 1126 Q504, Q505 Changed from PN4121 to 2N4258 4 2A | 13 1127 Q655 Changed from 2N3055 to MJE30SS 4 - - 1127 D660 Reverse connections circuit only 4 = 1127 F652 Replaced by link and re-inserted between anode ‘of D658 ond Q655 emitter 4 - - 1127 C651 and C652 -ve leads disconnected from anode of D658 and re-connected to Q655 emitter 4 9A 13 1138 R612 Changed from 2202 to 5602 4 9A 13 1138 R614 Changed from 6202 to 1KO 4 9A 13 1138 R623 Changed from 6K8 to 15K 5 All circuits re-drawn - no changes. 6 1A 13 1120 R17 Inserted in GND lead of SIA 1502 5% é 1a | 13 1120 | R67 Inserted in GND lead of SIA 1502 5% 6 134 | 13 1120 | ADD C18 IpF 630V 10% NPO CER 6 13A | 13 | 1120 | ADD Cé8 -IpF_630V_ 10% NPO CER 6 18A | 13 a Delete DIOI, D104, D141, D144 IN4148. 6 = | = | 1121 | DIO1 Replaced by link (was in series with D102 with cathode to point A). 6 - - 1121 | D104 Replaced by link (was in series with D103 with anode to -ve lead of C102). 6 - - 1121 D141 Replaced by link (was in series with D142 with cathode to point B). 6 - - 1121 D144 Replaced by link (was in series with D143 with anode to -ve-lead of C142), 6 - | = | 1121 | Dc Voltages on bases of Q105, Q106, G45, G14 hanged from OV to-0.1 -2- F75A/648/mbB.W.D. ELECTRONICS PT LTD. MANUAL CHANGE INFORMATION FOR MODEL BWD 540 FROM SERIAL NO. ISSUE DATE FROM SERIAL NO. ISSUE DATE 30000 3 33300 4 | 34600 5 35610 6 Issue Page Sect. | Cet. AMENDMENT 6 - | - 1121 | DC Voltages at(62) and (3) changed from +4.3V to +N 6 47 10, 4e] - Line 1 Change 0.2V to -0.1V 6 48 | 10.4e; = Line 2 (from top of page) change 4.3V to 3. 6 4A 13 1122 ADD R246 150K 5% 1/4W MG IRH RG 1/4 6 4A 13 1122 R231 Changed from 22K to 39K 6 4A 13 1122 R236 Changed from 22K to 39K 6 4A} 13 1122 C184 Changed from 4p7 to 3p3 6 4A 13 - Delete R244 22K 6 14A} 13 ne Delete C237 47pF and C238 18pF 6 1eA} 13 - | Delete D231 IN4148 é = | = | 1122 | Remove C238 18pF and R244 22K. Replace with link- D231 and C237 Issue 5. Cirevit shown below. bine * f pep sco/a9. O28 avy TRG ‘Neur PRM R382 288i. en 6 15A| 13 1124 ADD C330 InF 63V HI-K CER é 9A] 13 | 1127 | Delete R671 10KQ 5% IW replace with link. Geni was in series with wire from D664 anode to D607 1138). 6 BA 13 1138 ADD R608 1K5 5% 1/4W MG IRH RG 1/4 6 94] 13 | 1138 | ADD R625 1K5 5% 1/4W MG IRH RG 1/4 6 9A 13 1138 R621 Changed from 1MQ to 270KQ 6 94 | 13 | 1138 | R623 Changed from 10K to 12K é 9A | 13 | 1138 | R624 Changed from 10K to 18K é - | = | 1138 | Remove D607 and re-connect with anode to D605 cathode and cathode to +55V. F75A/648/mbB.W.D. ELECTRONICS PTY. LTD. FROM SERIAL NO. | ISSUE DATE FROM SERIAL NO. | ISSUE DATE 30000 3 18.3.76 36200 8 9.3.77 | 33300 4 12.4.76 30000 5 B37 34600 5 ooeene 36811 10 17.5.7 35610 6 T.11.76 ~ i 30000 7 24.1.7 i Issue | Page | Sect. | Cet. AMENDMENT 6 - | 1138 | G4)Woveform added and $3) waveform changed \ From:- 8 : 7 | 6 12a} 13 1120 | C2 changed from 6p8 to 3p3 6 134] 13 1120 | C16 changed from 3p3 to 4p7 6 IBA} 13 1120 | C52 chonged from 6p8 to 3p3 7 -| - 1124 | Circuit error. Join the two SOKQ sections of R370A~1 os shown (issue 7). Applicable to all previous serial numbers. | 8 8a | 13 1138 | R603 changed from 5K6 10 6K2 1%. | 9 oA | 13 1124 | R370A-1 Pt. No. changed from TF-1 to 010-001 9 7A |. 13 1125 | R450A-G Pt. No. changed from TF=1 to 010-001 9 - - 1127. | Output to D407 (#1138) on 1652 changed from Pin 2 | to Pin 7 (cirevit error ~ applicable from Serial No. 35610). | a oa | 13 1138 | Delete R624 was in parallel with RV6OT 10 1138 | Connect L.H. end of RV601 to 10 8a | 13 1138 | ADD R600 47K 5% 1/4W MG IRH RG 1/4 10 124 | 13 1138 | ADD RV605 20K Lin, Preset. SON VTP 10 7A | 13 1138 | ADD C60 1000F 63V HI-K CER 10 1138 | D607 Catnode wos previously connected to +58V 10 nA | 13 112z | Delete RV18Z 2002 Preset replace with link. 10 7A | 13 1126 | R504 changed from 18KQ to 15KQ 10 8A | 13 1126 | R510 changed from 6KB to 5K6 10 4 | 9 The tind paragropn from the top of the page as veen changed. from: The rectonguler waveform is token from the BC-DC convert transformer winding | that supplies the #35 rail. {f is taken through R671 ond then clipped on the positive excursion by a 47V zener diode 0446! Dé07 conducts on the pos part of the signal but disconnects the negative going waveform. 10 4 10 Pasition of RV606 shown in “TOP VIEW" 10 51 10 Description of RV606 adjustment odced to end of first paragraph 10.4 (p). F754/648/mbB.W.D ELECTRONICS PTY. LTD MANUAL CHANGE INFORMATION FOR MODEL BWD 540 FROM SERIAL NO. | ISSUE Dare || FROM SERIAL NO. | ISSUE DATE 36811 ' 10 17.5. | | 37821 i 20. Seeneuneieine | 38445 i 22 5.12.77 | | | 9980 "13 | 104.78 | | ; _ _ Agee © a | a.78 Issue | Poge | Sect. | Cet. AMENDMENT 1 10 | 194 | 13. | 1126 | D503 changed to DSCBA end D5OBB added in series ~ | the type remains unchanged. 10 | 198 13 | 1126 | D504 changed to D504A and D504B added in series ~ i | the type remains unchanged. 10 | 198 | 13° | 1126 | D506 changed to DS06A and D506B added in series ~ | | the type remains unchanged. jou | 1124 | Lead deleted going to $402 ¢/2 from D313 anode. 11 | 16A | 13 | 1125 | C411 150pF 630V 20% CER removed and replaced with | | link. Was in series with pin 6 U402F and junction of | i | D407 and R420. Soul 7a 13° | 1125 | R420 2K2 5% 1/4W MG removed. Was from = to anode of : I p4o7. {out | 1125 | Connection from $402 c/2 now goes to R508 #1126. i | | | Originally it went to Q309 Base #1124. ; | 8A 13 | 1126 | R508 1K2 5% 1/4 MG added. Me} 198 13 | 1126 | 5048 removed. Replaced by link. i 504A CCT Ref. changed to D504, | | Type changed from IN4148 to Selected Component. Ne ellzee za) 13 | 1125 | R402 33Q Changed to 682. | 42 | 178 13 | 1125 | R425 1502 Changed to 4702 5% IW RGI ) a3} 10a 13 | 1122 | R752 8202 Removed, Was from base G751 to gnd. 13, | 104 13 | 1122 | R753 15K Changed to 6kB 13 1122 | Connection from R751 now to C204 base. Was to ©201 base. 13 1127 | DC Output Socket added to Rear Panel, 13 | 8A | 13 | 1138 | R605 4k7 Changed to 6K2. 13 | 9A | 13 | 1138 | R624 22K (nominal) added. Selected component. 13; 23A | 13° | 1138 | @605 BF469 added in series from wiper of RV604 to pit isle { 1138 | Ground removed from RV601. / 44 | 3A 19 | 1122 | R199 12K Added. Circuit and Parts List omission. 14 | 144 | 13 | 1122 | C204 68pF Added. Circuit and Parts List omission. i 48 | 0 | Description added to 10-4(g) 14g yee7eeen e108 | Description added to 10-4(a) 451) 10 | | Description added to 10-4(m) 14 | 52 10 | "Feed in S0kHz to Ch. 2 and adjust for 6 div. display | | «." changed to "Feed in 50kHz to Ch. 1 and Ch. 2 a ‘ond adjust ...." Sect. 10-4 (q) "14! 228, 13, | 1124 | G31 & C312 BC547. changed to BCSA7A. 14, 228 13 | 1125 | G402 & Q403 2N3694 changed to 2N4249 matched pair. 145 22A 0) 13} 1125 F75A/648/mb L 401 2N3694 changed to BC547A. -5-B.W.O. ELECTRONICS PTY. LTD. MANUAL CHANGE INFORMATION FOR MODEL BWD 540 F75A/548/ mio - - FROM SERIAL.NO. | ISSUE | DATE —||_—_- FROM SERIAL NO ISSUE DATE 40800 ! | C — | ' | ' r T i L | Issue | Page ] Sect. AMENDMENT 115 | 1124 R332 33Q replaced by D301 IN4148 | 15 1124 R348 10K and C322 1p5 removed, Were in series with each other with R348 connected to pin 4 U303B and C322 connected to the cathode of D310, pois | 6a 3 | R332 removed. 1 1S | 6A | 13 1124 R327 820Q added in series with C314. 15 | 6A | 13 R348. removed. 15 15A 13 C322 removed. 115 194 13 1124 | D301 IN4148 added. 15 19A 13 ; 1124 | D310 1N4148 changed to 1N6263. ; 15 194 13 1125 | D410 1N4148 changed to IN6263. i 15 16A 13 1126 C503 1p5 added across R510. | 15 20A 13 D691 TIL209 changed to FLV310 15 | 4A 13 , 122 R230 10kQ added from pin 10 U231C } 15 | 2 j 2 | Para 2.3: Bandwidth reduced from 2MHz to 1.5MHz. 1MODEL BWD 540, 100 MHz DUAL TRACE OSCILLOSCOPE INTRODUCTION The bwd 540 field portable DC to 100MHz SmV to 20V/div dual channel oscilloscope provides the high performance demanded of a laboratory instrument with the advantage of lightweight and optional battery operation of a portable instrument. The bwd 540 has the features and performance to make accurate measurements with ease. A well laid out panel and a large high intensity 8 x 10 cm CRT simplifies operation learning time and makes for easier operation. Several features make this oscilloscope unusually versatile. A x5 gain amplifier for Ch. 1 increases the sensitivity to ImV/div without loosing the dual trace facility that coscade operation via cable patching causes, XY operation i phase corrected to give ten times the measuring range than is usually provided. Polarity inversion and a vernier are also included for the X input. Alternative power input requirements give the 540 a ‘go anywhere’ low voltage, @5 operation is possible from AC sources, low voltage DC or an optional battery pack. The battery charger is incorporated as standard and the battery pack may be added at any time, carried separately and the oscilloscope may even be operated remotely from it by an extension cable. The two time bases feature wide operating range from 5n sec/div down to Ssec/div for the main T.B. and 1 sec/div for the delayed time base. to beyond 100MHz for 1 div deflection and both time bases have i trigger selection of both source and polarity. Internal trigger take off is taken before the position controls but after the vernier and polarity controls. This ensures the trigger level control setting is always related to the displayed signal amplitude but not its position on the CRT. It also means the Ch. 1 signal output is always proportional to the Ch. 1 display. ‘An additional trigger facility provided for the main time base is a video sync. separator for stable T.V. line or frame lock. This feature may also be used: in communication work to lock modulated RF signals to the modulation envelope. For modulated signals and complex digital words, a variable trigger hold off operates on all time base speeds, As the 540 is based primarily on standard multi-sourced components, servicing is simplified and component availability is assured. A range of accessories is available. This includes a low cost switched dual range probe with 1:1,10:1 and a reference OFF position. Full 100MHz bandwidth is available in the 10:1 position and 20MHz at the 1:1 setting. A light hood, storage cover, dust cover and the BP3 rechargeable battery pack are also available from B.W.D. Electronics or your nearest supplier. 540 -1- 54624 2.2 2.3 PERFORMANCE - VERTICAL SYSTEM. Bandwidth: (mV to 2V/div). DC to 100MHz-3db referred to 6 div. deflection at 50kHz from 25Q source with vernier to Cal position. In ADD mode bandwidth is DC to 100MHz~3db.. (BV to 20V/div) DC to >30MHz~3db referred to 8 div defl. at 50kHz. AC Coupling <2Hz = 3db or 0,2Hz with 10:1 probe in use. Bandwidth: Channel 1 only at x5 gain, DC to 30MHz~3db AC coupling <2Hz-3db. Rise Ti 4n Sec. 10nSec at x5 gain and attenuator steps from 5 to 20V/div. Measured between 10% and 90% points on a 6 div. input. Sensitivity: (Both Channels) SmV to 20V/div. in 12 calibrated steps (1-2-5 sequence). Channel 1 only x5 gain ImV to 4V/div. Calibration Accuracy: Within 3% at switch settings with Vernier to cal (5% at x5 gain). Uncalibrated Vernier continuously variable between steps, extends range to 50V/div. Input R&C: IMQ within 2% and 26pF within 2pf. Maximum Input Voltage: 500V (DC + Peak AC) AC component 500V p-p maximum TkHz or Tess. Minimum Undistorted Deflection; >8div at 75MHz. >5.5 div at 100MHz. Display Modes: Chan.1, Chan. 2, Alt. Chop, Add. Chopping Frequency: Approx. 500kH2. Delay Line: Permits viewing of leading edge of displayed waveform. Trace Inversion: Push=push switch enables Channel 2 to be inverted for display ‘convenience or when the two amplifiers are used in the ADD mode to provide a differential input facility. CMRR (In ADD Mode): At least 20db from DC to 20MHz. Common mode signal ‘amplitude 5Sec/div. NOTE: Vernier is operative on 'A' TB only when ‘A is selected, It is operative on "B' TB in the intensified mixed and delayed modes. Sweep Accuracy: measured over centre 8 div. of CRT. #15 0 435°C He x10 Magnification | (excluding first 20nSec of display) | | 415 0 438°C 0-50 5% 6% Calibrated Sweep Delay: Delay Time Range: 100nSec fo ISec. Delay Time Accuracy: 3% over calibrated range. Delay Multiplier: 0.5 to 10 x Time/Div setting. Delay Ji Multiplier Linearity: <1% of full scale. 1 in 20,000 of maximum delay time. ‘A’ Time Base Sweep Modes: Mode: Auto (with level select) Non-Auto or Single Sweep with reset button and ready lamp. Ready lamp indicates trace readiness prior to commencement of sweep in all operating modes. Trace free runs in Auto with no trigger signal . Time Base 'A' Trigger: Source: Int. Chan. 1 or 2, or mixed displays, Ext. xl or Line frequency. Coupling: AC or DC, Slow, Fast, TV Line TV frame (also operates as a detector for modulated RF waveforms). Slope: +or - with level select over 8 div. internal or SV p-p external. Internal, 0.3 div defl. DC to >25MHz increasing to | div defl. at HF trigger mode. Signal level requirement increases by x5 in Ch. 1. x5 gain. In CHOP mode trigger bandwidth extends to not less than IMHz. Sensitivi 100MHz2.6 External, 200mV p-p DC to 25MHz increasing to 500mV at SOMHz in gated trigger mode. 200mV p-p at 100MHz in HF trigger mode. Max, trigger level control 5V p-p (50V p-p with 10:1 probe). Signal level extends fo not less than IMHz in CHOP mode. External Input Impedance: 1MQand 10pf. ‘Max. Input Voltage: 500V (DC + Peak AC) AC component 500V p-p maximum. Video Trigger: <2div of composite waveform to over full screen deflection for line or frame lock. Trigger Hold Off: Continuously variable. To greater than the selected sweep period ‘above 10mSec/div. "BY Time Base (delayed). Sweep Rate: 50nSec to 0.2Sec/div. in 19 steps of 1-2-10 sequence. An uncalibrated Vemier covers range between steps and extends range to at least 1Sec/div. Sweep Accuracy: (Measured over centre 8 div. of CRT) x1 Magnification 415 t0 435°C (excluding first 20nSec of display) 415 to 435°C 0-50°C 5% ime Base igs Source: Int. Chan.1 or 2or Ext. Coupling: Int. & Ext. DC coupled. Slope: +or - with level select over 8 div. internal or 42V pp Ext. Sensitivity: Int. 1 div 10Hz to 20MHz. 2 div extends range from DC to 40MHz. H.F. trigger increases to 70MHz for 1 div and 100MHz for 2 div deflection in H.F. trigger mode. Ext. 200mV p=p 10Hz to 25MHz 500mV p=p DC to 40MHz. H.F. trigger increases to 100MHz for 200mV p-p input in H.F. trigger mode. Mixed Sweep. Accuracy: Identical to A & B sweep accuracy excluding 0.5 div of start of main sweep and 0.2 divor 0.1ySec. (whichever is greater) either side of transition from main to delayed sweep. Note: Transition from A to B sweep is delayed compared to the Time/Div. X multiplier Setting until B time base reaches the same voltage as A time base and takes over the display. Mag: x1 or x10 Horizontal position control fitted with fine and coarse adjustment. Max, Sweep Speed: 5nSec/div. Output Waveform: 4mm Sockets located on rear of 540. (1) Displayed Time Base +1V to +13V 10K source impedance. (2) A Time Base gate 40.2V to 4V 1kQ source impedance. (3) B Time Base gate +0.2V to +4V 1kQ source impedance. 540 5 7 54627 2.8 540 546 GENERAL DETAILS. CRT: 80x 100mm rectangular, high beam current gun with mesh PDA. EHT: 12kV. Graticule: Internal parallax free with variable illumination, Fitted light blue filter for P31 or amber for P7. Phosphor: Normally fitted with P31, P7 available as Option 04. Z Modulation: 2V positive will blank trace at all intensities from DC to >10MHz. Input impedance 4.7KQand 10pf. Max input 430V p- Beam Finder: Push button returns trace to within limits of CRT screen and over rules intensitity setting. Calibrator: Output, rectangular, positive going from ground, IkHz frequency approx. Voltage: 1V p-p. Accuracy: 1% 15 to 35°C, 2% 0 to 50°C. Low Voltage Indicator: L.£,D. ‘Power On' indicator lamp flashes when DC or battery voltage is below minimum operating level . Output Waveform: 4mm Sockets located on rear of 540 main frame. (1) Displayed Time Base +1V to 13V 10k source impedance. (2) A Time Base gate +0.2V to +4V 1kQ source impedance. (3) B Time Base gate +0.2V to +4V 1kQ source impedance. Power Requirements. AC. 98 fo 195V and 195 to 270V. Selection by recessed switch accessible through bottom cover. 48 to 40Hz 50 watts max. DC. 20V to 30V at 1.5 Amps. Battery Pack (optional) 3 hours per recharge. Battery charger incorporated in standard instrument. Recharging from AC or 32V DC. Finish: Grey blue covers, epoxy coated trims and offwhite panels. Dimensions: 145mm high x 320mm wide x 430mm deep (standard model). Height increases to 223mm with battery pack added. Weight: Instrument 9kg. Battery Pack = 5kg. Shipping weight: Instrument 12kg. Battery Pack 7kg. Ordering Code: Standard model bwd 540. Battery Pack bwd BP/3 Options: P7 phosphor/05 Environmental . Specification is met within power supply range shown and from 45°C fo +35°C fo 80% RH unless otherwise stated. ADD 2% to specification for 0-50°C and 0 to 90% RH. Storage - 20°C to +70°C. BATTERY PACK. The BP/3 pack may be attached or detached from Model bwd 540 at will. It is fixed by two screws and connects via a plug lo the rear panel socket, If desired the battery pack can be carried separately to the oscilloscope and is provided with a handle for this convenience. Operation via an extension cable from the battery pack is possible when it is necessary fo keep instrument weight to a minimum. Recharge time of 14 hours provides approx. 3 hours running time.29 2.11 Optional Accessories: x 10:1 DucHead Probe P32 Dust cover cl6 10:1 200MHz probe kit P33 Panel storage cover SC52 Demodulator probe P35 Oscilloscope trolley Tél Viewing hood C44 Cameras-details on request External graticule for video applications. See accessory leaflets for full details. PROBES. Two probe sets are available to suit the 540 amplifiers. Both provide full bandwidth operation. P32 DuoHead Probe: This miniature probe incorporates a 3 position slide switch for 1:1 ‘and a REF off position. It is supplied with a detachable retractable hook, a Fixed point and a BNC adaptor. Pulse response in the 10:1 position exhibits approx. 8% overshoot with a InSec rise time input. Input C & R fs T1pf and 10MQ. Asa 1:1 probe bandwidth is limited to approx. 20MH2 Input C & Ris 64pf and IMO. P33 200MHz Probe: This model has detachable 1:1, 10:1 or 100:1 heads plus a demodulator head. With the 10:1 head only bandwidth is 200MHz and pulse response exhibits 4% overshoot with a InSec rise time input, Input C & R is 13pf & 1OMQ. Probe is supplied with detachable miniature hook, point 4mm jack and 10:1 head 1:1 and 100:1 heads are optional extras. DIMENSIONS. ole 251 -6- 540 546LAYOUT OF FRONT PANEL CONTROLS CHANNEL 1 CONTROLS | ‘A' TIME BASE CONTROLS | [ 1 x5 Gain Attenuator | Level control Trigger select | Switch ‘ & Auto Switch Switches Vertical ' Ampl. | Attenuator F Time Base Ground | Vernier | ane 5.5. Reset Range Switch Switch witch | Trigger hold off & HF. A&B T.B. eee cS Trigger Vernier Control | Coupling Balance [ss | wit A&B Ext, Posit, ch. 2 2 Calibrate, (side) Chassis Ground [ ac-pe Vert. | 7 7 Time Base | | coupling} Position Hl Switch Attenuator Switch | Ampl. Vernier Delay Time Ground Multiplier. Switch pc ti lances! ‘ig. Norm = ae | Selectors Invert Attenuator Switch | CHANNEL 2 CONTROLS CRT CONTROLS ‘B' TIME BASE See page 25 ior rear panel layout and Battery Pack connections. 540 oeCh.1 and Ch.2 Volts div. ~ selects the vertical deflection factor in a 1-2-5 sequence (Vernier control must be in the calibrated detent for the indicated deflection factor) Calibrated accuracy is within 3% Vernier - provides continuously variable uncalibrated deflection factors between the calibrated settings of the VOLTS/div switch. { ~ positions the display vertically. Input Connectors - for application of external signals to the inputs of the vertical ‘amplifier. In the X-Y mode of operation, the signal connected fo the Ch.2 connector provides horizontal deflection and the signal connected to the Ch.1 connector provides the vertical deflection. Input impedance is 1 megohm paralleled by approximately 24pf. Minimum bandwidth in the normal mode of operation is DC to 100MHz from SmV to. 2V/div and DC to 3OMHz from SV to 20V/div & x5 gain on Ch.1. Xzaxis has a bandwidth in X-Y operation of DC to 2MHz and is compensated to have 2 or less phase difference with relation to the Y axis from DC to 500kHz. AC, DC and GND Push Buttons - selects the input coupling to the vertical amplifier, In the AC position, signals are capacitively coupled to the vertical amplifier. The DC component of the input signal is blocked. Low frequency -3db point is below 2Hz. In the DC position, all components of the input signal are passed to the input amplifier. In the GND position, the input of the vertical amplifier is disconnected from the input connector and grounded. Gain x1 or x5 - Push button out gain is SmV to 20V/div. Button in, gain is increased by x on Chan. 1 only to ImV/div. max. Invert ~ Chan. 2 display is inverted when the button is pressed in. VERTICAL DISPLAY - selects mode of operation for vertical amplifier system. 1, Chan.1 only is displayed. Must als be selected for X-Y operation, ALT: Dual trace display of the signals of both channels. Display is switched Between channels at the end of each sweep. CHOP: Dual trace display of the signals of both channels. Display is switched between channels af a repetition rate of approx. 500kHz. ‘ADD: Signals applied to the Ch.1 and Ch.2 input connectors are algebraically added, and the algebraic sum is displayed on the CRT, The INVERT switch in Chan, 2allows the display to be Ch.1 minus Ch.2 (Normal differential operation). 2, Channel 2 only is displayed. ‘A! Trig (Main or Delaying Time Base). Two push buttons select the required internal trigger source. The right button selects @ mixed signal from Ch. 1 ond Ch, 2 alternately when pushed in, and either Ch. 1 or Ch. 2 when out. The left button selects Ch. 1 when out and Ch. 2 when in. In the ADD mode it supplies the algebaic addition of Ch. 1 ‘and Ch. 2 trigger signals or Ch. 1 - Ch, 2 with the INVERT switch operated, In the Ch. I., CHOP & Ch. 2 modes leave the RH button out and select Ch. 1 or Ch. 2 trigger as required. DC BAL. Preset controls to balance input stage to eliminate trace movement when Vernier controls are operated. -8- 540 5463.2 540 546 TIME BASE SECTION. Two complete time base generators and associated circuits are located within the RH panel section of the bwd 540. Layout and operation of the controls is straight forward and familiarisation will only take a few minutes, The time bases are referred to as A (main) and B (delayed). The time base to provide the CRT display is selected by the five position rotary switch marked HORZ. DISPLAY. Trigger Select Buttons (in sequence from L to R). s. Trace is normal with button out, immediately it is depressed, the next sweep will latch the circuit and prevent further sweeps from occurring. Ready Light: Located above S.S. button indicates trace readiness in all sweep modes and when trace has been reset in the SS. mode and is ready for next trigger signal. it Button out coupling is normal. With button depressed TV Frame or line Tock is obtained and may be locked by adjustment of level control. Line lock is obtained with all other buttons out, Frame lock with the SLOW button pressed. Trigger polarity corresponds with the polarity of the video waveform. Button out enables the positive or rising slope of the trigger waveform to initiate the time base. With the button in the negative or falling slope jers the time base. Slow: Button out, coupling is normal, when pressed in, a CR network attenuates Fignals above 5kHz. | (-3db at 10kHz approx.) Fa Button out, coupling Fignals below 1OktHz and ali Line: When both SLOW and FAST buttons are depressed the lirie frequency powering the oscilloscope is coupled to the trigger circuit to lock the trace. The phase of the line frequency trigger point may be adjusted by the LEVEL control and the + switch. normal, when in,a series capacitor attenuates jinates DC coupling. NOTE: This faci is inoperative on DC or battery operation. AC-DC: Button out trigger circuit is AC coupled and approx. ~ 3db at 10Hz. With button depressed circuit is DC coupled and signals down to DC will trigger the trace. as selected by A Trig push buttons jer attenuators. External signals are Int-ext: Button out trigger signal i located between the vertical amp! selected when the button is pressed. External Input Socket. External input for both A & B trigger circuits. Level Control: Selects the precise point on the triggering waveform that initiates the time base trace. Selection is available of the full 8 div. of CRT display or up to 5V pp of external trigger. Larger external signals can be accommodated by @ 10:1 probe. When LEVEL knob is pushed in the time base will free run if a trigger signal is not present or if the control is turned until it is out of the range of the trigger signal. With the knob out, the automatic base line is eliminated and no trace is present in the absence of a trigger signal. -9-‘ine/Di The large outer knob controls B time base range from 50 nano Sec to 0.2sec/div only. Triple concentric knob. The winged grey knob is the main A time base range and covers the entire range from S0nSec to Isec/div. NOTE: The two knobs are interlocked so that B time base range cannot be switched to a slower speed than the A time base to eliminate incorrect displays. : The small red knob doubles for both A & B time base vernier control. When the HORZ. DISPLAY is set to A it operates as 'A' time base vernier and provides a 5-1 range overlapping each step and extends the range down to approx. 5 sec/div. When the HORZ. DISPLAY switch is turned to the remaining 4 positions the control becomes the B time base vernier providing a 5-1 range and extending the range down to approx. Isec/div. This method of changeover ensures that the A time base in its delaying mode is always calibrated and the delay period is the selected time/div x the multiplier setting. Reset. Push button will reset the time base when the single shot (SS) button is pressed. Trigger Hold Off/HF Trig Switch. Dual function control. With the knob pushed in the time bose operates in a gated trigger mode to beyond 60MHz. When the knob is pulled out the trigger circuit is switched to HF trigger. This increases the sensitivity to enable signals as low as 0.5 div or 200mV pp external to lock the trace at IO0MHz. HF trigger may be used at all frequencies above 1OMHz below this double triggering may occur. Trigger hold off operates with the knob either in or out. Fully clockwise in the NORM position, hold off is minimum. Rotation counter clock- wise will increase the time base hold off on all 'A' time base ranges and to greater than the selected trace length at all speeds above 10mSec/div. Display Switch. A Normal A time base operation with no delay. INTEN. A time base brightened over a selected portion as determined by B time base and the 10 tum Delay Multiplier. BDL'YD ) Only the portion of the trace intensified at the INTEN switch step will be BY A. _) _ shown on the CRT. B TRIGGER ) As for previous step but trace will only be initiated by a trigger pulse DL'YD BY A ) applied to B time base. Push Buttons - vertical row. x1 x10 Mag. Trace length expands x10 when button is depressed. ‘NORM/X-Y. When the X-Y button and x10 Mag button are both depressed Ch. 2 ‘amplifier is switched to the horizontal amplifier to provide identical XY facilities. B time base Trigger selector buttons. Ch.1-Ch.2. Ch.1 selected with button OUT. Ch, 2 with button depressed. INT-EXT. With button OUT Ch. 1 or 2 os selected by the above button is supplied to B time bose trigger. EXT signals via the BNC socket above the TB range ‘tch are coupled in when the button is IN. -10- 540 5463.3 3.4 +or-. The positive shope of trigger signal initiates the B time base with button OUT. negative slope initiates with button IN. Level Control/HF With knob IN B time base is gated and will normally be used for all frequencies to 4OMHz. When knob is OUT the trigger sensitivity is increased to provide HF non= gated trigger which extends the range to 100MHz. Level select is always operative in both the gated and HF trigger modes. Delay Multiplier. _Multiplies the TIME/DIV os selected by the A time base switch ‘vat The fange 0.5 to x10 providing a delay range from 160nSec to T0See. Hortzontal Position. Fine and coarse controls position the trace to display any point along if on the screen. CRT CONTROLS. Inteniy/ Power OnzOff__. Fully aniclock switches AC powar tothe instrament = this includes charging current when rear panel switch is in CHARGE position but NOT DC or battery supplies. Dual Function Control. Clockwise rotation turns on power and increases trace intensity. Focus. Adjusts sharpness of trace, control should be set initially in conjunction with the ‘ASTIGMATISM preset for best overall trace sharpness. Graticule. Adjusts the internal graticule illumination. Power Indicator. When power input voltage is above minimum necessary for correct ‘calibration Tight will be on and continuous. If supply voltage falls below correct level ~ particularly DC or battery the light flashes on and off at a 1 second rate approx. Cal. IV p-p. Approx. IkHz rectangular positive going waveform of IV p-p amplitude. Rise time Is 98-135 195- 270V (OPERATING RANGE) 540 la 5465.1 5.2 540 546 4 FIRST TIME OPERATION. One of the major features of the 540 Oscilloscope is that normal operation is obtained when all push buttons are ‘out’, A quick scan over the panel therefore immediately indicates any variation to normal and assists in quick familiarisation with the instrument's operation. The panel is divided into 3 operating areas. L.H. side is the vertical section - Channels 1 and 2. R.H. side is the A & B Time Base section, Centre are the CRT controls and calibrator. For first time operation, if unfamiliar with this class of oscilloscope, set the controls as below and follow the steps outlined until each feature is understood: Vertical Amp! Attenuators 0.2V/div. Verniers CAL (clockwise) Input switches AC (button OUT) xl = x5 gain (Ch.1) x1 (button OUT) Norm/Invert (Ch. 2) Norm (button OUT) Trigger Select Ch. 1 (both buttons OUT) Time Bases: Trigger buttons Alll out. Trigger level Centered and pushed in. Time/div switches B time base 0,05, Sec (outer ring) A time base 0.2m Sec (grey knob) Vernier CAL (Clockwise) Trigger Hold Off Clockwise and pushed in. Horizontal Display A time base (counterclock) Vertical push button All out. Horizontal position Both knobs centred. B trigger level Centered and pushed in. Multiplier Any setting. CRT Controls: Focus Centered. Intensity ON/OFF OFF, fully counter clock. Graticule 3/4 clockwise rotation. Astig Centered or leave as supplied. Connect power lead to 48 - 440Hz AC supply or leads to 20 - 30V DC supply and switch instrument on. Turn intensity control to approx. 2 o'clock position, after a few seconds trace will appear. Adjust intensity and focus then position it centrally across screen. If trace is not horizontal, adjust the Trace Alignment preset on rear panel until it aligns with the graticule line. Tum vernier control of Ch. 1 counter-clockwise, recentre trace with vertical position control, then rotate vernier back to Cal, if trace moves re-centre with DC Bal control. Repeat if necessary to eliminate movement. Connect a 1:1 probe bwd P32 from the 1V calibrator socket to Ch. 1 input, centre trace. Waveform should be 5 div. high with vernier to cal. If not, adjust calibration at L.H, side of cabinet. -13-5.3 5.4 The IkHz square wave displayed 5 div. high and approx. one waveform per 2 divisions horizontally. Depress the DC button on Ch. 1 amplifier ~ the trace will rise and the bottom of the waveform will now correspond with the CRT centreline indicating the input signal is a waveform positive going with respect to ground. Depress the GND button on Ch, 1, the trace will disappear then after 0.3 sec. a bright reference base line will appear as the Auto time base operates. The GND switch disconnects the input signal in this condition but grounds the amplifier. Release GND push button and trace will again be standing on the cenireline. Release DC button then rotate position control and note display can be moved off CRT above and below, but without changing the trigger condition as the trigger take-off is ahead of the position control. DUAL TRACE OPERATION. Set Ch. 2 amplifier as for Ch. 1, then switch Vertical Display to 2 and depress Trigger Selector Ch. 2 button. Take a parallel signal from the 1V calibrator output to Ch. 2 input (leave Ch. 1 signal connected). Set Balance and Cal as for Ch. 1 previously described. Reduce attenuator settings on both amplifiers to 0.5V/div. then switch Vertical Display to ALT. Two traces will appear which can be positioned above and below CRT centreline. If Ch. 2 is moved up and down the screen it will be noticed no interaction occurs between the displays and trigger is uneffected by the position control. With the traces positioned above each other, switch the time base range switch to slower sweep speeds and observe how flicker between the traces increases until at 10m Sec/div. the switching between the traces is readily visible. This is the useful lower limit of the Alternate switching mode. Now increase the time base speed, the traces will remain locked tight through to 0.05y Sec/div. Return time base range to Im Sec/div again and switch the main frame Vertical Display to CHOP. Trace flicker immediately stops. When the time base frequency is reduced, the two traces appear simultaneously down to the lowest sweep frequency. Retum switch to Im Sec/div. and then increase time base speed. At speeds around 20 Sec/div. the waveforms will start to show the individual chopping sections indicating the useful upper limit of CHOP displays. As been seen, a wise overlap exists where both forms of dual trace display ce used satisfact Witn the time base returned to Im Sec/div. and both attenuators set to 0.5V/div. the traces will be 2 div. high. In this condition set the Vertical Mode to ADD. A single trace will appear with a 4 div. display, i.e. the two traces have been added together. Now press the Invert button on Ch. 2, the waveform will Zsappear leaving only a line. This is the difference between the two signals or the result when one is subtracted from the other. Applications for this form ‘of measurement are described later. Return switches to ALT and normal. TIME BASE OPERATION. Replace the input signal to Ch. 1 with a 2kHz (approx.) sine wave and adjust attenuator or input for 6 display. Time Base to 0.2m Sec/div. 540 eae 5465.5 5.6 540 546 TRIGGER LEVEL. With knob pushed in turn the control and observe that the trigger point moves up and down the wavefront. When it reaches the top or bottom exireme of the waveform the trace blanks out for a fraction of a second when trigger is lost, then the trace free runs in the Auto condition until the level control is readjusted to select a trigger signal. Now push in the + button to select -ve trigger. The waveform will now trigger on a ~ve going slope. Clockwise rotation of the level control will increase the trigger point level towards the ive point of the waveform, anticlock rotation towards the negative point as for + slope. Revert to + ve trigger selection, then pull out the Level Control knob. Auto is now switched off, turn the knob to select level and note the trace disappears when the level extends past the waveform limits, Push knob in again and reduce amplitude of displayed signal, with Level Control carefully adjusted, signal can be reduced to less than 4mm and stable lock is still obtained. T.B._VERNIER. Turn Vernier anticlockwise - observe approx. x5 the number of waveforms on CRT when fully anticlockwise. Return to Cal position. MAGNIFICATION. Adjust input frequency to produce one sine wave per div. and locate the peak of each waveform on a vertical graticule line. Press the x10 Mag. button, The trace will expand either side of the centre and-any portion of it can be viewed by rotating the position control, fine control for precise adjustment being made with the red knob, Return to xl and recentre trace horizontally. HORIZONTAL AMPLIFIER. Identical X-Y Parallel the 2kHz input sine wave to Ch. 1 and 2, set Vertical Display to 1, press X-Y and x10 Mag. buttons. Ch. 1 willnow present the vertical display and Ch, 2 the horizontal. To position the display horizontally use the fine and coarse horizontal position controls. The horizontal deflection may be reversed in polarity by pressing the INVERT switch. Vernier control between attenuator steps is available for both the vertical and horizontal axis, For zero phase shift between X-Y inputs at low ies it is essential to use DC coupling on both channels. XY displays should be contained within the 8 10 div. graticule to eliminate distortion due to signal overdrive. Delayed Time Base Operat : Full details of the three methods of displaying a delayed signal are described on Page 21. Z_MODULATION. Reset all push buttons to ‘out', connect IV p-p sine wave to Ch. 1, switch attenuator to 0.5V/div. Set Vertical Display to ALT. Position displays one above the other. Now parallel the 1V signal into rear panel Z Mod. socket. The tops of each displayed sine wave will diminish in intensity and the Ch. 2 trace will be broken into a series of light and dark sections, NOTE: A positive going signal decreases the trace brightness. ise5.7 5.8 6.1 AMPLIFIER DC_ BALANCE. If trace movement occurs when the vernier control is used, the balance should be reset. Turn the Vernier counterclockwise, recentre with the vertical position control, turn Vernier to CAL, recentre trace with DC BAL preset. Repeat as necessary fo eliminate trace movement. HIGH IMPEDANCE PROBES. For high frequency measurements the input loading on circuits particularly capacitance must be kept to minimum levels. The simplest way to achieve this is by use of a high impedance probe which reduces the input signal by a factor of x10 but simultaneously reduces the input capacitance to approx. 12pf and increases the input resistance fo 10MQ. Two types are available for this model . The bwd P32 and the bwd P33 probes. Both will provide full bandwidth operation. The P32 duo head probe has the additional advantage of a switch to provide 1:1 operation and an OFF reference position. To align a probe, couple it to Channel 1 input jack. Set attenuator to 20mV/div. and time base to 0.2m Sec/div. Place the point of the x10 probe tip on the 1V main frame calibrator socket, a square wave will appear probably with the top and kottom faces tilted in or out, With a small screwdriver supplied, adjust the screw in the side of the probe housing until waveform is square. It will remain correct at all settings. MEASUREMENT OF VOLTAGE AND TIME. The following sections describe the method of making specific measurements with the 540 Oscilloscope. Start with controls set as follows:~ All buttons out, T.B. to ImSec., Trigger Level centred. Vertical Mode to Ch.1. MEASUREMENT OF DC (Direct) VOLTAGES. Press Ch.1 AC-DC switch to DC. For an initial test take a 13V Dry Cell and set the attenuator to 0.5V. Connect the negative end to the Black socket, set the trace fo the centre of the graticule, touch a lead from positive end of the battery to the Ch.1 input socket, the trace will move up 3 div., i-e. 3 x0.5V #1.5V. Now reverse the connections to the battery and note how the trace moves down 3 div. This illustrates how an oscilloscope can display positive or negative voltages or both simultaneously, i.e. when viewing a sine input or square wave. NOTE: The IMQ input impedance of the oscilloscope must be taken into ccount when measuring high impedance points such as the base of transistors or the gate of FET's working with high value loads. The DC input facility may be used to measure AC waveforms swinging about @ AC voltage, as at the collector of a transistor or the anode of a valve, to check for bias settings or collector limiting, ete. Maximum DC input should not exceed x10 input attenuator setting if it is required fo recentre the trace to view a signal superimposed on it. Ifa higher input impedance is required, use a bwd P32 x 10 probe fo increase input fo 1OMQ and 12). -16- 540 5466.2 6.3 6.4 540 546 MEASUREMENT OF AN AC (Altemating) VOLTAGE Set the amplifier AC-DC switch to AC and the attenuator to 20V (if the input voltage is unknown). Connect a lead from ground to the ground side of the signal to be measured, then connect a lead from the input socket to the signal source. Bwd oscillators such as models 1128, 141, 160 or 603A oscillators are suitable for initial experiments in this test. Increase the vertical sensitivity by the Volts/Div. switch until a display between 3 divisions and 8 div. exists. Now adjust the Time Base switch to enable the waveform fo be readily seen. To measure the amplitude of a displayed waveform, measure its overall height in divisions against the calibrated graticule, then multiply this by the attenuator setting and the result is in Volts p-p, e.g. if the display is 6 div. high and the attenuator is set at 0.5V, then the amplitude is 6 x 0.5 = 3V peak to peak; to convert to RMS voltage for sine wave, divide the 3V by 2.84, e.g. 3.00 = 1.06V ims. 2.84 The frequency of a waveform can be found by checking that the Time Base Vernier is turned to Cal (clockwise) then switch the Time/Div. switch to a range where the signal can be clearly seen, e.g. if a waveform is 5 div. long and the switch is at 100i Sec., then the duration of the waveform is 5 x 100y Sec. = 500, Sec. The frequency can be determined by dividing 1 sec., i.e. 1,000,000y Sec by the duration of the waveform - 1098009 = 2,000Hz or 2kHz. INVERTED DISPLAYS, Where it is required to display a waveform inverted on the CRT feed it into Ch. 2 then push the Invert switch button. All information relating to display and measurement of inverted signals is identical to the normal input details, The calibration and accuracy are as detailed in the specification. BALANCED _OR DIFFERENTIAL MEASUREMENTS. AC_ Measurements: NOTE: When using the ‘Add’ facility between Ch. 1 and 2 the following limitations must be considered. Max. AC or DC Common Mode signal isless than 8 div. deflection, if a larger DC signal exists, it should be eliminated by using AC coupling into the amplifiers. To measure a signal appearing between two points in a circuit, neither of which is at earth (ground) potential, e.g. across a push-pull primary of an output transformer, between cathode and grid of a valve or emitter to collector of a transistor circuit and at the same time suppressany signal common to both points such as HT ripple or AC power line frequency as much as possible, the following method is used. Connect a probe from Ch. 1 input socket to one side of the component across which the waveform is developed and another probe from Ch. 2 input socket to the other side. The invert bution on Ch.2 is depressed to INVERT and the Vertical Display is switched to ADD. Attenuators are adjusted to identical settings to present a suitable display. -7-6.5 6.6 6.7 The resultant CRT trace is the waveform being developed between the points to which the leads are coupled. Measurement of voltage and time may be made as described previously as the calibration remains constant irrespective of the input facility employed. The differential input coupling is almost essential when making low level measurements in the millivolt region even when one side of the signal source is grounded. This is because signals generate hum and noise in ground loops and can completely mask the signal. To eliminate this problem, connect the probe from the Ch. 1 socket to the signal to be observed and a probe from the Ch, 2 socket to the nearest ground or common point to the signal on the equipment under fest. Hum and noise will be greatly attenuated by this means. DIFFERENTIAL DC_MEASUREMENTS. When low frequencies or signals with both AC and DC components are to be measured differentially, the mode of operation is almost identical to AC measurements, The following limits should be observed:~ Differential rejection will only operate if the Common Mode signal to be rejected is< 8 div., e.g. with the attenuator set at IV/div. the Common Mode signal must not be greater than 8V AC p=p or + 4V DC, or the input amplifier may be overloaded and the signal will be distorted. The accuracy of the input attenuator resistors also controls the rejection ratio and the other than 5niV settings may reduce the rejection to only 20-1 which means, in the case of a 100V p-p AC signal, a 5V p-p signal could still appear with the required signal superimposed on it. Adjustment of Ch. 1 or 2 vernier control will reduce the level to the minimum obtainable. Provided the limits and methods of connection indicated above are observed when making measurements with a differential amplifier, far more information can often be extracted from a circuit than with single ended amplifier operation, with only one signal lead and one side grounded. CURRENT MEASUREMENTS AC OR DC. If a resistor can be included in the ground end of a circuit the voltage drop across it can provide a direct conversion to the current through it by use of Ohms Law. At low currents a 1Q resistor connected across the vertical input terminal of the amplifier will enable the oscilloscope to read directly in mA or Amps in lieu of mV and Volts. Current through the 19 resistor will develop ImV for every 1 mA flowing and provides the direct conversion for currents fo at least 2 Amps. This configuration will read both AC or DC current and unlike an ammeter will show the actual current waveform. Practical applications are the charging currents in a filter capacitor of a power supply or the current through a rectifier, or high speed displays of pulse currents. IDENTICAL X-Y OPERATION. Start with all buttons out. Then set following controls:- Vertical Display - Ch. 1. Depress X-Y and x10 Mag. buttons. Signals for vertical display are fed into Ch. 1 and for horizontal display to Ch. 2, If phase measurements are to be made on frequencies below 100Hz, the two amplifiers must be DC coupled to minimise variations in the input circuit time consrants. 540 -~18- 5466.8 MEASUREMENT OF VOLTAGE & TIME (Cont'd.) Cascaded Amplifier Operation (Cont'd.) PHASE ANGLE? B c SIN @ = B/A (») ‘A method of measuring the phase angle between two equal frequency sine waves is to apply one signal to channel 1 and [5 the second input to channel 2 (switched through to X display jn the X-Y mode, The phase difference is obtained from the dimensions of the resulting elipse shown above. The phase angle may be recd from the scales above by joining the appropriate points on scales A & B and reading the phase angle on scale C. [49 540 -19- 5466.9 6.10 If zero phase shift exists the line will be straight up to S00kHz. Phase between the two signals can be determined from the chart opposite. No! x10 probes will produce additional phase shift and they must be checked and matched from a common signal source over the range to be measured if it essential to use them. CASCADED AMPLIFIER OPERATION. When the sensitivity of the vertical amplifier requires to be higher than the direct calibration allows or with the x5 gain of Ch. 1 in use, single channel operation with a sensitivity increase of x10 is available. A patching cable is required and shoud be connected between the Ch. 1 Output socket on the rear panel and Ch. 2 input. Irrespective of the input attenuator setting an output of 50mV prp is present at the Ch. 1 output socket for every I div. deflection on the CRT, therefore If Ch. 2 is set to SmV/div. a gain of x10 will exist between Ch. 1 input and the CRT display from Ch. 2. If less gain than x10 is required, use the x5 gain facility of Ch. 1. Bandwidth is approx. 2Hz to 25MHz. It is recommended AC coupling be used for Ch. 2 input to minimise trace movement. Select the time base trigger signal from Ch. 2. LINE TRIGGER, To retain a continuously locked display with a constant phase relationship when exploring signals locked to power line frequencies, e.g. in a power supply, or when tracing hum in circuits, push both SLOW and FAST buttons to select Line. Adjustment of the level control and + switch will provide phase variation of the displayed waveform, VIDEO (T.V.) WAVEFORM DISPLAYS. Video signals from closed circuit system, black and white or colour receivers, or TV Studio signals can be locked with complete stability. A composite signal should be a minimum of 2 div. amplitude. Stable lock can be maintained with signal amplitudes from 2 div. to over 8 div. If the video syne pulses are negative going, select #ve trigger and vice-versa. for vidual equalising layed. By utilising the higher speeds 9 the video information containing To lock to a frame pulse depress the TV and slow buttons then adjust | a stable lock. If the time base range is increased, the pulses and frame pulse serations can be di special test signals can be readily viewed. To lock to a random line leave the slow button out and adjust the Level control for a stable display. Where it is required to select a particular line from the video signal, switch HORIZONTAL DISPLAY switch to intensified. With B time base at 10y Sec. turn the Delay Multiplier 10 turn control until the desired line is intensified, turn display switch to B time base and the selected line will be presented, If the line is unstable select B TRIG DLYD by A then with + slope selected to suit display polarity, adjust the B. Trig. Level Control to display the line with complete stability. - 20 - 540 546540 546 " Tout 12 mate moo — 00 100 wo os os 190 v0 oo os 120 as eo po. 10 s 1 10 100 10 es os eo RISE_TIME 60 6-0: CHART eo es os 50" ro so 40) q 50 20 wo 0 ao zo oe GC a Cacitloscone Measured iso Time of Mise Time ise Time Input Wavetorm To use theabove chart read the rise time of the displayed waveform on the CRT between its 10% and 90% points. Find the point corresponding fo this value on Scale T out. Join this with a straight edge to the value corresponding to the oscilloscope bandwidth on Scale TI, the projection on Scale T2 is the rise time of the input pulse. -2-6.13 6.16 NOTE: As the gating pulse is available at the rear panel the selected line may be distinguished on a Video monitor by mixing the "BY gate pulse with the video to bright-up the monitor CRT during the line presentation, This provides a direct indication of the displayed line location. AMPLITUDE MODULATED CARRIER DISPLAY. The TV syne separator can also demodulate amplitude modulated signals ~ both double and single side band. If an amplitude modulated signal is displayed, select the TV button and + or - slope as required. Adjust the level control to provide a stable lock to modulation frequencies below SkHz. SINGLE SWEEP OPERATION. This feature is primarily used in conjunction with a camera for recording single waveforms, but can also be used at slow sweep speeds for manually lating the trace to coincide with other functions. Two modes of operation are available to suit these applications. For photographic application the Trig. LEVEL knob should be pulled out to Non-Auto and adjusted for correct setting on a similar amplitude waveform. Setting should be slightly away from max. sensitivity to eliminate the possibility of false triggering by noise, hum, etc., which may be present on the input signal. Next press the $$ button, place camera over CRT and open shutter. Apply the input signal which will initiate the time base for one sweep. The trace will then remain blanked out, and latched in a locked-out condition, Release the camera shutter then press the Reset button to release the time base and ready it for the next input signal, The ready condition is indicated by the LED Lamp above the SS button glowing. Where manual initiation of the time base is required, push the Level knob in for Auto operation. Each time the Reset button is pressed, the trace will immediately sweep across the screen once, and not wait for a trigger pulse to initiate it. HIGH FREQUENCY TRIGGERING AND TRIGGER HOLD-OFF. As trigger frequencies increase above 40MHz better locking and increased ity can be obtained by pulling out the HOLD-OFF knob to the HF TRIG position. Triggering is then available to greater than 100MHz. Where pulse trains are displayed locking to a specific pulse may be achieved by rotating the Hold-Off control counter clockwise from the NORM position, until the sweep repetition rate corresponds with input signal repetition rate. Trigger hold off operates with the knob in or out. This technique may also be applied to modulated RF displays. DISPLAYED TIME BASE OPERATIOI Three types of display are available to view a waveform delayed in time by the 540 time base; there are MIXED, DELAYED SWEEP (B delayed by A) and DELAYED TRIGGER. (B trigger delayed by A). The horizontal DISPLAY selects the three modes together with A time base only and A intensified by B. 540 -2- 546540 546 In the Mix mode a combined trace displays the 'A' or main time base to the left, then at the point selected by the Delay Multiplier dial the delayed or 'B! ime base completes the trace at a faster speed, thus presenting a non~ magnified and magnified waveform simultaneously. With the Delayed Sweep mode no display is presented during the delaying period, but immediately following this period the B time base is displayed. If very long delay periods are involved > 10,000 :1 jitter of the waveform and the inherent jitter of the time base may produce an unstable display in this mode. of the delayed waveform is available, however, when Delayed Trigger is employed. In this mode again no display is presented during the delaying period, but immediately after the B time base is armed in readiness to receive a trigger signal . When this is received, B time base will fire and present a stable display even with delay periods of > 20,000-1. Operating of the delay time base facility is performed as follows:~ With all push buttons ‘out feed in a 10kHz signal to Ch. 1 amg r, set to approx. 4 div. amplitude and set A time base to 0.5m Sec/div. Five waveforms will appear per div. Align the start of the trace with the first graticule mark. Now set the B time base to 501 Sec/div. (vernier to Cal) and the 10 turn Delay Multiplier to 50. Turn the DISPLAY switch to A intensified by B, a section one div. long starting at the Sth div. (CRT centre) will be brightened. Turn the Delay Multiplier down to zero and then up to 100 and note how the intensified portion tracks accurately with the dial calibration between 10 and 100, return dial to 50, now turn the B time base Time/div switch and note how the segment becomes shorter at higher sweep speeds and vice versa. With the aid of both controls any section of the main display can be selected for delayed presentation. With the B time base returned to 50y Sec. turn the DISPLAY switch to MIX. The first 5 div. of trace will remain as before, but the remaining 5 divisions will be displayed at 50, Sec/div. Turn the Delayed Multiplier and note how the waveforms appear to "peel off" the main display. Changing the B time base speed will change the magnification of the waveforms on the right. NOTE: The point at which the transition from time base A to B occurs in the MIX display is slightly delayed to the start of the intensified section. This is shown in the illustration below: looy ---------- ---- ~~ 'B TRACE INITIATED BY MULTIPLIER SETTING 50 DELAY MULT START OF ‘18 7| ‘8 TB RESETS “© TB. starts | DELAY BOTH A&B OnTiL “B TIME BASE TAKES OVER FROM "A eae6.17 To display only the delayed or B time base, move the Display Switch to B delayed by A, The start point of the delayed trace is now accurately controlled by the Delay Multiplier dial. If for example a pulse is brought in line with the first graticule mark using the B delayed by A mode, the A time base speed is 0.5m Sec/div. and the Delay Multi dial reads 50, then the pulse is 0.5 x 5m Sec = 2.5m Sec from the pulse which initially triggered the A time base. The displayed pulse width etc., can be read off directly from the CRT screen - remember the displayed sweep speed is set by B time base. If in the previous example the trace is jittering due fo an unstable, signal or noise, ete., then the Display Switch is turned to its final step B trigger delayed by A. The B time base will not commence immediately after the delay instead the B time base will be set ready to receive a trigger pulse to i the trace fo ‘ensure a stable trace. B. TRIG. DELAYED BY A. The signal to trigger the B time base can be obtained from three sources, It can be selected from either intemal channel or from an external source. The three lower push buttons control the source and polarity of the trigger signal. The trigger point on the waveform can be selected by the LEVEL control along side the push buttons. When triggering to frequencies above 20MHz the Level Control can be pulled out to engage the HF trigger facility, This enables signals to 100MHz to be triggered. At the high end care must be taken with the level control as the adjustment is critical. OSCILLOSCOPE OPERATION FROM DC SUPPLIE The rear panel terminals for the DC input are isolated from the chassis. This enables supplies grounded either polarity or floating up fo SOV from ground fo power the 540 oscilloscope. Normal current requirement is approx. 1.5 amps. Input circuit for DC operation is protected against reversed polarity connection and will withstand over-voltage pulses to 40V peak. NOTE: The front panel Power ON-OFF switches does not disconnect the DC supply. This must be done by removing the supply externally. If both AC and DC supplies are applied simultaneously the source supplying the higher voltage will power the oscilloscope. This would enable a standby DC supply fo take over from the AC power in the event of an AC failure. If the input DC supply falls below minimum operating requirements the front panel lamp will blink on and off to indicate loss of calibration. BP 3 BATTERY PACK OPERATION. The battery pack attaches to the 540 Oscilloscope by the two rear top cover holding down screws. A three pin plug on a short cable mates with the socket on the rear panel. Two switches control the battery supply. On the pack itself the switch turns the batteries on or off. When battery operation is NOT required or they are not being charged turn the switch to OFF. When the batteries are to power the oscilloscope or require charging turn the switch to ON. eae 540 24 aeThe slide switch on the oscilloscope must be left in the USE position for all modes of operation and all power supply sources. It is only switched to CHARGE when required for that purpose, It may be switched from use to charge with power connected without damage. NOTE: The front panel power ON-OFF switch does not disconnect the battery supply, this must be done by the switch on the battery pack itself. Approximately 14 hours is required to charge the battery pack when it is discharged to minimum operating voltage. A fully charged pack will provide over 3 hours operation. Actual operating time can be affected by temperature ‘and age of batteries. When the batteries have discharged to theirminimum operating condition the front panel light will blink to indicate loss of calibration. Batteries should be recharged and not left on when light is blinking. For transport purposes the pack may be detached from the oscilloscope and carried separately by the handle provided. 540 REAR VIEW WITH BATTERY PACK FITTED BATTERY USE/OFF SWITCH POSITION FIXING ‘SWITCH, ON SOME PACKS SCREW UP-USE DOWN- OFF BATTERY PACK uses CHARGE SWITCH DC. INPUT- FUSE D.C. INPUT SOCKETS A.C. INPUT. FUSE ? BEAM INPUT ROTATION 540 - 25 - 546CIRCUIT DESCRIPTION The following circuit descriptions are divided (9.1) Vertical Amplifiers CH.1 (9.19) (9.2) Beam Switched Amplifier. (9.20) (9.3) Output Amplifiers. (9.21) (9.4) Beam Switch. (9.22) (9.5) Trigger Amplifiers. (9.23) (9.6 t0 Time Base (9.24) 9.18) (9.25 2 a re & J Bos LA | 3 is EG ae Bg. oN : we 8 a * 2 em 3Ind sO sO—4" into the categories shown below: (9.26) + and - 15V regulators. (9.27) Battery charging (9.28) Calibrator. Horizontal Amplifier. Z mod and blanking. RT. Power Supply Input. DC Stabiliser. low voltage indicator. DC-DC Converter. sng | 90 sive aio) x2 ° [| 33L DT p>tem BS y wvemen TRIG caren] Position AUTO.TRIG. TRIGGER AMPS, ‘« TRIG POSITION BW.D.540_ BLOCK DIAGRAM sor 540 54691 540 346 VERTICAL AMPLIFIER: Channel Input signals to the BNC jack are copacitively coupled via Cl & SIA to the attenuator when SIB AC=DC switch is open, or directly when it is closed. When S1Ais out (as shown) the input signal passes to $2 attenuator. When the switch is IN,the input is opened whilst the attenuator is grounded. The attenuator S2 comprises 4 sections which are used independently or in series to provide the selected attenuator step. In the SmV position no attenuation occurs and the signal passes straight through. At the 10mV setting R10 and R1I(together with R15 in parallel) divides the input signal by 2. Capacitor C10 and C12 divide the signal by 2 at high frequencies to maintain a constant bandwidth, C11 maintains a constant input capacitance for that step. The 20mV step brings in R12 and R13, (R15 always remains in parallel with the shunt element). This reduces the signal by 4. C13 and C15 compensate for higher frequencies and C14 maintains input capacitance. At the 50mV setting switch section $2B/R and S2C/F brings R6 and R7 into circuit fo provide a x10 attenuation. This section then remains in circuit and the x2 and x4 networks are sequenced with it to provide 100 and 200mV steps. When 500nV is selected the R6 and R7 section is bypassed and R2 and R5 is switched in by S2A/F and S28/F to attenuate the signal by x100, This section now remains in circuit on all ranges to 20V/div. The x1, x2 and x4 sections selected by S2D/F and R are cascaded to increase the steps through IV and 2V. At SV the xl0 section selected by $28/F and S2C/F is added in to provide x1000 attenuation, which together with the x2 and x4 produces the final 10 and 20V steps. From the attenuator the signal is taken through R14, RIO] & C101 limiting components to Q101 FET source follower. Protection for the input gate is provided by diodes D101 and 102 for positive overload spikes and D103 and 104 for negative overload, Q101 FET is closely matched to Q102 and provides an identical source impedance to the following stage, electrical and thermal balance necessary for long term display stability. DC balance is set by RV102 the front panel DC BAL preset control. RVIOI adjusts the current through the FET's to set the output at 40.7V. The input FET stage drives a matched pair of emitter followers Q103 and 104 which provide a lowimpedance to drive the ver put amplifier and Channel 1 trigger amplifier via R200 and R202. The amplifier gain vernier is placed across the input to Q105 and 106 transistors. R111, 113, 112 and RV103 gain controlforma double L network, Variation of RV103 shunt element controls the gain over a 2.5:1 range. Q105, 106, 107 and 108 are balanced series ~ shunt feedback pairs. Vertical position control RV104 in the collecbreircuit of Q105 and 106 varies the current drawn through each side and so superimposes. a positioning voltage on the signal voltage. RV105 preset centres the position control range. Channel 1 gain is set by RV106 which is accessible through the side cover. DC operating conditions of the stage are set by RVIO7. The output from QUO7 and 108 passes via R124 and 125 to the beam switching stage Q181 and 182. -7-9.2 9.3 9.4 Channel 2. The attenuator and amplifier circuits are identical to Channel 1 other tha inclusion of the Invert switch S141, This reverses the input signal connectic toQ145 and 146. Output from Channel 2 amplifier Q147 and 148 passes via R164 and 165 to the beam switch stage Q183 and 184. the s BEAM SWITCHED AMPLIFIER. The beam switch stage consists of two balanced amplifiers Q181 and 182 in Channel 1 and Q183 and 184 in Channel 2, Q18I and 184 share one common collector load Q182 and 183 share the other. Therefore if the emitter resistor controlling the current through Q181 and 182 is grounded and Q183 and Q184 emitter resistor is taken fo a potential higher than the base voltage (> 5V), channel 1 will supply the signal to the output amplifier and channel 2 will be cut off. If the converse takes place channel 2 will supply the signal and channel 1 will be cut off. Capacitors C182 and 183 neutralise leakage signals due fo stray and feed through capacitance and maintain high isolation between the channels. If both stages are turned on simultaneously the signals from both channels are mixed as in the ADD mode. As twice the current is drawn when both channels are on, additional current is supplied to the collector load by the vertical display switch section S231A which connects RI91 and 192 10 the +15V rail. The collector loads for Q181, 182 and 183, 184 consists of R188 termination resistor and L181 delay line, the resistors R189 and 190 terminating the delay line into the upper cascode pair. The x5 gain switch $181 in Ch. 1 switches RVI81 x5 gain preset into circuit across the emitter resistors of Q181 and 182. The preset is adjusted to decrease the emitter degeneration by a factor of x5 thus increasing the gain by that amount, The stage gain is less than unity at x1, increasing the gain by x5 switch reduces the bandwidth to 30MHz. The transistor Q181 and 2 (or 183 and 4) and Q185 and 6 are a cascode circuit with delay line between them. They form a series shunt feedback stage with Q257 and 252. The shunt feedback resistors and the following output stage are driven by Q253 and 254 emitter followers to maintain maximum stage bandwidth and output swing. The common emitter resistor of Q257 and 252, R257 returns to -15V via S50IA, beam find switch. When the switch is pressed it opens, and current must now flow through R260,limiting the current and hence the output swing from the stage fo such an extent that it will not deflect the trace off the CRT screen, OUTPUT STAGE. The CRT drive is a cascode stage with emitter compensation and a collector T Networks. Final bandwidth compensation is set by the network between Q281 and 282 emitters. BEAM SWITCH. The Beam Switch circuit which turns Q181, Q182 and Q183, 184 on or off consists of a low power TTL quad nand gate U231 and drive transistors Q187 and 188. - 28 - 540 546540 546 Selection of the required Vertical Display is controlled by 9231 The first two gates A and B are cross coupled as an edge triggered bistable switch. Gates C and D are coupled by $281C either as a free running multivibrator in the CHOP mode or as a pulse shaper with 2 Sec delay in the ALT mode, When the Vertical Display is set to Ch.1 , pin 5 of Gate B is grounded through R237 by $231C. Pin 6 goes HI biasing on QI87 so tuming off Channel 1. When 6 is HI, 2 is HI therefore 3 goes LO and turnsoff Q188 cutting off channel 2. When Q181 and 182 conduct Channel 1 is connected through to the output. When Channel 2 is selected gate A is grounded by $231C and the switching action is reversed. Alternate operation is as follows. A positive going gate pulse from the time base via C237 is switched by $2319 to gate C input. $231C grounds R234 but leaves the second input on pin 10 open, The +ve pulse drives gate C input Hi, its output falls to LO, pulling gate D input LO. In tum, its output rises for approx. 2u Sec. determined by C233 and R235. When gate D output falls after 2u Sec. it couples through C231 and C232 to trigger the bistable and change over the channel selected for display. The 2 Sec delay is sufficient to allow the switching to take place after the time base has blanked out the display during time base flyback. When Chopped mode is selected, R233 is grounded by S231C completing a bistable circuit of gates C and D. The free running frequency is approximately 500kH2 which triggers gates A and B, the bistable switch, this in turnswitches the channels 1 and 2 on and off. The switching signal to gates A and B is also taken through C235 and R239 differentiator circuit to Q231 PNP chop blanking amplifier. Negative going excursions drive Q231 into enduction during the switching transition and the resultant positive going pulses at the collector are applied via R204 and to the Z modulation amplifier Q601. Also switched in circuit in the chopped mode is resistor R309 which reduces the trigger sensitivity and so eliminates switching transients from the chopping signals from iating the trigger circuits. The remaining display facility is ADD. In this condition both channels conduct into the common collector loads. This is performed by grounding gate A via $231C, pin 1 is therefore LO, pin 3 is Hl and pulls current through R196 turning Q188 hard on and consequently Ch. 2 Channel 1 drive is however HI and would be turned off so R197 connected to Q187 base is connected to + 15V by $231B. QI187 turns on and provides a current path for Channel 1 which also feeds ifs signal to the common load. The additional current drain of the two stages conducting would change the collector voltages so R191 and 192 are connected by S231A to + 15V to provide additional current to the stage and thereby maintaining correct DC Levels. The +6V DC supply to operate U 231 is obtained by using the series current through the output stage in parallel with a 6V regulator 1C located on the delayed time base P.C. Board. ~29-95 cH IN cH2 IN TRIGGER AMPLIFIERS (CH. 1 and CH. 2). Each channel is directly coupled to its own trigger amplifier via coupling resistors. R200 and 2 to U201 for channel 1 and R204and5 to U202 for Channel 2, Each 1C has a gain of approximately x30, The output of U201 and U202 supply two trigger circuits each. U201 supplies the delayed time base (8) trigger circuits via R211/C205 and D201 and 202 diode gate and to the main time base (A) trigger gating amplifier Q201 directly and via D206/C207 to Q202. D206/C207 are included to prevent Q202 being cut off when the input signal has a high DC offset component. U202 similarly supplies B trigger via R212/C212 and D203 and 4 diode gate. ‘A’ trigger signals pass directly to Q204 and via D207/C208 to Q203. The channel selected to supply the delayed time base (8) signal is controlled by biasing on either D 201 and 202 via R218 connected to -15V or D203 and 204 via R219 as selected by S401C H. 1 or Ch. 2 switch located ‘on the delayed time base board. The main time base switching is controlled by $201 Ch. 1 or Ch. 2 selector ‘and $202 individual or mixed selector. $201 and 202 are mounted on the trigger amplifier board on the vertical amplifier board, When $202 is in the individual position (out) as shown on Drg. 1122, $201 selects the channel to supply the trigger developed across the common collector load R215 by connecting the amplifier emitters to +15V via R201. In the MIX condition $201 is disconnected and instead the collectors of Q187 and 188 are connected to the emitters. When Alternate display is employed Channel 1 and 2 will be switched to supply the trigger signals alterately ‘and simultaneously with the channel being displayed. Channel 1 amplifier U201 also supplies the Ch. 1 signal output at the rear panel. The signal passes via R751 to Q751 emitter follower which drives the ‘output socket via R756. DC Level adjustments to U201 is set by RV201 and to U202 via RV202. 187 To ares SIMPLIFIED TRIGGER AMPLIFIER SCHEMATIC. cH2 ¥ OUTPUT - 30 - FOR X-Y OPERATION 540 546,9.6 TIME BASE CIRCUITS. The time base is divided into the following sections and shown in their inter relationship below:~ “AL TIME BASE —B’ TIME BASE (9.7) ger Amplifier. (9.15) Comparator. (9.8) TV Trigger selection. (9.16) Trigger Amplifier. (9.9) Dual Bi-stable trigger. (9.17) TB Gate (9.10) Sweep gating. (9.18) Sweep Generator. (9.11) Sweep Generator. (9.12) Holf Off. (9.13) Auto. (9.14) Single sweep. w ‘A, TIME BASE ext ae ATIME BASE AUTO ciRcuIT Sec ceee edt + a reo eFast or ofos A353, suannins NPN ENP 2356 t ——wwi85_» care MATH 6375-361 invert Ts RY Bt STABLE 378 Sao, | youre suore eT ties COMPARATOR *a" TRIG aoa Bl Kal ae ‘e! tay ‘SKO1B B’ TIME BASE ‘MULTE ae ea R406 C450-456 ~ source > LOWER PP 02 aos a LEVEL aoe bwd 540 TIME BASE BLOCK DIAGRAM 540 546 eae97 9.8 9.9 (MAIN OR DELAYING) TIME BASE (Dig. 1124), Signals to trigger the A time base are selected by S301A from either the intemal source or via the external trigger input socket and emitter follower Q301. $3018 AC+DC switch places C302 and 303 in series with the signal when AC coupled or it passes directly through when switched to DC. $301C places C304 in series with the signal in the Fast position or connects directly to $301D in the normal position, Trigger Amp $301D selects the path through R308 and C305 when pressed for slow or couples directly to S301E in the normal mode. S301E + or ~ polarity selector connects either the trigger signal or the voltage from the level control RV301 via R311, 312 and 313 to the balanced input of USO1. Adjustment of DC level setting at the input of U3OI is made by RV302 and 303, The output from U301 is coupled to a balanced transistor pair Q302 and 303. The common emitter load of this pair R320 is taken to RV304 trigger sensitivity preset. Two additional circuits are also connected to RV304 to affect the trigger sensitivity. These are R309 which reduces sensitivity when it is connected to the + 15V rail when $231 Vertical Display switch is turned to the Chopped mode. $305 is the other connection to RV304, this is normally closed for gated trigger operation. It is opened in the HF trig. mode when the Trigger Hold Off knob is pulled out. This increases the trigger sensitivity. Q302 is directly coupled to U302A bistable trigger whilst Q303 is taken through D304 to U302B. This is to enable the TV sync. separator to be switched into circuit via the diode gates D303, 304 and 305. TV TRIGGER SELECTION. When 301F is switched as shown on drawing 1124, Q304 base is reversed biased by R323 so that an input signal applied via R319 and C311 will not take it into conduction. When S301F is pressed to select TV, it connects Q304 base to #8V via R322 biasing it into conduction. $30IF connects Q302 collectors to via D305 and R321. This reverse biases D304 and prevents any signal on Q303 from triggering U302B. Negative going video signals applied to Q304 base cause the sync pulses to drive it hard into conduction. This causes Q304 to pull current through R324 collector load. For frame pulses the slow button must be pressed to filter out line pulses but leave the longer frame pulses. The sync. signal cause a negative signal to be developed which biases D303 into conduction. ‘As U3O2A latches fo the first video component to pass through Q302 after reset, this may be a line or frame pulse, U302B is primed ready to latch when a negative going frame or line pulse pulls D303 into conduction, DUAL BI-STABLE TRIGGER. U302 is an ECL dual OR-NOR gate, each section is connected as a bi-stable trigger by R326 and R328. U302A output is coupled into one input of U3028 and both gates have a common input via pin 13, In operation with no input signal and RV304 trigger level adjusted to centre, the collector of Q302 and 303 will be positive to the input level of U302. - 32 - 540 5469.10 540 546 The gate input via pin 13 is held LO by 1C-308A to which it is connected by R341. When @302 is pulled into conduction an input signal, pin 8 of U302 is pulled down. Current will flow through R326, @ voltage drop develops and the input goes to LO. The output on pin 6 follows and U302 latches in the LO state taking pin 14 of U302B LO also, When the input trigger signal reverses phase it causes Q303 to conduct, biasing D304 on and pulling current through R328. As pin 16 goes LO, the OR output on 3 will also go LO and latch in, Both triggers are latched to low state and cannot recover until an input to one gate ~ pin 13 in this case, goes Hl when it is reset during the hold off period. SWEEP GATING, ‘As the OR output goes low the NOR output on pin 2 goes Hi . This voltage difference Is applied across the emitter base junction of Q308 inverter driver stage. The collector load of Q308 is R339 and R340. When Q308 emitter base junction is reversed biased it is non conducting and U303B NAND gate will have one input level LO by R340, This will result in the output on pin 6 being HI, Five circuits are activated by U303B output. (1) Altemate trigger initiated by U302B going HI via R354. (2) Unblanking of the CRT is switched by the output going LO, via R355. (3) The gate output is taken through R356 to the rear panel socket. (4) The Ready light LED is gated between U303B and U303A outputs via R349 and 342, (5) The sweep circuit is gated on and off via R351 and diode D310. SWEEP GENERATOR. A positive going sawtooth waveform is generated by a Miller feedback circuit consisting of Q310 FET source follower, Q311 Miller integrator followed by Q312 emitter follower. When U3038 output is HI, D310 is biased on and pulls Q310 gate posi pulls Q311 into conduction and its collector falls. @Q312 follows and its emitter falls until D309 connected between D310 and Q312 emitter is pulled into conduction. Current will now flow through R351, D30?, R360, RV306 and R361 to-15V which reduces the voltage on D310, on Q310 gate and hence on Q311 base. Conduction reduces in Q311, its collector rises slightly and Q312 follows until a quiescent condition is reached where the forward bias on D311 is just equalled by the reverse bias via D309 and the divider to -15V. When RV305 is correctly set this will be +IV at the emitter of Q312 and pin 7 of the A and B time base P.C. Board interconnecting socket. This The arrival of a trigger signal at USU2 will cause it to latch as previously described and the outputs on pins 2 and 3 will reverse, biasing Q308 hard into conduction. The junction of R339 and R340 will be pulled positively, gate input 4 of L803 will HI (assume gate 5 is H} ), output will drop to LO and D310 will become reversed biased. The Miller circuit is now left the gate of Q310 taken to a negative voltage as determined by the timing resistor R370 selected by S304D wafter of the Time/Di range switch and the setting of RV472 vernier control. = 33 -9.12 Q310 gate will therefore be pulled negatively, however a timing capacitor as selected by S304E is also connected to Q310 gate and via the switch back to Q312 emitter. The fall at Q310 gate is amplifier and inverted by Q311 at its collector and is followed by Q312 and so coupled to the timing capacitor. The effect of large amount of negative feedback is to linearise the waveform resulting in less than 0.2% non-lineaity at the generator output over most of the timing range. The timing capacitors are changed over the lower ranges every sixth step which Tepresents two decades of timing change. The 1,2,5, 10 timing changes are produced by resistors selected by S304D wafer. The highest speeds have individual preset capacitors to enable stray capacitance etc., to be compensated by capacitor adjustment. The sweep voltage continues to rise at the output of Q312 until the take off point on RV306 in its emitter load rises to + 1.4V. D313 and Q30? now conduct to ite the trace termination switching, HOLD OFF CIRCUIT. U303 A and C gates and Q309 are cross coupled as a mono-stable. C370 - 374 with C321 in parallel as selected by $304C set the time of the mono stable period. When Q309 conducts at the positive excusion of the trace it pulls U303C input HI, its output becomes HI, U303A input follows and its output in turn falls to LO. This is coupled through C321 and any parallel capacitor on S304C to pull Q309 input HI via D311, this latches U303C output to a high state until C321 etc., discharges through R353. This period of time is selected to be longer than the Miller integrator fakes to discharge the timing copacitor and to settle to ina quiescent condition, Hold off capacitors selected by S304C wafer are changed to suit the timing capacitors and to minimise lost time during hold off at higher frequencies. The switching signals generated by U303A and C are used as follows: From pin 3 of U308A, the output pulse is coupled by R341 to pin 13 of U302A and B dual Bi-stable trigger. This positive output pulse unlatches U302 and holds it until the delay period is complete. @308 becomes reversed biased and in 4 of U302B falls to low, the circuit is then in readiness for the next input trigger signal. The HI output from U303A (pin 3) during hold off is inverted by U303D, causing U303B output to go HI, D310 is forced into conduction, @310 gate goes positive, its source follows faking Q311 base positive. It conducts causing its collectar to fall rapidly. @Q312 follows and the selected timing capacitor C375- C381 is discharged through the low impedance path of U303B, R351 and D309 in series going to +4.5V and R360, RV306 and R361 in series connected to ~ 15V. The discharge is halted when D309 conducts as previously described. At the end of the hold-off period U30BA goes LO and U303B output goes HI, but as pin 4 of USO3B is now low U303B remains with its output on pin 6 Hl, until the time base is initiated by the U302 latching, Q308 conducting and switching U303B output from HI to LO thus disconnecting D310 and allowing the sweep circuit to start. = 34 - 540 5469.14 9.15 540 546 The LED Ready Light on the front panel is connected between U303B output and U30BA output. A voltage only appears across it when U303B is HI ~ between sweeps and when U303A is LO after the hold off period, i.e, the period when the time base is ready, awaiting a trigger signal. AUTO CIRCUIT, 305, 306 and 307 are responsible for the auto action. When the level control RV304 is pushed in $302 is opened leaving capacitor C318 charged to H5V. It proceeds to discharge through R334 and if U302B trigger gate Is not switched by an incoming trigger signal it will continue to discharge until D306 conducts. This in turn will cause Q307 to conduct and draw current through R347 pulling pin 4 of U303B HI, its output drops fo LO and the time base is initiated and will continue to free run til U302B latches. When this occurs a trigger pulse is fed via C314 fo Q306 base. It conducts, pulls Q305 base positive, Q305 conducts and pulls Q306 base negative and the two transistors latch together and charge C318 towards the +15 rail, When the capacitor is charged the current through Q306 is insufficient to hold Q305 in conduction s the latch releases and C318 again discharges until another trigger pulse latches Q305 and 306, and the action is repeated. If trigger signals continue to switch @305 into conduction C318 will remain charged ‘and 307 will remain non-conducting, however, in the absence of trigger signals Q305 will not conduct, C318 will discharge within 0.3 seconds approximately, 307 will conduct and via R347 will pull input 4 of gate U3O3B to its high state irrespective of the action of Q308 and initiate the next time base sweep. At the end of the trace when the reset circuit next operates U303B output will only be switched to HI by the hold-off circuit via U303D and immediately it completes its task both inputs to U303B will be HI, its output will fall and @ sweep will be initiated. A free running trace results not locked to any trigger signal ond will continue to do so until trigger signals again switch U302 and hence Q305 into conduction to recharge C318 to bias Q307 off. Another output of U302A gate is taken via R342 to C413 on the delayed time base board to reset the B time base hold off gate. SINGLE SWEEP. Single sweep operation of A time base is obtained by shorting out C321 and all other hold off capacitors by $301G/A, converting U303A and C from a mono stable to bi-stable. When this circuit is latched by Q309 conducting at the end of the sweep period no further sweep can occur until the circuit is unlatched by depressing the reset button $303, This places C329 across the input of Q30?, The charging current which will flow into C329 will pull Q309 base to a low state. U308C output will rise and unlatch the bi-stable circuit in readiness. for the next sweep. B TIME BASE Comparator. The point on the trace at which B time base fires isset by Q402 and @403 and U403 comparator. This circuit is a high gain differential amplifier which feeds comparator 1.C U403. The sweep waveform from Q312 emitter is connected to Q402 whilst the comparison voltage across RV405 Delay Multiplier is fed to Q403. ~35-When the Horizontal Display switch is in position *A' only, Q404 will be pulled hard into conduction by its base resistor R430 being taken to -15V by switch $4028. This causes Q404 to saturate and pull the base of Q403 up to almost + 15V, it will therefore remain conducting irrespective of the input to Q402. When $402 isswitched to all other positions Q404 is turned off and Q404 and 403 are free to conduct. In the quiescent condition when A time base is blanked out awaiting a trigger signal Q402 will be cut off and Q403 will be conducting. Pin 4 of U403 will be negative fo pin 3 and the TTL compatible ouputs will be Hi at pin 11 and LO at pin 9. The HI output on 11 will pull D404 into conduction and hold the input of U402A HI in the reset condition. The LO output on 9 will reverse bias diode D405, The circuit will remain in this condition until the comparator is switched over by the A time base signal. TRIGGER AMPLIFIERS AND BI-STABLE LATCH. Input signals are selected by S401B from an extemal or the intemal source. Q401 emitter follower presents a low output impedance for signals driving U401 differential amplifier and also provides a DC voltage shift which is adjusted by RV401. S40IA selects the input polarity by coupling the signal input and level select voltage to either pin 1 or 14. The outputs of U401 are taken through diodes D401 and 402 to direct coupled Hex Inverter gates connected as latching schmitt triggers. As the B time base trigger is only required for the B trigger delayed by A mode it is rendered inoperative in all other conditions by disconnecting the negative voltage supply to 1C D401. This prevents U401 being able to pull enough current through D401 and D402 to latch the bi-stable circuits. The action of the circuit is as follows: Assuming pins 1 and 13 are HI. With the arrival 0s a positive going signal on Pin | of U401 the ampl will conduct pulling pin 1 low via D401. Pin 2 and 3 will become HI causing the output at 4 to switch to LO. This signal is communicated by R406 fo Pin 1 pulling it LO thus latching the circuit ina LO state. The second pair of inverter gates C and D have been held by diode 403 which prevented current through D402 changing the state of gates C and D. However once pin 4 switches to LO, D403 is disconnected leaving gates C and D free to be controlled by U401 and D402, The following half cycle of the trigger waveform will cause pin 7 to rise and through the differential action at the 1C amplifier, will cause pin 8 to fall and make D402 conduct. The same sequence of events will follow. Pin 13 will go towards LO, 12 and 11 will go HI, Pin 10 will be LO and via R408 the inputpin will be pulled LO thus latching the circuit in the LO state. The trigger circuit will remain in this state until it is reset by a pulse from the comparator via D404 at the end of the sweep. As can be seen the trigger circuit also forms the time base gate and consequently reduces the delay time in initiating the saw tooth sweep down to a few nano seconds. Trigger bandwidth is increased by the very high speed switching inherent the TTL inverter gates. Increase sensitivity is obtained when switch $403 remove closed in the HF trigger mode when the Level control RV40Z is pulled out. = 36 - 540 5469.18 540 546 Output from the latching trigger circuit is taken from Pin 12 and drives another section of the same 1C gate U02E via two resistors R417 and 418. The resistors are used to inject the signal from the comparator and from D406 to terminate the sweep. GATING CIRCUITS $402A wafer of the Horizontal Display selects the mode of triggering the B time base. As shown in drg. 1125, $402 is switched to A time base and Q404 is held on by R430 preventing B time base from operating, The next position of $402 (INTEN) connects diode D405 from the output of U403 comparator to the junction of R417 and 418, @404 base is released from the -15V rail allowing Q403 base to fall to the voltage on RV405 Delay Multiplier potentiometer. When the A time base sweep voltage applied to Q402 base rises to the potential on Q403 base, Q402 will become reversed biased, D408 will disconnect, Q403 will conduct and its collector will rise above ground potential. U403 comparator input to pin 4 will rise above 3 switching the outputs on 9 and 11. The output on 11 will have no effect but the change from LO to Hl on 9 will make D405 conduct and via R418 cause U402E input to rise, its output will go to LO to initiate the B time base. D410 is disconnected permitting Q406, 407 and 408 Miller circuit to sweep, As B time base is running faster than A the B sweep will terminate before A. SWEEP GENERATOR. The voltage on RV40B controls the end of the sweep when it rises to + 1.4V and biases Q405 into conduction. This pulls input 5 of U402F LO its output rises and pulls the base of Q405 positive, and latches the bi-stable circuit. D406 conducts and pulls input 9 LO, a Hi appears on 8 which via R422 pulls D410 into conduction. The gate of source follower Q405 is driven positively, this pulls Q407 hard into conduction by the direct coupling of RVAQ7 from Q406 source. Q407 collector falls, Q406 emitter follower falls until D411 conducts. During the return trace the timing capacitors are selected by $3048 are discharged by the current flowing in D410, R422 and R436, RV4OB and R437, the CR value determining the fall time of the circi When the emitter of Q408 falls to approx, + 3V D411 conducts and current flows through R422. D411, R436, RV402 and R437 to -15V and will continue to flow until D410 is pulled to a lower conduction level and a stable quiescent state is reached. The output of U402E is also connected to the unblanking circuits via R424 and D475 diode to S402A/1, $4028/\ applicd-15V through R474 to pre-bias the 'B' unblanking waveform negatively with respect to 'A’ unblanking level. The resultant unblanking pulse fed out to the Z modulation amplifiers causes an increase in trace intensity during the period of the B time base, producing @ display with an intensified section. In this position of $402 only the A time base sweep waveform is selected by $4028/1 via D471. The bi-stable latch U402F and Q405 js reset at the start of the next A sweep by a negative pulse from U303A via R342 and C413 to Q405 base. at G9.19 The third position of S402 selects MIXED display. 4028/1 disconnects B intensified unblanking but sweep signals from both A and B time bases are connected to the horizontal amplifier by $402B/1 via diodes D472 and D473. The gating circuit is identical to the Intensified condition in that the B time base is initiated when the comparatorswitches and U402E output goes LO. Once B time base is initiated the sweep waveform on Q408 emitter will ‘appear on D473 anode and take it positive. D472 is already conducting as A time base output sweeps positively towards +13V. At a point in time determined by thesetting of the Delay Multiplier and the B time base range setting the signal on D473 will rise positively to D472 thus cutting off the sweep from A time base and feeding B time base through to the output amplifier instead. The resultant display is that the slower A time base appears on the left hand side of the display followed by the higher speed B time base, See sketch on Page 23. At the end of the B sweep the output of Q405 is fed to U402E to end the sweep and then the output of U402F via C411, D407 and 402C/2 to the base of 309 to end the A sweep also. If the Delay Multiplier is set near the maximum delay and there is little difference between A and B sweep speeds, A time base may finish first in which case U303A gates Q405 via C413 to end both time bases. The fourth step of S402 is B time base delayed by A. The only difference introduced by the switches is that only B sweep is selected by $4028/1 and B unblanking only by S402A/1. Therefore no display will be present on the CRT until B time base starts when unblanking the CRT displays B sweep only, The final position of $402 is B trigger delayed by A. Two changes to the switching occur, UA02E is not pulled into conduction by U403A, instead diode D404 releases U402 and allows the trigger signal generated by the ‘BY trigger circuit U401 and U402 to pull U402E input HI. This causes its output to go LO and start the B sweep. $4028/2 connects R410 directly to ~15V thus bringing the trigger circuit into operation, Initiating of B time base by @ trigger input can only take place when U402 clamp voltage via D404 is removed. This only occurs when U403 comparator output on 11 goes to its LO state. As pin 7 of U401 will normally be in a LO state U402 A and B will latch in to a LO when D404 disconnects thus releasing D403 leaving U402 C and D latch ready to switch on receiving the next trigger signal when the outputs of U401 will reverse, pin 7 will go HI and 8 will drop to LO. HORIZONTAL AMPLIFIER. This circuit consits of a shunt feedback input stage Q501 driving a balanced stage Q502, 503 followed by emitter followers Q504, 505 which drive the complementary output pairs Q506, 507 and Q508, 509 with overall feedback around the balanced amplifier. Six inputs are taken fo Q501 base in addition fo the collector to base feedback resistor R513 which converts Q501 to a current input stage stage with very low input impedance, These are the 'X' input via R501, ine and coarse position controls, via R502 and 503, trace centering voltages R504 and 505 and the time base input via R510 and RV506. ~ 38 - 540 5469.20 540 545 The time base signals are selected by $4028/1 Horizontal Display switch and applied to Q501, Horizontal position control voltages from RV504A and B are mixed with the sweep waveform along with the centering voltages from R504 and 505. The latter resistor is disconnected when the X-Y latter is pressed. X input signals are shorted to ground by $401B when the time base is used but opened in the X-Y mode. C501 across the X input line corrects the phase of the signal to match the vertical channel which is delayed approx. 100 n Sec by the delay line, The inverted signal at Q501 collector drives the base of Q502. Q503 base is retumed to +6V via R518 and 517 to provide DC balance. The emitter resistors of Q502 and 503 are the negative feedback resistors R521 and 527 from the driver stage. The amount of feedback and hence the stage gain is set by R516 shunt resistor in the XI mag. position and R515, with RV505 in series are switched in parallel with R516 at x10 mag. Whilst Q502 is a bose driver stage with emitter feedback, Q503 is emitter driven via R516 and 515/RV505. Drive signals for the output are developed across collector hoods R522 and 523 with RV508 balanced control between them. Current through the stage is set by RV507 under normal conditions but when S5O1A Beam Find button is pressed RV5O7 is opened and a reduced current flows through R 54010 restrict the horizontal deflection to within screen limits. Emitter followers Q504 and 505 provide alow impedance drive for the output stages. 506 and 507 are a PNP-NPNoomplementary stage driving the X2 plate. Like wise Q508 and 509 drive the XI plate. Both run at a quiescent current of approx. 5mA which is set by R530, 529, 531 and 520 for the X2 stage and R538, 536, 542 and 528 for the XI stage. If a positive going input is applied to Q507 to turn it on, Q506 which receives at high frequencies the same drive signal via C514 will be tumed off, Thus reducing the load and assisting Q507 in charging the capacitor load formed by the deflection plates. In a similar manner negative going signals will tum Q3507 off and Q506 ‘on when the X2 plate is being driven positively. The drive signals to Q508 and 509 are similar to the X2 stage described, Diodes D503 and 506 prevents the output stages being driven into positive saturation whilst D504 and 505 prevent Q507 saturating, Output limiting is also set by D501 and 502. Trace linearity is adjusted by C508, C510 and RV507. Z_MODULATION AND BLANKING. The Z modulation stage consists of Q601 common base input stage which presents a low input impedance to the six input signals available to modulate the CRT trace. Output signals developed across collector load R607 are applied through diode D601 to Q602 emitter follower and mixed with the feedback signal via R611 from the output stage. The complementary pair output stage Q603 and 604 operate at a quiescent current of approx. SmA as set by R614, 609 and 610 around 603, During the return trace the output of Q603 and 604 is held low to blank the CRT. The negative going unblanking pulse from S402A/1 switch deck is fed to Q601 via R602. ~ 39 -9.21 9.22 This increases the current in Q601 and produces a negative fall at its collector. 602 emitter falls cutting of Q604 and pulling Q608 hard on. The high frequency component of the waveform is capacitively coupled to the CRT grid via C606. The DC component of the CRT grid drive is developed by modulating a 22kHz rectangular waveform and then demodulating it at the CRT cathode. The rectangular waveform is taken from the DC-DC converter transformer winding that supplies the +117V rail. |t is taken through R621 and then clipped on the positive excursion by D607. RV606 sets the clipping level providing an intensity range control, D606 isolates the switching waveform from the Z modulation amplifier output. It controls the amplitude of signal present at the junction of D606 and 607, The more positive the output of the amplifier the smaller the signal amplitude with respect to ground. When the modulated waveforms are coupled by C607 to the CRT cathode they are DC restored by D605 and then coupled through D604 and R620 to be combined with the AC coupled component at the CRT grid. CRT. The cathode ray tube is operated with an overall potential of 12KV. The cathode supply from a half wave rectifier D672 followed by a two section RC filter C663, R615 and C605. The PDA voltage is supplied by a 5 stage multiplier through a C and R filter consisting of R622 and the capacity of the screened cable used to provide the final connection to the P.D.A. connector. CRT focus by RV602 and astignation correction by RV604 are front panel controls whilst RV603 geometry preset is internal on the rear P.C, board near the CRT socket. POWER SUPPLIES The power supply system in the 540 Oscilloscope is designed to provide operation from either AC or DC power sources on a rechargeable battery. POWER INPUT AC input passes first to the power switch on the Intensity control then to the 117 = 235V changeover switch located on the transformer bracket. The transformer T651 has secondary windings consists of a main winding supplying a bridge rectifier D651 and two 6.9V windings. One supplies the graticule lights and the tine voltage for the time base trigger via R672. The other winding forms an extension with the main winding to increase the supply for battery charging. Rectifier D651 operation is self evident when the USE/CHARGE switch however when ‘charge’ is selected the bottom pair of diodes C and D in D651 become reversed biased and D655 and 656 become the lower half of the bridge circuit, D656 is switched by S652A to be in ‘parallel’ with C and D655 is switched by $6528 in ‘parallel’ with D. The rectified output of either supply is filtered by C652 and C453. The external DC supply input is connected in at this point via D658 which isolates the input if it is below the rectified AC input and also prevents a reversed voltage from damaging the circuit. In a similar manner the battery is connected in via D657. It must be switched off by the battery pack switch when it is not required fo operate the oscilloscope. in USE * Serial No's below 33291 only. - 40- 540 5469.23 9.24 9.25 9.26 540 546 DC_STABILISER. The rectified AC or DC supplies are stabilised at 17. 5V_ by the regulator, U651, inverter drive stage Q652 and 653, emitter follower driver Q654 and series pass transistor Q655, The 1C U651 is connected across the stabilised output, the reference voltage connects to the Inverting input whilst the Non-Inverting input picks up a voltage on the divider chain R655, RV651 and R656 connected across the stabilised output via switch S652A. Output voltage is adjusted by RV651. When S652 is switched to Charge, R656 is disconnected leaving D673, R657 and R652 to set the output voltage in conjunction with RV651 and R655 at 28V, The output control voliage from U651 developed across R658 is applied to Q652 where it is inverted at the collector across R659 and connected fo the base of emitter follower Q654. This stage in turn drives the series pass transistor 655. LOW VOLTAGE INDICATOR. Q658 base drive is obtained from the divider R666 and R665 across Q655 and under normal operation Q658 is held in conduction pulling its collector up to the negative unregulated rail, This in turn via R662 pulls pin 3 non inverting input of US52op. amp negatively. The output at 6 follows and the front panel LED D691 lights by the current flowing through it via R670. If the unregulated input drops to less than 1.2V across Q655, Q658 becomes reversed biased allowing its collector to fall and pin 3 takes up a voltage set by divider R663, 664 and R669. The inverting input is connected back to the output through R668 and has capacitor C457 returned to the positive rail. If the output is latched negatively C657 will be charged negatively until it rises above pin 3 voltage. The 1C output will suddenly invert and settle near the positive rai C663 will be charged in the opposite direction and when it reaches the voltage on pin 3 the state will be reversed. The front panel LED will be switched on and off by U652 at an approx. 1 sec rate until the correct input voltage is restored. DC = DC CONVERTER All the DC supplies required by the oscilloscope are supplied through a DC to DC converter consisting of Q656 and 657 with transformer T652. The push pull primary has separate feedback windings for Q656 and 657 and a starting base feed resistor R661. Both the base feed resistor and the centre tap of the collector winding is taken to S652A Use/Charge switch to the positive (OV) rail in the Use position. When Charge is selected the converter supply is disconnected. The multiple secondary windings are rectified by high speed diodes to supply low and HI voltage windings and EHT. The CRT heater supply is not rectified, In the event of a short circuit on any rail the converter will turn off or squegg audibly. The CRT modulator voltage is taken from the 55V rail ahead of D664, passed through R671 and then applied fo the blanking circuit. + AND -15V REGULATORS, Additional filtering and regulation is provided for the + and -15V rails by regulator 1C's U68] and US82, Output voltage is adjusted by RV681 from the +15V and RV682 for the -15V rail. An additional CR filter R681/C681 is incorporated in the +I7V rail to reduce ripple -level. -41 -9.27 9.28 BATTERY CHARGING. With $652 switched to charge,the unregulated supply is +34V approx. The regulated supply is set by RV652 to 428V and is applied via D659 and then through R651 to the battery. 651 has its base and emitter connected across R651 so that any current flow that causes more than 0.6 to 0.7V f0 appear across R651 will cause Q651 to conduct. It will pull the voltage at the inverting input of U651 negatively, reducing the output voltage of the regulator until the charging current is reduced to just maintain Q651 in conduction. A constant current is maintained to charge the battery until its own internal impedance reduces the current demand as it becomes fully charged. CALIBRATOR. Q701 and Q702 comprise a free running emitter coupled multivibrator operating at approximately IkHz. The output voltage across R706 is limited in a positive direction (when Q702 cuts off) by the divider action of D701, R706 and RV701, the output calibration control, In a negative direction Q702 pulls the collector below ground, but D701 cuts off and the output signal swings between ground and approximately + 1.8V. 1V p-p output level Is set by Rv701. page 540 54610. 540 546 ALIGNMENT AND MAINTENANCE. The following chart suggests steps to be followed to localise a fault causing instrument failure. iP CONABR EH Non operating. Check input supply. Check 117 = 235V input range switch. Check fuses. Check USE/CHARGE switch. Switch to USE. ficator OFF, Check through regulator. Ponel i Panel indicator ON. Audible buzzing indicates converter is overloaded. Remove rear panel check 22kHz signal on rear panel transistors. Check all voltage rails + 6 Red/White wire, +15 Yellow - 15 Violet, +116 Red. Press trace find and check vertical and horizontal position. TB OK. NO VERTICAL. i. VERTICAL OK, NO TIME BASE Make sure Horz. Display switch is jon ond LEVEL Switch to Ch. 1 if still faulty, Check Ch. 2 in ‘At only po: knob is pushed in for AUTO. If one Ch. faulty check that input ii. Press X-Y button only. Spot stage for unbalanced amplifier stages. should be present and Horizontal NOTE: Input FETS and transistors Position should move spot. must be replaced as matched pairs in vertical amplifiers If faulty check Horizontal Amp. Check DC BAL adjust as on P25. iv. If okay, check time base. Both faulty check, delay line for v. 'A' time base okay No. B. T.B, ofc. check comparator outputs when switched to INTENSIFIED, Check output drive stages for balance. vi. If okay, check B time base If correct though to deflection plates, circuit. check CRT. POWER SUPPLY If faults are located in power supply board, it may be unplugged and slipped out of frame for access to all components. Short circuits to output of converter will cause circuit to shut down or emit an audible sound which indicates o fault condition, ayebwd 540 COMPONENT LAYOUT POWER SUPPLY HORIZONTAL SECTION AMPLIFIER ce MAIN ‘At TIME BASE U302 asor 3° avsos evaos U708 D651 RV606 Front RV603 U231 $231 A-D_—RV202 oe CRT BLANKING RV201 S201 & 202 TRIGGER AMPL. . & DISTRIBUTION SECTION BOARD TOP VIEW ae CHI. CAL DELAY 255 eae 182 RyI06 LINE & 2 RVIOlCH.1 ATTEN. Front RV701 ares ATTEN. VERTICAL AMPLIFIER SECTION L.H. SIDE VIEW ~ 44 -bwd 540 COMPONENT LAYOUT POWER ‘SUPPLY D655 SECTION EHT D658 Multiplier Fo52 \ cbse Fés! 657 860 1652 aide10.3 10.4 ALIGNMENT AND MAINTENANCE The following details cover almost the entire factory alignment procedure, and will therefore allow realignment of any section following a component replacement or periodical recalibration. Only the section required for the service being performed should be followed, do not re-set other controls. NOTE: To assist in checking voltages and tracing leads the following wire colours have been adopted:~ -15V Violet, ground - black, +6V_red/white, +15V Yellow, + 116V red. ‘A.C. Power Line (before on/off switch) Brown ~ active, blue - neutral and yellow/ green - ground, A.C. Power after on/off switch, Brown/white and blue/w In the power supply/rectifier compartment at the rear red is positive (OV on is and blue is negative (usually between -18V and -32V). All D.C. Measurements should be made with a 20,000 9/V meter or a DVM with > 10MQ input impedance. Oscilloscope waveforms are obtained using a 10:1 high impedance probe. Power line ripple can be checked with a 1:1 probe but in each case the ground lead must be used to minimise noise or interference. To remove covers to obtain access, first remove all forms of power source from the instrument. The top cover is removed by unscrewing the two rear side serews and the front top screws. It is then pulled to the rear and upwards. The bottom cover is removed by unscrewing the four feet and lifting off. The rear panel slides from behind the heat sink when the four fixing screws are removed. Internal shields are detached by removing the holding screws. TEST EQUIPMENT The following instruments are required for a full ali servicing requirements a meter, oscilloscope and Voltage Calibration from SmV to 200V p-p at IkHz. Square Wave output accuracy > 0.2%. Time Calibrator from 1Hz to 100MHz accuracy > 0.1%. 1 nano second rise time square wave 250mV p-p MHz rep. rate. (All above instruments are available ina Bradley Medel 192 Oscilloscope Calibrator). Low frequency oscillator 1Hz to IMHz. (bwd 141 and 160 generators). generators). H.F. generator 50kHz to 100MHz constant amplitude output (Tek 191). H.F. generator to 150MHz for trigger check. Oscilloscope ImV to 20V/div sensitivity, time base to 100n Sec/div and triggering to > 50 MHz (bwd 540 or bwd 525), ALIGNMENT AND CALIBRATION. nal source are sufficient. « Power supplies. The converter type supply in the bwd 540 has a major advantage cover multiple regulated supplies in that it will turn off all rails if a short or heavy load is placed across a rail or even between rails. tee 540 546Under certain conditions it will squeg and emita buzzing sound giving audible warning of a faulty condition, (a) Initial resistance check, values shown are approximate +6V rail 6002, + 15V 4002, - 15 400, 470 8000, +116 8002, - 1360V O/C. Across input filter capacitor 6K8. Red DC input terminal to chassis 10KQ, Across a/c input 40Q (235V) 202 (117V). (b) Remove sockets on two MJE 3055 transistors on rear panel. Set USE/CHARGE switch to USE. Connect AC power input to a variable voltage transformer ‘and Increase input to SOV AC (235V input) 25V__(117V input). Voltage a/e main filter cap approx. 6.5V. Approx. 5.5V across C 656 on Power Supply board, Increase input to 100V AC (235) or 50V(117) voltages should increase to 12.5 and 12.2 respectively, Increase input lo 200V (or 100V) and set voltage o/e C656 to 17.4V by RV65I at top of power supply board. 17.4V should remain constant to 270V AC (235V) or 125V (117V) input. NOTE: Alll above measurements can be made WRT the Red DC input terminal on rear panel which is the OV rail of the power supply, but is isolated (via 10K) fram the chassis. (©) Retum input voltage to 0, switch to CHARGE. Follow above procedure. AC input 50V. W o/c filter. 8.5V a/c C656 AC input 200V set RV652, For 29.5V a/c open circuit. Check voltage remains constant up fo 270V input. Connect a 10002 1W resistor 9/¢ battery socket pins and finally adjust RV 651 for 28V a/c the IK resistor. (d)__ Return AC input to OV. Refit sockets on MJE 3055 transistors. Switch to USE, Connect an oscilloscope input fo one MJE 3055 collector. Set scope attenuator to 0.5V/div, use 10:1 probe and TB set to SQ Sec/div. Increases AC input, at approx. 90V (235) or 45V (117) a trapesoidal waveform should appear on monitoring oscilloscope 3 div. high and 1 div./vaveform. Check all DC rails to verify diode and regulator operation. 46V = 3V, +15V = 3.5V, =15V = 4,2V, 455V = 430, 4117V = 455, CRT cathode = -650V. Continue increasing AC input and check each 50V (25V) that rails remain in step with each other. At 200V AC input (100V) + 55V should be correct. Set +15V by RV6BI and -15V by RV682, located on rear lower P.C. Board. Check all voltages (other than P.D.A. which requires a special probe) and that converter signal is approx. 22kHz and 35V p-p on MJE 3055 collector. VERTICAL INPUT AMPLIFIER. (e) Set RVIO} and RV141 at front of board for =0.1 between chassis and connections to Vemier controls. Set front panel DC balance contro! for zero volts across vernier control - control to CAL. -47 - 540 546Check balance exists at each stage in each input amplifier, then adjust RV107 for 3.9V average to chassis on R124 and 125 and RV147 for 3.9V on R164 and 165. (f) VERTICAL OUTPUT AMPLIFIER. Switch Vertical Display to Ch. 1 then check voltages through stages compared fo circuit and finally set Q281 and 282 output stage collectors to 439V with RV253 average to chassis. Use position control to equalise voltages. Set RVI05 fo equalise trace movement above and below centre by position control . Check channel 2 then centre trace by RV145-DC Balance is set by turning the vernier control counterclock, centre with position, turn vernier to CAL, recentre with DC bal, repeat as necessary. (g) ATTENUATOR ALIGNMENT._ oo 0 cu | ce oO 8 CHANNEL oo 0 1 cr cn | co cu. lunder ATTENUATOR LAYOUT @-s4 cé5 ces | cB 53 under CHANNEL e oo 0 c62 cet} c56 | 5 0 o oo 8 000 Attenuator Step Input Vollage Response Adjustment Input Capacitor Adj. Chl Ch. 2 Ch} Chi2 mV 20mVv None None None None 10mV 50mV cl2 62 None None 20m 100mVv cis C65 None None 50mV 200m ce C58 6 C56 100mV 500m cul él None None 200m vv ci4 C64 None None Vv 2 cas c54* a C53 wv BV None None None None av lov None None None None 5V 20v None None None None lov 50V None None None None 20v 100 None None None None “The slugs of C3 and C53 should be removed completely and an insulated adjustment tool used to set C4 and C54. C3 and C53 can now be replaced and set as described on page 49. 540 - 48 - 546Two methods of input capacitance alignment are available as detailed below:- (i) Measure input capacitance with instrument operating at 20mV attenuator setting, then adjust Cé (C56) at 50mV/div and C3 (C53) at 0.5V/div to equalise the input capacitance to the 20mV setting. (ii) Connect @ x10 probe (bwd P32) to the input socket. Set attenuator to 20mV, couple probe to a calibrator with 1V, 1kHz output, adjust probe compensation for optimum square wave. Now tum attenuator to 50mV step, increase input to 2V and adjust Cé (C56) for clean wave free of under or overshoot. Repeat at .5V with 20V input, adjust C3 and C53 for clean square wave. (h) VERTICAL AMPLIFIER ALIGNMENT. Select Ch, 1 set atten, at 50mV, Vernier to CAL, Set calibration with a 200mV 1% IkHz square wave. Remove cal. signal and apply a IMHz square wave with

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