DIGITAL SYSTEM DESIGN

By: NANSON ECE UG

UNIT 1:

INTRODUCTION To VHDL

VHDL: ​ Very high speed integrated hardware description language

This language was developed to make high speed integrated circuits.

This language allows you to describe and simulate complex digital systems.

Simulation : It allows us to verify the functionality of the circuits virtually using the
tools of the software we can verify the function .

Design units:
GENERICs

Generics are a general mechanism used to pass information to an instance of an

entity. The information passed to the entity can be of most types allowed in
VHDL.

The most obvious, and probably most used, information passed to an entity is
delay times for rising and falling delays of the device being modeled. Generics
can also be used to pass any user-defined data types, including information such
as load capacitance, resistance, and so on. For synthesis parameters such as
datapath widths, signal widths, and so on, can be passed in as generics.

All of the data passed to an entity is instance-specific information. The data

values pertain to the instance being passed the data.

The data passed to an instance is static data. After the model has been
elaborated (linked into the simulator), the data does not change during
simulation. Generics cannot be assigned information as part of a simulation run.
The information contained in generics passed into a component instance or a
block can be used to alter the simulation results, but results cannot modify the
generics
The following is an example of an entity for an AND gate that has three generics
associated with it:

ENTITY and2 IS
GENERIC(rise, fall : TIME; load : INTEGER);
PORT( a, b : IN BIT; PORT( c : OUT BIT);
END AND2​;
Architectures:

The entity describes the interface to the VHDL model. The architecture describes
the underlying functionality of the entity and contains the statements that model
the behavior of the entity. An architecture is always related to an entity and
describes the behavior of that entity.

1.Describes behavior of entity

2.Must be associated with a specific entity
3.Single entity can have many architectures but only one can be active at a time
4.An architecture is similar to a schematic of the component.
Data Objects:

A data object is created by an ​object declaration​ and has a ​value​ and ​type​ associated
with it. An object can be a Constant, Variable, Signal or a File.
1.Signal
Signals can be considered wires in a schematic that can have a current value and future
values.
Signals are used for communication between components.
Signals are declared ​outside​ the process .
Some delay must be incurred in a signal assignment

​ type [ := initial value] ;

signal​ ​list_of_signal_names:

Signals are updated when their signal assignment statement is executed, ​after a certain
delay​, as illustrated below,

​ UM <= (A ​xor​ B) ​after​ 2 ns;

S
if no delay is specified, the signal will be updated after a ​delta​ delay. One can also
specify multiple waveforms using multiple events as illustrated below,

signal​ wavefrm : std_logic;

wavefrm <= ‘0’, ‘1’ after 5ns, ‘0’ after 10ns, ‘1’ after 20 ns;
2.Variables:
Variables and Constants are used to model the behavior of a circuit and are used in
processes, procedures and functions.
A variable can have a single value, as with a constant, but a variable can be updated
using a variable assignment statement.
Variables are used for local storage of data.
Variables are more convenient than signals for the storage of
(temporary) data.

variable​ ​list_of_variable_names​: type [ := initial value] ;

A variable can be updated using a ​variable assignment statement​ such as

Variable_name := expression;
3.Constants:
A constant can have a single value of a given type and cannot be changed during the
simulation.
Constants declared at the start of an architecture can be used
anywhere in the architecture.
Constants declared at the start of an architecture can be used
anywhere in the architecture.
A constant is declared as follows,

​ ​of​_​name_of_constant:​ type [ := initial value] ​;

constant​ ​list_

Data Types :
ACCESS TYPES​ Most hardware design engineers using VHDL probably never
use access types directly but access types provide very powerful programming
language type operations. An access type in VHDL is very similar to a pointer in
a language like Pascal or C.
Access types allow the designer to model objects of a dynamic nature.For
instance, dynamic queues, fifos, and so on can be modeled easily using access
types.
File Types
A file type allows declarations of objects that have a type FILE. A file object can
be read from,written to,and checked for the end of file only with special
procedures and functions.
A ​file type declaration​ specifies the name of the file type and the base type of
the file.Following is an example of a file type declaration:
TYPE integer_file IS FILE OF INTEGER;

Composite Types
It consists of array and record types.

1.Record Types:
Record types group objects of many types together as a single object.
Each element of the record can be accessed by its field name.
Record elements can include elements of any type,including arrays and
records.The elements of a record can be of the same type or different types.

TYPE instruction IS
RECORD
opcode : optype;
src : INTEGER;
dst : INTEGER;
END RECORD;

2.Array Types:
Array types group one or more elements of the same type together as a single
object.Each element of the array can be accessed by one or more array indices.

TYPE data_bus IS ARRAY(0 TO 31) OF BIT;

VARIABLE X: data_bus;
VARIABLE Y: BIT;
Y := X(0); --line 1
Y := X(15); --line 2

Delays:

1.Inertial Delay:
Inertial delay is the default in VHDL. If no delay type is specified, inertial delay is
used. Inertial delay is the default because, in most cases, it behaves similarly to
the actual device.
In an inertial delay model, the output signal of the device has inertia, which must
be overcome for the signal to change value.
The inertia value is equal to the delay through the device.

The buffer has a single input A and a single output B. The waveforms are shown
for input A and the output B. Signal A changes from a ‘0’ to a ‘1’ at 10
nanoseconds and from a ‘1’ to a ‘0’ at 20 nanoseconds. This creates a pulse or
spike that is 10 nanoseconds in duration. The buffer has a 20- nanosecond delay
through the device.

2.Transport delay:
Transport delay is not the default in VHDL and must be specified. It represents a
wire delay in which any pulse, no matter how small, is propagated to the output
signal delayed by the delay value specified.
Transport delay must be explicitly specified . i.e keyword “TRANSPORT” must be
used .

3.Delta delay:
Signals Drivers

Every signal assignment in a process creates a driver for that signal. The driver
of a signal holds its current value and all its future values as a sequence of one
or more transactions, where each transaction identifies the value to appear on
the signal along with the time at which the value is to appear.
Concurrent statements:
Component Declaration

A component instantiated in a structural description must first be declared using

a component declaration. A component declaration declares the name and the
interface of a component. The interface specifies the mode and the type of ports.
The syntax of a simple form of component declaration is :
Component Instantiation

A component instantiation statement defines a subcomponent of the entity in

which it appears. It associates the signals in the entity with the ports of that
subcomponent. A format of a component instantiation statement is

component-label: component-name port map ( association-list) ',

The component-label can be any legal identifier and can be considered as the
name of the instance. The component-name must be the name of a component
declared earlier using a component declaration. The association-list associates
signals in the entity, called actuals, with the ports of a component, called locals.

A configuration

is, therefore, used to bind

1. an architecture body to its entity declaration,
2. a component with an entity.

Configuration specifications:

A configuration specification is used to bind component instantiations to specific

entities that are stored in design libraries. The specification appears in the
declarations part of the architecture or block in which the components are
instantiated. Binding of a component to an entity can be done on a per instance
basis, or for all instantiations of a component, or for a selected set of
instantiations of a component. Instantiations of different components can also be
bound to the same entity.

Configuration declaration
Configuration specifications have to appear in an architecture body. Therefore, to
change a binding, it is necessary to change the architecture body and re-analyze
it. This may sometimes be cumbersome and time consuming. To avoid this, a
configuration declaration may be used to specify a binding.

A configuration declaration is a separate design unit, therefore, it allows for late

binding of components, that is, the binding can be performed after the
architecture body has been written. It is also possible to have more than one
configuration declaration for an entity, each of which defines a different set of
bindings for components in a single architecture body

The typical format of a configuration declaration is

configuration ​configuration-name of entity-name is

block-configuration
end​ [ configuration-name ];

Generate statement

A ​generate statement​ is an iterative or conditional elaboration of a portion of a

description. This provides a compact way to represent what would ordinarily be a
group of statements.

The generate statement simplifies description of regular design structures.

Usually it is used to specify a group of identical components using just one
component specification and repeating it using the ​generate​ mechanism.

A generate statement consists of three main parts:

● generation scheme (either ​for scheme​ or ​if scheme)​ ;

● declarative part (local declarations of subprograms, types, signals,
constants, components, attributes, configurations, files and groups);
● concurrent statements.
SEQUENTIAL STATEMENTS
Sequential statements are used to define algorithms to express the behavior of a
design entity. These statements appear in process statements and in
subprograms (procedures and functions).

Wait statement
suspends process/subprogram execution until a signal changes, a condition
becomes true, or a defined time period has elapsed. Combinations of these can
also be used.

Syntax:
wait​ [​on​ signal_name {,signal_name}]
[​until​ condition]
[​for​ time expression]
Ex:
wait until clock = '1' or enable /='1' for 25ns;

Signal assignment statement

Assign a waveform to one signal driver

Example
A <= B after 10ns;
C <= A after 10ns; -- value of C is current A value

Variable assignment statement

Update a process/procedure/function variable with an expression. The update
takes effect immediately.

Example
A := B and C;
D := A; -- value of D is new A value

Conditional Statements
Standard ​if..then​ and ​case​ constructs can be used for selective operations.

if​ condition ​then

... sequence of statements...
elseif​ condition ​then
... sequence of statements...
else
... sequence of statements...
end if;

NOTE: ​elsif​ and ​else​ clauses are optional.

case​ expression ​is

when​ choices ​=>​ sequence of statements
when​ choices ​=>​ sequence of statements
...
when others​ ​=>​ sequence of statements
end case;

NOTE: ​case​ choices can be expressions or ranges.

Loop statements
Sequences of statements can be repeated some number of times under the
control of ​while​ or ​for​ constructs.
label: ​while​ condition ​loop
... sequence of statements ...
end loop​ label;
label: ​for​ loop_variable ​in​ range ​loop
... sequence of statements...
​end loop​ label;

Loop termination statements​ -

allow termination of one iteration, loop, or procedure.
next​ ​[when​ condition​];​ -- end current loop iteration
exit [when​ condition​];​ -- exit innermost loop entirely
return​ expression; -- exit from subprogram
Functions: & Procedures
Functions are used to describe frequently used sequential algorithms that return a single
value that is returned to the calling program using a return statement.

http://vlsi-design-engineers.blogspot.com/2015/07/vhdl-functions-and-proc
edures.html
Packages
A package provides a convenient mechanism to store and share declarations
that are common across many design units. A package is represented by
1​. a package declaration, and optionally,
2. ​a package body.

A package declaration contains a set of declarations that may possibly be shared

by many design units. It defines the interface to the package, i.e., it defines items
that can be made visible to other design units, for example, a function
declaration. A package body, in contrast, contains the hidden details of a
package, for example, a function body.
Std_logic_1164 Package

Package std_logic_1164 is defined in the library IEEE. This package is not part of the VHDL LRM.

Description:

The Std_logic_1164 package is the IEEE standard for describing digital logic values in VHDL (IEEE
STD 1164). It contains definitions for std_logic (single bit) and for std_logic_vector (array). It also
contains VHDL functions for these types to resolve tri-state conflicts, functions to define logical
operators and conversion functions to and from other standard types.

VHDL LIBRARIES

VHDL libraries allow you to store commonly used packages and entities that you can use in
your VHDL files. A VHDL package file contains common design elements that you can use in
the VHDL file source files that make up your design.
VHDL library is a container, which holds files that define entities, architectures, or packages.

VHDL Operators:
The predefined operators in the VHDL language are classified into the following
five categories:
1. Logical operators
2. Relational operators
3. Adding operators
4. Multiplying operators
5. Miscellaneous operators
Test Benches
To simulate your design, you need both the design under test (DUT) or unit under test
(UUT) and the stimulus provided by the test bench.
A test bench is HDL code that allows you to provide a documented, repeatable set of stimuli
that is portable across different simulators.
A test bench can be as simple as a file with clock and input data or a more complicated file
that includes error checking, file input and output, and conditional testing.