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    24-Booth Multiplier, Behavioral Modeling-17!02!2023

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    This document discusses behavioral modeling in Verilog at the highest level of abstraction. It describes the initial and always blocks that are used for behavioral modeling. Initial blocks execute once at time 0 while always blocks execute continuously throughout simulation. Procedural assignments within these blocks allow modeling of sequential and concurrent behavior. Examples are given for modeling basic logic gates and a magnitude comparator at the behavioral level.

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    24-Booth Multiplier, Behavioral Modeling-17!02!2023

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    This document discusses behavioral modeling in Verilog at the highest level of abstraction. It describes the initial and always blocks that are used for behavioral modeling. Initial blocks execute once at time 0 while always blocks execute continuously throughout simulation. Procedural assignments within these blocks allow modeling of sequential and concurrent behavior. Examples are given for modeling basic logic gates and a magnitude comparator at the behavioral level.

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    This document discusses behavioral modeling in Verilog at the highest level of abstraction. It describes the initial and always blocks that are used for behavioral modeling. Initial blocks execute once at time 0 while always blocks execute continuously throughout simulation. Procedural assignments within these blocks allow modeling of sequential and concurrent behavior. Examples are given for modeling basic logic gates and a magnitude comparator at the behavioral level.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    30 views13 pages

    24-Booth Multiplier, Behavioral Modeling-17!02!2023

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    This document discusses behavioral modeling in Verilog at the highest level of abstraction. It describes the initial and always blocks that are used for behavioral modeling. Initial blocks execute once at time 0 while always blocks execute continuously throughout simulation. Procedural assignments within these blocks allow modeling of sequential and concurrent behavior. Examples are given for modeling basic logic gates and a magnitude comparator at the behavioral level.

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    Behavioral or algorithmic level

    • This is the highest level of abstraction provided by


    Verilog HDL.

    • A module can be implemented in terms of the desired


    design algorithm without concern for the hardware
    implementation details.

    • Designing at this level is very similar to C programming.


    Behavioral modeling

    • There are two structured procedures in Verilog:


    – initial
    – always
    • Concurrent execution is observed in between these procedures.
    • Sequential / concurrent execution can be realized within these
    procedures.
    • Only registers can be assigned in these procedures.
    • The assignments in these procedures are called “procedural
    assignments”.
    initial statement

    • Starts execution at ‘0’ simulation time and executes only once

    during the entire simulation.

    • Multiple statements in initial block can be grouped with (begin

    & end) keywords.

    • These blocks are not synthesizable and cannot be nested.

    • Each initial block represent a separate and independent activity.

    • initial blocks are used in generating test benches.


    initial block structures

    initial initial
    xor_out = in1 ^ in2; begin
    and_out = a_in & b_in;
    end

    initial
    begin
    enable = 1’b0;
    rst = 1’b0;
    #100 rst = 1’b1;
    #20 enable = 1’b1;
    end
    always statement

    • Starts execution at ‘0’ simulation time and is active all through


    out the entire simulation.

    • Multiple statements inside always block can be grouped with


    (begin & end) keywords.

    • Execution of always blocks is controlled by using the timing


    control.

    • always blocks cannot be nested.


    always statement

    • An always block without any sensitivity control will


    create an infinite loop and execute forever.

    • Each always block represent a separate and


    independent activity.

    • These blocks can synthesize to different hardware


    depending on their usage.

    • always block with timing control are synthesizable.


    always block structures

    always @(a_in or b_in)


    always
    begin
    xor_out = in1 ^ in2;
    and_out = a_in & b_in;
    end

    always @(posedge reset)


    begin
    if (reset == 1’b1)
    q_out = 1’b0;
    else
    q_out = d_in;
    end
    always block - Examples

    always statement with timing control - Example


    module cntr (cnt_out, clk_in);
    input clk_in;
    output cnt_out;
    reg cnt_out;
    wire clk_in;
    always @(posedge clk_in)
    cnt_out = cnt_out + 1’b1;
    endmodule
    always block - Examples
    always statement without timing control -Example

    module clk_gen (clk_out);

    output clk_out;
    reg clk_out;

    always
    #5 clk_out = ~clk_out;
    initial
    clk_out = 1’b1;
    endmodule
    Examples
    2 x 1 multiplexer
    module mux_2x1 (y, a, b, s);
    output y;
    input a, b, s;
    reg y;
    always @(a or b or s)
    if (s==1) y = a;
    else y = b;
    endmodule.
    Magnitude comparator
    else if (a>b)
    module comparator (a,b,eq,lt,gt);
    begin
    input [3:0] a, b; eq = 1’b0;
    output reg eq,lt, gt; lt = 1’b0;
    always @(a,b) gt = 1’b1;
    begin end
    else
    if (a ==b)
    begin
    begin eq = 1’b0;
    eq = 1’b1; lt = 1’b1;
    lt = 1’b0; gt = 1’b0;
    gt = 1’b0; end
    end
    end
    endmodule
    Test bench for comparator
    module comparator_tb ();
    reg [3:0] a, b;
    wire eq, lt,gt;
    comparator C1 (a,b,eq,lt,gt);
    initial
    begin
    a = 4’b1100;
    b = 4’b 1100;
    #10;
    a = 4’b0100;
    b = 4’b 1100;
    #10;
    a = 4’b1000;
    b = 4’b0010;
    end
    endmodule

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