 Behavioral Modeling

Concepts
Constructs
Structured Procedures
 Two basic structured procedure statements
always
initial
 All behavioral statements can appear only inside these
blocks
 Each always or initial block has a separate activity flow
(concurrency)
 Start from simulation time 0
 Cannot be nested
Structured Procedures:
initial statement
 Starts at time 0
 Executes only once during a simulation
 Multiple initial blocks, execute in parallel
 All start at time 0
 Each finishes independently
 Syntax:
initial
begin
// behavioral statements
end
Structured Procedures:
initial statement (cont’d)
 Example:
module stimulus;
reg x, y, a, b, m; initial
#50 $finish;
initial endmodule
m= 1’b0;

initial
begin
#5 a=1’b1;
#25 b=1’b0;
end

initial
begin
#10 x=1’b0;
#25 y=1’b1;
end
Structured Procedures:
always statement
 Start at time 0
 Execute the statements in a looping fashion
 Example
module clock_gen;
reg clock;

// Initialize clock at time zero

initial
clock = 1’b0;

// Toggle clock every half-cycle (time period =20)

always
#10 clock = ~clock;

initial What happens if such a

#1000 $finish; $finish is not included?
endmodule
Procedural Assignments

 Assignments inside initial and always

 Are used to update values of reg,
integer, real, or time variables
The value remains unchanged until another
procedural assignment updates it
In contrast to continuous assignment (Dataflow
Modeling, previous chapter)
Procedural Assignments (cont’d)
 Syntax
 <lvalue> = <expression>

 <lvalue> can be
 reg, integer, real, time
 A bit-select of the above (e.g., addr[0])
 A part-select of the above (e.g., addr[31:16])
 A concatenation of any of the above
 <expression> is the same as introduced in dataflow modeling
 What happens if the widths do not match?
 LHS wider than RHS => RHS is zero-extended
 RHS wider than LHS => RHS is truncated (Least significant part is kept)
Types of Procedural Assignments

Blocking Assignments

Non – Blocking Assignments

Blocking Assignment

The = token represents a blocking procedural

assignment
➤ Evaluated and assigned in a single step
➤ statement are executed in the order
➤ Execution flow within the procedure is blocked
until the assignment is completed
➤ Evaluations of concurrent statements in the
same time step are blocked until the assignment
is completed
initial
begin
X = 0; Y = 1; Z = 1; Execute at time 0
count = 0;
reg_a = 16’b0; reg_b = reg_a;

#15 reg_a[2] = 1’b1; At time 15

#10 reg_b[15:13] = {X,Y,Z} At time 25

count = count + 1; At time 25, there is a delay

end in preceding statements
 NON-BLOCKING ASSIGNMENT

The <= token represents a non-blocking

assignment
➤ Evaluated and assigned in two steps:
The right-hand side is evaluated
immediately
The assignment to the left-hand side is
postponed until other evaluations in the
current time step are completed
➤ Execution flow within the procedure continues
until a timing control is encountered (flow is not
blocked)
module evaluates2(out);
output out;
reg a, b, c;
initial
begin
a = 0; b = 1; c = 0;
end
always c = #5 ~c;
always @(posedge c)
begin
a <= b;
b <= a;
end
endmodule
 Blocking assignment

module evaluates2(out,a,b,c);
output out;
reg a, b, c;
initial
begin
a = 0; b = 1; c = 0;
end
always c = #5 ~c;
always @(posedge c)
begin
a = b;
b = a;
end
endmodule
 A sequence of nonblocking assignments
don’t communicate
a = 1; a <= 1;
b = a; b <= a;
c = b; c <= b;

Blocking assignment: Nonblocking assignment:

a=b=c=1 a=1
b = old value of a
c = old value of b
Race condition will occur in blocking assignment . Either of them will
execute first.
module non_block1(out,);
//input
output out;
reg a, b, c, d, e, f;
//blocking assignments
Initial
begin
a = #10 1;
b = #2 0;
c = #4 1;
end
//non-blocking assignments
initial
begin
d <= #10 1;
e <= #2 0;
f <= #4 1; OUTPUT ?
end
#100 $finish;
endmodule
module non_block1(out);
//input
output out;
reg a, b;
Initial
begin
a = 0;
b = 1;
a <= b;
b <= a;
end
initial
begin

$monitor ($time, ,”a = %b b = %b”, a,b); OUTPUT ?

#100 $finish;
end
endmodule
Behavioral Modeling Statements:
Conditional Statements
 Just the same as if-else in C
 Syntax:
if (<expression>) true_statement;

if (<expression>) true_statement;
else false_statement;

if (<expression>) true_statement1;
else if (<expression>) true_statement2;
else if (<expression>) true_statement3;
else default_statement;

 True is 1 or non-zero
 False is 0 or ambiguous (x or z)
 More than one statement: begin end
Conditional Statements (cont’d)
 Examples:
 if (!lock) buffer = data;

 if (enable) out = in;

 if (number_queued < MAX_Q_DEPTH)

begin
data_queue = data;
number_queued = number_queued +1;
end
else $display(“Queue full! Try again.”);

 if (alu_control==0)
y = x+z;
else if (alu_control==1)
y = x-z;
else if (alu_control==2)
y = x*z;
else
$display(“Invalid ALU control signal.”);
Behavioral Modeling Statements:
Multiway Branching
 Similar to switch-case statement in C
 Syntax:
case (<expression>)
alternative1: statement1;
alternative2: statement2;
...
default: default_statement; // optional
endcase
 Notes:
 <expression> is compared to the alternatives in the
order specified.
 Default statement is optional
Multiway Branching (cont’d)
 Examples:
reg [1:0] alu_control;
...
case (alu_control)
2’d0: y = x + z;
2’d1: y = x – z;
2’d2: y = x * z;
default: $display(“Invalid ALU control signal.”);
Multiway Branching (cont’d)
 Example 2:
module mux4_to_1(out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3, s1, s0;
reg out;

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1,s0})
2’d0: out = i0;
2’d1: out = i1;
2’d2: out = i2;
2’d3: out = i3;
endcase
endmodule
Multiway Branching (cont’d)
 The case statements compares <expression> and alternatives bit-for-bit
 x and z values should match
module demultiplexer1_to_4(out0, out1, out2, out3, in,
s1, s0);
output out0, out1, out2, out3;
input in, s1, s0;
always @(s1 or s0 or in)
case( {s1, s0} )
2’b00: begin ... end
2’b01: begin ... end
2’b10: begin ... end
2’b11: begin ... end
2’bx0, 2’bx1, 2’bxz, 2’bxx, 2’b0x, 2’b1x, 2’bzx:
begin ... end
2’bz0, 2’bz1, 2’bzz, 2’b0z, 2’b1z:
begin ... end
default: $display(“Unspecified control signals”);
endcase
endmodule
Multiway Branching (cont’d)
 casex and casez keywords
 casez treats all z values as “don’t care”
 casex treats all x and z values as “don’t care”
 Example:
reg [3:0]
integer state;
casex(encoding)
4’b1xxx: next_state=3;
4’bx1xx: next_state=2;
4’bxx1x: next_state=1;
4’bxxx1: next_state=0;
default: next_state=0;
endcase
Behavioral Modeling Statements:
Loops
 Loops in Verilog
while, for, repeat, forever
 The while loop syntax:
while (<expression>)
statement;
 Example:
Look at p. 136 of your book
Loops (cont’d)

 The for loop

Similar to C
Syntax:
for( init_expr; cond_expr; change_expr)
statement;
Loops (cont’d)

 The repeat loop

Syntax:
repeat( number_of_iterations )
statement;
The number is evaluated only when the loop is
first encoutered
Example:
 Look at p. 138 of your book
Loops (cont’d)

 The forever loop

Syntax:
forever
statement;
Equivalent to while(1)
Example:
 Look at pp. 139-140 of your book
Procedural Assignments (cont’d)
 The two types of procedural assignments
 Blocking assignments
 Non-blocking assignments
 Blocking assignments
 are executed in order (sequentially)
 Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count; All executed at time 0
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
#15 reg_a[2] = 1’b1; executed at time 15
#10 reg_b[15:13] = {x, y, z};
count = count + 1;
end All executed at time 25
Procedural Assignments (cont’d)
 Non-blocking assignments
 The next statements are not blocked for this one
 Syntax:
 <lvalue> <= <expression>
 Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count; All executed at time 0
initial begin
x=0; y=1; z=1;
count=0;
reg_a= 16’b0; reg_b = reg_a;
reg_a[2] <= #15 1’b1; Scheduled to run at time 15
reg_b[15:13] <= #10 {x, y, z};
Scheduled to run at time 10
count <= count + 1;
end
Procedural Assignments (cont’d)
 Application of non-blocking assignments
 Used to model concurrent data transfers
 Example: Write behavioral statements to swap values of
two variables
 Another example
always @(posedge clock)
begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1;
end
The old value of reg1 is used
Procedural Assignments (cont’d)
 Race condition
 When the final result of simulating two (or more) concurrent
processes depends on their order of execution
 Example:
always @(posedge clock)
b = a;
always @(posedge clock)
a = b;
 Solution: always @(posedge clock)
always @(posedge clock) begin
temp_b = b;
b <= a; temp_a = a;
always @(posedge clock) b = temp_a;
a = temp_b;
a <= b; end
Procedural Assignments (cont’d)

 Recommendation
Concurrent data transfers => race condition
Use non-blocking assignments wherever
concurrent data transfers
Example: pipeline modeling
Disadvantage:
 Lower simulation performance
 Higher memory usage in the simulator
TIMING CONTROLS
3 – TYPES
DELAY BASED TIMING CONTROL

1.REGULAR DELAY
…
parameter latency = 20;
parameter delta = 10;
reg x, y, z, p, q;

initial
begin
x = 0;
#10 y = 1;

#latency z = 0;
#(latency + delta) p = 1;

#y x = x + 1;
end
2. Intra Assignment Delay

reg x, y, z; Takes value at time 0, evaluate

initial and assign to y after 5 time unit
begin
x = 0; z = 0;
y = #5 x + z;
end

OR
initial
begin
x = 0; z = 0;
temp_a = x + z;
#5 y = temp_a;
end
3. Zero Delay

initial
begin
x = 0;
y = 0;
end
Executed last
initial
begin
#0 x = 1;
#0 y = 1;
end
Event Based Control Timings
1. Regular event delay
 @ - symbol
Changes when ever clock changes
@ (clock) q = d;

During change in + ve edge

@ (posedge clk) q = d;

Eva immediately and assigned q

at +ve edge
q = @ (posedge clk) d;
2. Named Event Control
Symbol - >
event does not hold any data
keyword - event

1. event packets;
always @ (posedge)
beign
if (last_data_recevied)
-> packets; // this will trigger the event

2. event count;
always @ (count)
 3. Event OR control

Keyword OR is used for multiple triggers

always @ (clk or reset or J or K)

if (reset)
q = J;
else if(clk)
q = K;
end

Level Sensitive timing control

keyword wait

always
wait (count_enable)
#20 count = count + 1;
module JK_flip_flop ( j ,k ,clk ,reset ,q ,qb );
output q ; reg q ;
output qb ; reg qb ;
input j ; wire j ;
input k ; wire k ;
input clk ; wire clk ;
input reset ; wire reset ;
always @ (posedge (clk)) begin
if (reset) begin
q <= 0; qb <= 1;
end
else begin
if (j!=k) begin q <= j;
qb <= k; end
else if (j==1 && k==1) begin
q <= ~q; qb <= ~qb;
endend
end
endmodule