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    Inputs Physical Design

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    Agnathavasi
    The key inputs to the physical design stage are: (1) a gate-level netlist containing cell, net, and pin/port information; (2) a LEF file with physical cell information; (3) a library file with timing, power, and area details; and (4) a technology file with layer and design rules. Additional inputs include TLU+ files with parasitic resistances and capacitances, SDC files with timing constraints, MMMC files for analysis views, and UPF files for power implementation. Sanity checks are performed on the inputs to ensure correctness before proceeding to later design stages.

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    Inputs Physical Design

    Uploaded by

    Agnathavasi
    2K views2 pages
    The key inputs to the physical design stage are: (1) a gate-level netlist containing cell, net, and pin/port information; (2) a LEF file with physical cell information; (3) a library file with timing, power, and area details; and (4) a technology file with layer and design rules. Additional inputs include TLU+ files with parasitic resistances and capacitances, SDC files with timing constraints, MMMC files for analysis views, and UPF files for power implementation. Sanity checks are performed on the inputs to ensure correctness before proceeding to later design stages.

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    Inputs physical design

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    Inputs physical design

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    The key inputs to the physical design stage are: (1) a gate-level netlist containing cell, net, and pin/port information; (2) a LEF file with physical cell information; (3) a library file with timing, power, and area details; and (4) a technology file with layer and design rules. Additional inputs include TLU+ files with parasitic resistances and capacitances, SDC files with timing constraints, MMMC files for analysis views, and UPF files for power implementation. Sanity checks are performed on the inputs to ensure correctness before proceeding to later design stages.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    2K views2 pages

    Inputs Physical Design

    Uploaded by

    Agnathavasi
    The key inputs to the physical design stage are: (1) a gate-level netlist containing cell, net, and pin/port information; (2) a LEF file with physical cell information; (3) a library file with timing, power, and area details; and (4) a technology file with layer and design rules. Additional inputs include TLU+ files with parasitic resistances and capacitances, SDC files with timing constraints, MMMC files for analysis views, and UPF files for power implementation. Sanity checks are performed on the inputs to ensure correctness before proceeding to later design stages.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    VLSI MENTORS SPURTHI B A

    INPUTS TO PHYSICAL DESIGN


    1. GATE LEVEL NETLIST(.v)
    -> The Synthesized and optimized Netlist is provided as input and it contains
    cell information, net information and pin or port information.
    -> It mainly contains the list of nets and their logical connections to standard
    cells and Macros.
    2. PHYSICAL LIBRARY [LEF]
    -> Liberty Exchange Format [LEF] file contains physical information such as
    shape, size, direction, and symmetry, input and output pins direction for each cell
    in the design.
    -> Library exchange format (LEF) is an ASCII representation of the abstract of
    the standard cells.
    3. LOGICAL LIBRARY [ .lib or .db]
    -> It contains timing, power and area related information of all the cells in the
    design.
    -> Timing information such as cell delay, setup and hold time, PVT parameters,
    maximum transition, capacitance and fan out are defined.
    -> Power information such as Leakage power, internal power etc.
    4. TECHNOLOGY FILE
    -> It contains technology-specific information such as physical and
    electrical characteristics for each metal layer, and design rules i.e. shapes,
    color, and stipple, area, and DRC rules between the metal layers.
    5. TLU+ FILE
    -> It contains R, C parasitic information per unit length for each metal.
    -> These R, C parasitics are used for calculation of net delay.
    6. SDC FILE
    VLSI MENTORS SPURTHI B A

    -> Synopsys Design Constraints [SDC] contains all the timing constraints such
    as Clock definitions, input and output delay, clock latency, clock uncertainty,
    timing exceptions etc. are defined
    OTHER INPUT FILES ARE:
    -> MMMC [Multi – Mode Multi – Corner file] =It is used to generate
    different analysis views based on different delay corners and constraints
    mode.
    -> UPF [Unified Power Format] = is an industry-wide power format
    specification to implement low power techniques in a power-aware design
    flow.
    SANITY CHECKS
    -> Sanity checks are an important step for physical design engineers to
    make sure that the inputs received for physical design are correct and
    consistent. Checks such as library checks, netlist checks and SDC checks are
    performed.
    -> Any issues in the input files may cause problems in the later stages.

    Hence, the Import stage in design involves loading all the above inputs and
    performing Sanity checks.

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