74HC174; 74HCT174

Hex D-type flip-flop with reset; positive-edge trigger

Rev. 6 — 1 September 2021 Product data sheet

1. General description
The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data
inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset
all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the
LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR
causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Input levels:
• For 74HC174: CMOS level
• For 74HCT174: TTL level
• Six edge-triggered D-type flip-flops
• Asynchronous master reset
• Complies with JEDEC standards
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V.
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C.

3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC174D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT174D
74HC174PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
74HCT174PW body width 4.4 mm
Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

4. Functional diagram

9 C1
9
CP 1
3 2 R
D0 Q0
4 5
D1 Q1 3 2
6 7 1D
D2 Q2 4 5
11 10
D3 Q3 6 7
13 12
D4 Q4 11 10
14 15
D5 Q5 13 12
MR
14 15
1
aaa-007149 aaa-007150

Fig. 1. Logic symbol Fig. 2. IEC logic symbol

D0 D1 D2 D3 D4 D5

D Q D Q D Q D Q D Q D Q
FF1 FF2 FF3 FF4 FF5 FF6

CP MR CP MR CP MR CP MR CP MR CP MR

CP

MR

Q0 Q1 Q2 Q3 Q4 Q5
aaa-007151

Fig. 3. Logic diagram

5. Pinning information

5.1. Pinning
74HC174
74HCT174

MR 1 16 VCC
74HC174
Q0 2 15 Q5 74HCT174
D0 3 14 D5
MR 1 16 VCC
D1 4 13 D4 Q0 2 15 Q5
D0 3 14 D5
Q1 5 12 Q4
D1 4 13 D4
D2 6 11 D3 Q1 5 12 Q4
D2 6 11 D3
Q2 7 10 Q3
Q2 7 10 Q3
GND 8 9 CP GND 8 9 CP

aaa-007152 aaa-007154

Fig. 4. Pin configuration SOT109-1 (SO16) Fig. 5. Pin configuration and SOT403-1 (TSSOP16)

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Product data sheet Rev. 6 — 1 September 2021 2 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

5.2. Pin description

Table 2. Pin description
Symbol Pin Description
MR 1 asynchronous master reset input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5 2, 5, 7, 10, 12, 15 flip-flop output
D0, D1, D2, D3, D4, D5 3, 4, 6, 11, 13, 14 data input
GND 8 ground (0 V)
CP 9 clock input (LOW-to-HIGH edge-triggered)
VCC 16 positive supply voltage

6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care; ↑ = LOW-to-HIGH clock transition.
Operating modes Inputs Outputs
MR CP Dn Qn
reset (clear) L X X L
load "1" H ↑ h H
load "0" H ↑ l L

7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA
IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current - 50 mA
IGND ground current -50 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 500 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.

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Product data sheet Rev. 6 — 1 September 2021 3 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

8. Recommended operating conditions

Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC174 74HCT174 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VI input voltage 0 - VCC 0 - VCC V
VO output voltage 0 - VCC 0 - VCC V
Tamb ambient temperature -40 - +125 -40 - +125 °C
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V

9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74HC174
VIH HIGH-level VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
input voltage VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
input voltage VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level VI = VIH or VIL
output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA
current
ICC supply current VI = VCC or GND; IO = 0 A; - - 8.0 - 80 - 160 μA
VCC = 6.0 V
CI input - 3.5 - - - - - pF
capacitance

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Product data sheet Rev. 6 — 1 September 2021 4 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max Min Max Min Max
74HCT174
VIH HIGH-level VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
input voltage
VIL LOW-level VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
input voltage
VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V
IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 5.5 V - 0.15 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1 - ±1 μA
current
ICC supply current VI = VCC or GND; IO = 0 A; - - 8.0 - 80 - 160 μA
VCC = 5.5 V
ΔICC additional per input pin;
supply current VI = VCC - 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
Dn input - 25 90 - 112.5 - 122.5 μA
CP input - 130 468 - 585 - 637 μA
MR input - 125 450 - 562.5 - 612.5 μA
CI input - 3.5 - - - - - pF
capacitance

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Product data sheet Rev. 6 — 1 September 2021 5 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

10. Dynamic characteristics

Table 7. Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 8
Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74HC174
tpd propagation CP to Qn; see Fig. 6 [1]
delay VCC = 2.0 V - 55 165 - 205 - 250 ns
VCC = 4.5 V - 20 33 - 41 - 50 ns
VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns
VCC = 6.0 V - 16 28 - 35 - 43 ns
tPHL HIGH to LOW MR to Qn; see Fig. 7
propagation VCC = 2.0 V - 44 150 - 190 - 225 ns
delay
VCC = 4.5 V - 16 30 - 38 - 45 ns
VCC = 5.0 V; CL = 15 pF - 13 - - - - - ns
VCC = 6.0 V - 13 26 - 33 - 38 ns
tt transition time Qn output; see Fig. 6 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tW pulse width CP input HIGH or LOW;
see Fig. 6
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
MR input LOW; see Fig. 7
VCC = 2.0 V 80 12 - 100 - 120 - ns
VCC = 4.5 V 16 4 - 20 - 24 - ns
VCC = 6.0 V 14 3 - 17 - 20 - ns
trec recovery time MR to CP; see Fig. 7
VCC = 2.0 V 5 -11 - 5 - 5 - ns
VCC = 4.5 V 5 -4 - 5 - 5 - ns
VCC = 6.0 V 5 -3 - 5 - 5 - ns
tsu set-up time Dn to CP; see Fig. 6
VCC = 2.0 V 60 6 - 75 - 90 - ns
VCC = 4.5 V 12 2 - 15 - 18 - ns
VCC = 6.0 V 10 2 - 13 - 15 - ns
th hold time Dn to CP; see Fig. 6
VCC = 2.0 V 3 -6 - 3 - 3 - ns
VCC = 4.5 V 3 -2 - 3 - 3 - ns
VCC = 6.0 V 3 -2 - 3 - 3 - ns

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Product data sheet Rev. 6 — 1 September 2021 6 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max Min Max Min Max
fmax maximum CP input; see Fig. 6
frequency VCC = 2.0 V 6 30 - 5 - 4 - MHz
VCC = 4.5 V 30 90 - 24 - 20 - MHz
VCC = 6.0 V 35 107 - 28 - 24 - MHz
VCC = 5.0 V; CL = 15 pF - 99 - - - - - MHz
CPD power per package; [3] - 17 - - - - - pF
dissipation VI = GND to VCC
capacitance
74HCT174
tpd propagation CP to Qn; see Fig. 6 [1]
delay VCC = 4.5 V - 21 35 - 44 - 53 ns
VCC = 5.0 V; CL = 15 pF - 18 - - - - - ns
tPHL HIGH to LOW MR to Qn; see Fig. 7
propagation VCC = 4.5 V - 20 35 - 44 - 53 ns
delay
VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns
tt transition time Qn output; see Fig. 6 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tW pulse width CP input; see Fig. 6
VCC = 4.5 V 16 7 - 20 - 24 - ns
MR input LOW; see Fig. 7
VCC = 4.5 V 20 7 - 25 - 30 - ns
trec recovery time MR to CP; see Fig. 7
VCC = 4.5 V 12 -3 - 15 - 18 - ns
tsu set-up time Dn to CP; see Fig. 6
VCC = 4.5 V 16 4 - 20 - 24 - ns
th hold time Dn to CP; see Fig. 6
VCC = 4.5 V 5 -3 - 5 - 5 - ns
fmax maximum CP input; see Fig. 6
frequency VCC = 4.5 V 30 63 - 24 - 20 - MHz
VCC = 5.0 V; CL = 15 pF - 69 - - - - - MHz
CPD power per package; [3] - 17 - - - - - pF
dissipation VI = GND to VCC - 1.5 V
capacitance

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
2 2
PD = CPD × VCC × fi + Σ (CL × VCC × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
2
Σ (CL × VCC × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.

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Product data sheet Rev. 6 — 1 September 2021 7 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

10.1. Waveforms and test circuit

VI

Dn input VM

GND
th th
tsu tsu
1/fmax
VI

CP input VM

GND
tW
tPHL tPLH
VOH
90 % 90 %
Qn output VM VM
10 % 10 %
VOL
tTHL tTLH

aaa-007155

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 6. Input to output propagation delay, output transition time, clock input pulse width, set-up and hold times
for data input and maximum frequency

VI

CP input VM

GND
t rec
tW
VI

MR input VM VM

GND

tPHL
VOH

Qn output VM

VOL
aaa-007156

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 7. Master reset to output propagation delays, master reset pulse width and master reset to clock recovery
time

Table 8. Measurement points

Type Input Output
VI VM VM
74HC174 VCC 0.5VCC 0.5VCC
74HCT174 3V 1.3 V 1.3 V

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Product data sheet Rev. 6 — 1 September 2021 8 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr

tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW

VCC VCC

VI VO RL S1
G DUT open

RT CL

001aad983

Test data is given in Table 9.

Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig. 8. Test circuit for measuring switching times

Table 9. Test data

Type Input Load S1 position
VI tr, tf CL RL tPHL, tPLH
74HC174 VCC 6 ns 15 pF, 50 pF 1 kΩ open
74HCT174 3V 6 ns 15 pF, 50 pF 1 kΩ open

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Product data sheet Rev. 6 — 1 September 2021 9 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

11. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

D E A
X

y HE v M A

16 9

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 8 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8
o
o
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT109-1 076E07 MS-012
03-02-19

Fig. 9. Package outline SOT109-1 (SO16)

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Product data sheet Rev. 6 — 1 September 2021 10 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

D E A
X

y HE v M A

16 9

Q
A2 (A 3 )
A
A1
pin 1 index

θ
Lp
L
1 8
detail X
w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.

mm
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8o
1.1 0.25 0.65 1 0.2 0.13 0.1
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.06 0o

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT403-1 MO-153
03-02-18

Fig. 10. Package outline SOT403-1 (TSSOP16)

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Product data sheet Rev. 6 — 1 September 2021 11 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

12. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic

13. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT174 v.6 20210901 Product data sheet - 74HC_HCT174 v.5
Modifications: • Type number 74HCT174DB (SOT338-1/SSOP16) removed.
74HC_HCT174 v.5 20210226 Product data sheet - 74HC_HCT174 v.4
Modifications: • The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Type number 74HC174DB (SOT338-1/SSOP16) removed.
• Section 2 updated.
• Section 7: Derating values for Ptot total power dissipation updated.
74HC_HCT174 v.4 20160512 Product data sheet - 74HC_HCT174 v.3
Modifications: • Type numbers 74HC174N and 74HCT174N (SOT38-4) removed.
74HC_HCT174 v.3 20130416 Product data sheet - 74HC_HCT174_CNV_2
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT174_CNV_2 19980708 Product specification - -

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Product data sheet Rev. 6 — 1 September 2021 12 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
injury, death or severe property or environmental damage. Nexperia and its

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Draft — The document is a draft version only. The content is still under the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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products in automotive equipment or applications.
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In the event that customer uses the product for design-in and use in
special or consequential damages (including - without limitation - lost
automotive applications to automotive specifications and standards,
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customer (a) shall use the product without Nexperia’s warranty of the
or replacement of any products or rework charges) whether or not such
product for such automotive applications, use and specifications, and (b)
damages are based on tort (including negligence), warranty, breach of
whenever customer uses the product for automotive applications beyond
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Nexperia’s specifications such use shall be solely at customer’s own risk,
Notwithstanding any damages that customer might incur for any reason and (c) customer fully indemnifies Nexperia for any liability, damages or failed
whatsoever, Nexperia’s aggregate and cumulative liability towards customer product claims resulting from customer design and use of the product for
for the products described herein shall be limited in accordance with the automotive applications beyond Nexperia’s standard warranty and Nexperia’s
Terms and conditions of commercial sale of Nexperia. product specifications.
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to information published in this document, including without limitation reference only. The English version shall prevail in case of any discrepancy
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Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical Notice: All referenced brands, product names, service names and
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of an Nexperia product can reasonably be expected to result in personal

74HC_HCT174 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 6 — 1 September 2021 13 / 14

Nexperia 74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description............................................................. 3
6. Functional description................................................. 3
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................4
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 6
10.1. Waveforms and test circuit........................................ 8
11. Package outline........................................................ 10
12. Abbreviations............................................................ 12
13. Revision history........................................................12
14. Legal information......................................................13

© Nexperia B.V. 2021. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 1 September 2021

74HC_HCT174 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved

Product data sheet Rev. 6 — 1 September 2021 14 / 14