CD 40174

HEF40174B
Hex D-type flip-flop

Rev. 7 — 21 November 2011 Product data sheet
1. General description
The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs (D0 to D5), a
clock input (CP), an overriding asynchronous master reset input (MR), and six buffered
outputs (Q0 to Q5). Information on D0 to D5 is transferred to Q0 to Q5 on the
LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to
Q5 = LOW) independent of CP and D0 to D5.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits

 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 Specified from 40 C to +85 C
 Complies with JEDEC standard JESD 13-B
3. Applications
 Shift registers
 Buffer/storage register
 Pattern generator
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number Package
Name Description Version
HEF40174BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF40174BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors HEF40174B
5. Functional diagram
3 4 6 11 13 14
D0 D1 D2 D3 D4 D5
D Q D Q D Q D Q D Q D Q
FF1 FF2 FF3 FF4 FF5 FF6
CP CP CP CP CP CP
CD CD CD CD CD CD
CP
9
MR
1
Q0 Q1 Q2 Q3 Q4 Q5
2 5 7 10 12 15
001aae565
Fig 1. Functional diagram
D0 D1 D2 D3 D4 D5
D D D D D D
FF1 FF2 FF3 FF4 FF5 FF6
CP Q CP Q CP Q CP Q CP Q CP Q
CD CD CD CD CD CD
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5
001aae567
Fig 2. Logic diagram
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 21 November 2011 2 of 14

6. Pinning information
6.1 Pinning
HEF40174B
MR 1 16 VDD
Q0 2 15 Q5
D0 3 14 D5
D1 4 13 D4
Q1 5 12 Q4
D2 6 11 D3
Q2 7 10 Q3
VSS 8 9 CP
001aae566
Fig 3. Pin configuration
6.2 Pin description

Table 2. Pin description
Symbol Pin Description
MR 1 master reset input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5 2, 5, 7, 10, 12, 15 buffered output
D0, D1, D2, D3, D4, D5 3, 4, 6, 11, 13, 14 data input
VSS 8 ground supply voltage
CP 9 clock input (LOW-to-HIGH; edge-triggered)
VDD 16 supply voltage
7. Functional description
Table 3. Function table[1]
Input Output
CP D MR Q
 H H H
 L H L
 X H no change
X X L L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition.

8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current VI < 0.5 V or VI > VDD + 0.5 V - 10 mA
VI input voltage 0.5 VDD + 0.5 V
IOK output clamping current VO < 0.5 V or VO > VDD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +85 C
Ptot total power dissipation DIP16 package [1] - 750 mW
SO16 package [2] - 500 mW
P power dissipation per output - 100 mW
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions

Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VI input voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
10. Static characteristics

Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Unit
Min Max Min Max Min Max
VIH HIGH-level input voltage IO < 1 A 5V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A 5V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V

Table 6. Static characteristics …continued

VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Unit
Min Max Min Max Min Max
VOH HIGH-level output voltage IO < 1 A 5V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A 5V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
II input leakage current 15 V - 0.3 - 0.3 - 1.0 A
IDD supply current IO = 0 A 5V - 20 - 20 - 150 A
10 V - 40 - 40 - 300 A
15 V - 80 - 80 - 600 A
CI input capacitance - - - - 7.5 - - pF
11. Dynamic characteristics

Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 C; or test circuit see Figure 5; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
tPHL HIGH to LOW CP to Qn; 5V 48 ns + (0.55 ns/pF)CL - 75 155 ns
propagation delay see Figure 4 10 V 19 ns + (0.23 ns/pF)CL - 30 65 ns
15 V 12 ns + (0.16 ns/pF)CL - 20 45 ns
MR to Qn; 5V 58 ns + (0.55 ns/pF)CL - 85 175 ns
see Figure 4 10 V 24 ns + (0.23 ns/pF)CL - 35 70 ns
15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns
tPLH LOW to HIGH CP to Qn; 5V 48 ns + (0.55 ns/pF)CL - 75 155 ns
propagation delay see Figure 4 10 V 19 ns + (0.23 ns/pF)CL - 30 65 ns
15 V 12 ns + (0.16 ns/pF)CL - 20 45 ns
tt transition time see Figure 4 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns
15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns
tsu set-up time Dn to CP; 5V 20 10 - ns
see Figure 4 10 V 10 5 - ns
15 V 10 5 - ns

Table 7. Dynamic characteristics …continued

VSS = 0 V; Tamb = 25 C; or test circuit see Figure 5; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
th hold time Dn to CP; 5V 10 0 - ns
15 V 5 0 - ns
tW pulse width CP input LOW; 5V 70 35 - ns
minimum width; 10 V 30 15 - ns
see Figure 4
15 V 20 10 - ns
MR input LOW; 5V 70 35 - ns
minimum width; 10 V 35 15 - ns
see Figure 4
15 V 25 10 - ns
trec recovery time MR input; 5V 45 25 - ns
15 V 15 5 - ns
fmax maximum frequency see Figure 4 5V 5 11 - MHz
10 V 15 30 - MHz
15 V 20 45 - MHz
[1] tt is the same as tTHL and tTLH.
Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol Parameter VDD Typical formula for PD (W) where:
PD dynamic power 5V PD = 3500  fi + (fo  CL)  VDD 2 fi = input frequency in MHz,
dissipation 10 V PD = 16000  fi + (fo  CL)  VDD2 fo = output frequency in MHz,
15 V PD = 42000  fi + (fo  CL)  VDD2 CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo  CL) = sum of the outputs.

12. Waveforms
VI
MR input
0V
VI
CP input VM
0V
VI
Dn input
0V
tPLH tPHL tPHL
VOH
90 %
Qn output VM
10 %
VOL
tTLH tTHL 001aak039
a. CP and MR to Qn Propagation delays and Qn transition times
1/fmax
VI
CP input VM
0V
tsu th tW
VI
Dn input VM
0V
trec
VI
MR input VM
0V
tW 001aae568
b. CP and MR minimum pulse widths, MR to CP recovery time, and Dn to CP set-up and hold times
VOH and VOL are typical output voltage levels that occur with the output load.
Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded area are where input changes result in predicable output performance.
Measurement points are given in Table 9.
Fig 4. Waveforms showing switching times

tW
VI
90 % 90 %
negative
pulse VM VM
10 % 10 %
0V
tf tr
tr tf
VI
90 % 90 %
positive
pulse VM VM
10 % 10 %
0V
tW
001aaj781
a. Input waveforms
VDD
VI VO
G DUT
RT CL
001aag182
b. Test circuit
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 5. Test circuit for measuring switching times
Table 9. Measurement points and test data

Supply voltage Input Load
VI VM tr, tf CL
5 V to 15 V VDD 0.5VI  20 ns 50 pF

13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
D ME
seating plane
A2 A
L A1
c
Z e w M
b1
(e 1)
b b2
16 9 MH
pin 1 index
E
1 8
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A A1 A2
b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.73 0.53 1.25 0.36 19.50 6.48 3.60 8.25 10.0
mm 4.2 0.51 3.2 2.54 7.62 0.254 0.76
1.30 0.38 0.85 0.23 18.55 6.20 3.05 7.80 8.3
inches 0.068 0.021 0.049 0.014 0.77 0.26 0.14 0.32 0.39
0.17 0.02 0.13 0.1 0.3 0.01 0.03
0.051 0.015 0.033 0.009 0.73 0.24 0.12 0.31 0.33
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
95-01-14
SOT38-4
03-02-13
Fig 6. Package outline SOT38-4 (DIP16)


SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D E A
X
y HE v M A
16 9
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8o
o
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT109-1 076E07 MS-012
03-02-19
Fig 7. Package outline SOT109-1 (SO16)


14. Revision history

Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF40174B v.7 20111121 Product data sheet - HEF40174B v.6
Modifications: • Legal pages updated.
• Changes in “General description”, “Features and benefits” and “Applications”.
HEF40174B v.4 20090813 Product data sheet - HEF40174B_CNV v.3
HEF40174B_CNV v.3 19950101 Product specification - HEF40174B_CNV v.2
HEF40174B_CNV v.2 19950101 Product specification - -

15. Legal information
15.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
Draft — The document is a draft version only. The content is still under
NXP Semiconductors products in such equipment or applications and
internal review and subject to formal approval, which may result in
therefore such inclusion and/or use is at the customer’s own risk.
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of Applications — Applications that are described herein for any of these
information included herein and shall have no liability for the consequences of products are for illustrative purposes only. NXP Semiconductors makes no
use of such information. representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended Customers are responsible for the design and operation of their applications
for quick reference only and should not be relied upon to contain detailed and and products using NXP Semiconductors products, and NXP Semiconductors
full information. For detailed and full information see the relevant full data accepts no liability for any assistance with applications or customer product
sheet, which is available on request via the local NXP Semiconductors sales design. It is customer’s sole responsibility to determine whether the NXP
office. In case of any inconsistency or conflict with the short data sheet, the Semiconductors product is suitable and fit for the customer’s applications and
full data sheet shall prevail. products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
Product specification — The information and data provided in a Product design and operating safeguards to minimize the risks associated with their
data sheet shall define the specification of the product as agreed between applications and products.
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however, NXP Semiconductors does not accept any liability related to any default,
shall an agreement be valid in which the NXP Semiconductors product is damage, costs or problem which is based on any weakness or default in the
deemed to offer functions and qualities beyond those described in the customer’s applications or products, or the application or use by customer’s
Product data sheet. third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
15.3 Disclaimers the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limited warranty and liability — Information in this document is believed to Limiting values — Stress above one or more limiting values (as defined in
be accurate and reliable. However, NXP Semiconductors does not give any the Absolute Maximum Ratings System of IEC 60134) will cause permanent
representations or warranties, expressed or implied, as to the accuracy or damage to the device. Limiting values are stress ratings only and (proper)
completeness of such information and shall have no liability for the operation of the device at these or any other conditions above those given in
consequences of use of such information. the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
In no event shall NXP Semiconductors be liable for any indirect, incidental,
repeated exposure to limiting values will permanently and irreversibly affect
punitive, special or consequential damages (including - without limitation - lost
the quality and reliability of the device.
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such Terms and conditions of commercial sale — NXP Semiconductors
damages are based on tort (including negligence), warranty, breach of products are sold subject to the general terms and conditions of commercial
contract or any other legal theory. sale, as published at http://www.nxp.com/profile/terms, unless otherwise
Notwithstanding any damages that customer might incur for any reason agreed in a valid written individual agreement. In case an individual
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards agreement is concluded only the terms and conditions of the respective
customer for the products described herein shall be limited in accordance agreement shall apply. NXP Semiconductors hereby expressly objects to
with the Terms and conditions of commercial sale of NXP Semiconductors. applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without No offer to sell or license — Nothing in this document may be interpreted or
limitation specifications and product descriptions, at any time and without construed as an offer to sell products that is open for acceptance or the grant,
notice. This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or
to the publication hereof. other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein
authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior
safety-critical systems or equipment, nor in applications where failure or authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly NXP Semiconductors’ specifications such use shall be solely at customer’s
states that this specific NXP Semiconductors product is automotive qualified, own risk, and (c) customer fully indemnifies NXP Semiconductors for any
the product is not suitable for automotive use. It is neither qualified nor tested liability, damages or failed product claims resulting from customer design and
in accordance with automotive testing or application requirements. NXP use of the product for automotive applications beyond NXP Semiconductors’
Semiconductors accepts no liability for inclusion and/or use of standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer 15.4 Trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the
Notice: All referenced brands, product names, service names and trademarks
product for such automotive applications, use and specifications, and (b)
are the property of their respective owners.
whenever customer uses the product for automotive applications beyond
16. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 November 2011
Document identifier: HEF40174B

CD 40174

Uploaded by

Copyright:

Available Formats

CD 40174

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CD 40174

Uploaded by

Copyright:

Available Formats

HEF40174B

Hex D-type flip-flop

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

2. Features and benefits

Fig 1. Functional diagram

Fig 2. Logic diagram

Product data sheet Rev. 7 — 21 November 2011 2 of 14

Fig 3. Pin configuration

6.2 Pin description

Product data sheet Rev. 7 — 21 November 2011 3 of 14

9. Recommended operating conditions

10. Static characteristics

Product data sheet Rev. 7 — 21 November 2011 4 of 14

Table 6. Static characteristics …continued

11. Dynamic characteristics

Product data sheet Rev. 7 — 21 November 2011 5 of 14

Table 7. Dynamic characteristics …continued

[1] tt is the same as tTHL and tTLH.

Table 8. Dynamic power dissipation PD

Product data sheet Rev. 7 — 21 November 2011 6 of 14

tPLH tPHL tPHL

tTLH tTHL 001aak039

a. CP and MR to Qn Propagation delays and Qn transition times

Product data sheet Rev. 7 — 21 November 2011 7 of 14

Table 9. Measurement points and test data

Product data sheet Rev. 7 — 21 November 2011 8 of 14

13. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE REFERENCES EUROPEAN

Fig 6. Package outline SOT38-4 (DIP16)

Product data sheet Rev. 7 — 21 November 2011 9 of 14

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE REFERENCES EUROPEAN

Fig 7. Package outline SOT109-1 (SO16)

Product data sheet Rev. 7 — 21 November 2011 10 of 14

14. Revision history

Product data sheet Rev. 7 — 21 November 2011 11 of 14

15. Legal information

15.1 Data sheet status

15.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected

Product data sheet Rev. 7 — 21 November 2011 12 of 14

16. Contact information

Product data sheet Rev. 7 — 21 November 2011 13 of 14

© NXP B.V. 2011. All rights reserved.

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.