LTC1159

LTC1159-3.3/LTC1159-5
High Efficiency Synchronous
Step-Down Switching Regulators
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FEATURES DESCRIPTIO
■ Operation from 4V to 40V Input Voltage The LTC®1159 series is a family of synchronous step-down
■ Ultrahigh Efficiency: Up to 95% switching regulator controllers featuring automatic Burst
■ 20µA Supply Current in Shutdown ModeTM operation to maintain high efficiencies at low
■ High Efficiency Maintained Over Wide Current Range output currents. These devices drive external complemen-
■ Current Mode Operation for Excellent Line and Load tary power MOSFETs at switching frequencies up to 250kHz
Transient Response using a constant off-time current-mode architecture.
■ Very Low Dropout Operation: 100% Duty Cycle A separate pin and on-board switch allow the MOSFET
■ Short-Circuit Protection driver power to be derived from the regulated output

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■ Synchronous FET Switching for High Efficiency voltage providing significant efficiency improvement when
■ Adaptive Non-Overlap Gate Drives operating at high input voltages. The constant off-time
■ Available in SSOP and SO Packages current-mode architecture maintains constant ripple cur-
rent in the inductor and provides excellent line and load
U transient response. The output current level is user pro-
APPLICATIO S grammable via an external current sense resistor.
■ Step-Down and Inverting Regulators
The LTC1159 automatically switches to power saving
■ Notebook and Palmtop Computers
Burst Mode operation when load current drops below
■ Portable Instruments
approximately 15% of maximum current. Standby current
■ Battery-Operated Digital Devices
is only 300µA while still regulating the output and shut-
■ Industrial Power Distribution
down current is a low 20µA.
■ Avionics Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
■ Telecom Power Supplies Burst Mode is a trademark of Linear Technology Corporation.

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TYPICAL APPLICATIO VIN

+ CIN
VIN 1N4148 100µF LTC1159-5 Efficiency
100V
CAP P-GATE Si9435DY 100
0.15µF FIGURE 1 CIRCUIT
+ VCC 0.1µF VIN = 10V
3.3µF P-DRIVE
VCC
EXTVCC 90
D1 L* RSENSE
EFFICIENCY (%)

MBRS140T3 33µH VIN = 20V

LTC1159-5 1 0.05Ω 2 VOUT
3 4 5V/2A 80
0V = NORMAL SHDN1 SENSE +
>2V = SHUTDOWN SHDN2 0.01µF
SENSE –
ITH 70
+ COUT
3300pF CT N-GATE Si9410DY
220µF
CT S-GND P-GND
1k 300pF
60
LTC1159 • F01
*COILTRONICS CTX33-4-MP 0.02 0.2 2
LOAD CURRENT (A)
LTC1159 • TA01

Figure 1. High Efficiency Step-Down Regulator

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LTC1159
LTC1159-3.3/LTC1159-5
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ABSOLUTE AXI U RATI GS (Note 1)

Input Supply Voltage (Pin 2) ..................... – 15V to 60V Operating Temperature Range
VCC Output Current (Pin 3) .................................. 50mA LTC1159C .............................................. 0°C to 70°C
Continuous Pin Currents (Any Pin) ...................... 50mA LTC1159I ........................................... – 40°C to 85°C
Sense Voltages ......................................... – 0.3V to 13V Extended Commercial
Shutdown Voltages ................................................... 7V Temperature Range ............................... – 40°C to 85°C
EXTVCC Input Voltage ............................................. 15V Storage Temperature Range ................ – 65°C to 150°C
Junction Temperature (Note 2) ............................ 125°C Lead Temperature (Soldering, 10 sec)................. 300°C

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PACKAGE/ORDER I FOR ATIO
TOP VIEW ORDER PART TOP VIEW ORDER PART
P-GATE 1 20 CAP
NUMBER NUMBER

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P-GATE 1 16 CAP
VIN 2 19 SHDN2 VIN 2 15 SHDN2
VCC 3 18 EXTVCC LTC1159CG VCC 3 14 EXTVCC LTC1159CN
P-DRIVE 4 17 PGND LTC1159CG-3.3 P-DRIVE 4 13 N-GATE LTC1159CN-3.3
P-DRIVE 5 16 N-GATE LTC1159CG-5 VCC 5 12 PGND LTC1159CN-5
VCC 6 15 PGND CT 6 11 SGND LTC1159CS
VCC 7 14 SGND ITH 7 10 VFB (SHDN1)* LTC1159CS-3.3
CT 8 13 SHDN1 SENSE – 8 9 SENSE + LTC1159CS-5
ITH 9 12 VFB
N PACKAGE S PACKAGE LTC1159IS
SENSE – 10 11 SENSE + 16-LEAD PDIP 16-LEAD PLASTIC SO
LTC1159IS-3.3
*FIXED OUTPUT VERSIONS
G PACKAGE LTC1159IS-5
20-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 80°C/ W (N)
TJMAX = 125°C, θJA = 110°C/ W (S)
TJMAX = 125°C, θJA = 135°C/ W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VSHDN1 = 0V (Note 3), unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VFB Feedback Voltage (LTC1159 Only) ● 1.21 1.25 1.29 V
IFB Feedback Current (LTC1159 Only) ● 0.2 µA
VOUT Regulated Output Voltage VIN = 9V
LTC1159-3.3 ILOAD = 700mA ● 3.23 3.33 3.43 V
LTC1159-5 ILOAD = 700mA ● 4.90 5.05 5.20 V
∆VOUT Output Voltage Line Regulation VIN = 9V to 40V – 40 0 40 mV
Output Voltage Load Regulation
LTC1159-3.3 5mA < ILOAD < 2A ● 40 65 mV
LTC1159-5 5mA < ILOAD < 2A ● 60 100 mV
Burst Mode Output Ripple ILOAD = 0A 50 mVP-P
IIN VIN Pin Current (Note 4)
Normal Mode VIN = 12V, EXTVCC = 5V 200 µA
VIN = 40V, EXTVCC = 5V 300 µA
Shutdown VIN = 12V, VSHDN2 = 2V 15 µA
VIN = 40V, VSHDN2 = 2V 25 µA
IEXTVCC EXTVCC Pin Current (Note 4) EXTVCC = 5V, Sleep Mode 250 µA

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 LTC1159
LTC1159-3.3/LTC1159-5
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VSHDN1 = 0V (Note 3), unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Internal Regulator Voltage VIN = 12V to 40V, EXTVCC = 0V, ICC = 10mA ● 4.25 4.5 4.75 V
VIN – VCC VCC Dropout Voltage VIN = 4V, EXTVCC = Open, ICC = 10mA 300 400 mV
VEXT – VCC EXTVCC Switch Drop VIN = 12V, EXTVCC = 5V, ISWITCH = 10mA 250 350 mV
VP-GATE – VIN P-Gate to Source Voltage (Off) VIN = 12V – 0.2 0 V
VIN = 40V – 0.2 0 V
VSENSE + – Current Sense Threshold Voltage
VSENSE – LTC1159 VSENSE – = 5V, VFB = 1.32V (Forced) 25 mV
VSENSE – = 5V, VFB = 1.15V (Forced) ● 130 150 170 mV
LTC1159-3.3 VSENSE – = 3.4V (Forced) 25 mV
VSENSE – = 3.1V (Forced) ● 130 150 170 mV
LTC1159-5 VSENSE – = 5.2V (Forced) 25 mV
VSENSE – = 4.7V (Forced) ● 130 150 170 mV
VSNDN1 SHDN1 Threshold

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LTC1159CG, LTC1159-3.3, LTC1159-5 0.5 0.8 2 V
VSHDN2 SHDN2 Threshold 0.8 1.4 2 V
ISHDN2 Shutdown 2 Input Current VSHDN2 = 5V 12 20 µA
ICT CT Pin Discharge Current VOUT in Regulation 50 70 90 µA
VOUT = 0V 2 10 µA
tOFF Off-Time (Note 5) CT = 390pF, ILOAD = 700mA, VIN = 10V 4 5 6 µs
tr, tf Driver Output Transition Times CL = 3000pF (Pins P-Drive and N-Gate), VIN = 6V 100 200 ns

– 40°C ≤ TA ≤ 85°C (Note 6)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VFB Feedback Voltage (LTC1159 Only) 1.2 1.25 1.3 V
VOUT Regulated Output Voltage VIN = 9V
LTC1159-3.3 ILOAD = 700mA 3.17 3.30 3.43 V
LTC1159-5 ILOAD = 700mA 4.85 5.05 5.25 V
IIN VIN Pin Current (Note 4)
Normal VIN = 12V, EXTVCC = 5V 200 µA
VIN = 40V, EXTVCC = 5V 300 µA
Shutdown VIN = 12V, VSHDN2 = 2V 15 µA
VIN = 40V, VSHDN2 = 2V 25 µA
IEXTVCC EXTVCC Pin Current (Note 4) EXTVCC = 5V, Sleep Mode 250 µA
VCC Internal Regulator Voltage VIN = 12V to 40V, EXTVCC = 0V, ICC = 10mA 4.5 V

VSENSE + – Current Sense Threshold Voltage Low Threshold (Forced) 25 mV

VSENSE – High Threshold (Forced) 125 150 175 mV
VSHDN2 SHDN2 Threshold 0.8 1.4 2 V
tOFF Off-Time (Note 5) CT = 390pF, ILOAD = 700mA, VIN = 10V 3.5 5 6.5 µs

Note 1: Absolute Maximum Ratings are those values beyond which the life Note 3: On LTC1159 versions which have a SHDN1 pin, it must be at
of a device may be impaired. ground potential for testing.
Note 2: TJ is calculated from the ambient temperature TA and power Note 4: The LTC1159 VIN and EXTVCC current measurements exclude
dissipation PD according to the following formulas: MOSFET driver currents. When VCC power is derived from the output via
LTC1159CG, LTC1159CG-3.3, LTC1159CG-5: TJ = TA + (PD • 135°C/W) EXTVCC, the input current increases by (IGATECHG • Duty Cycle)/(Efficiency).
LTC1159CN, LTC1159CN-3.3, LTC1159CN-5: TJ = TA + (PD • 80°C/W) See Typical Performance Characteristics and Applications Information.
LTC1159CS, LTC1159CS-3.3, LTC1159CS-5: TJ = TA + (PD • 110°C/W) Note 5: In applications where RSENSE is placed at ground potential, the off-
time increases approximately 40%.

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LTC1159
LTC1159-3.3/LTC1159-5
ELECTRICAL CHARACTERISTICS
Note 6: The LTC1159C, LTC1159C-3.3, and LTC1159C-5 are not tested Note 7: The logic-level power MOSFETs shown in Figure 1 are rated for
and not quality assurance sampled at – 40°C and 85°C. These VDS(MAX) = 30V. For operation at VIN > 30V, use standard threshold
specifications are guaranteed by design and/or correlation. The LTC1159I, MOSFETs with EXTVCC powered from a 12V supply. See Applications
LTC1159I-3.3 and LTC1159I-5 are guaranteed and tested over the – 40°C Information.
to 85°C operating temperature range.

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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage Line Regulation Load Regulation
100 60 20
FIGURE 1 CIRCUIT FIGURE 1 CIRCUIT FIGURE 1 CIRCUIT
ILOAD = 1A ILOAD = 1A VIN = 24V
40 0

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95
20 –20
EFFICIENCY (%)

∆VOUT (mV)
∆VOUT (mV)

90 NOTE 6 0 NOTE 6 –40

–20 –60
85
–40 –80

80 –60 –100
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 0 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V) INPUT VOLTAGE (V) LOAD CURRENT (A)
LTC1159 • TPC01 LT1159 • TPC02 LTC1159 • TPC03

Operating Frequency
EXTVCC Pin Current VIN Pin Current vs (VIN – VOUT)
10 500 2.0
FIGURE 1 CIRCUIT FIGURE 1 CIRCUIT VOUT = 5V
T = 0°C
8 400
NORMALIZED FREQUENCY

1.5
SUPPLY CURRENT (µA)
EXTVCC CURRENT (mA)

ILOAD = 1A
6 300 T = 25°C
T = 70°C
NOTE 6 NORMAL NOTE 6 1.0
4 200

ILOAD = 100mA
0.5
2 100

ILOAD = 0 VSHDN2 = 2V
0 0 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V) (VIN – VOUT) VOLTAGE (V)
LTC1159 • TPC04 LTC1159 • TPC05 LTC1159 • TPC06

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 LTC1159
LTC1159-3.3/LTC1159-5
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TYPICAL PERFOR A CE CHARACTERISTICS
EXTVCC Switch Drop Off-Time vs VOUT Current Sense Threshold Voltage
600 80 160

500 70 140 MAXIMUM

THRESHOLD
60 120

SENSE VOLTAGE (mV)

EXTVCC – VCC (mV)

400

OFF-TIME (µs)
50 100

300 40 80

30 60
200
20 40 MINIMUM
100 THRESHOLD
10 LTC1159-5 20
LTC1159-3.3
0 0 0
0 5 10 15 20 0 1 2 3 4 5 0 20 40 60 80 100

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SWITCH CURRENT (mA) OUTPUT VOLTAGE (V) TEMPERATURE (°C)
LTC1159 • TPC07 LTC1159 • TPC08 LTC1159 • TPC09

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PI FU CTIO S
VIN: Main Supply Input Pin. SENSE+: The (+) Input for the Current Comparator. A built-
in offset between the SENSE+ and SENSE – pins, in conjunc-
SGND: Small-Signal Ground. Must be routed separately
tion with RSENSE, sets the current trip threshold.
from other grounds to the (–) terminal of COUT.
N-Gate: High Current Drive for the Bottom N-Channel
PGND: Driver Power Grounds. Connect to source of N-
MOSFET. The N-Gate pin swings from ground to VCC.
channel MOSFET and the (–) terminal of CIN.
P-Gate: Level-Shifted Gate Drive Signal for the Top
VCC: Outputs of internal 4.5V linear regulator, EXTVCC
P-Channel MOSFET. The voltage swing at the P-gate pin is
switch, and supply inputs for driver and control circuits.
from VIN to VIN – VCC.
The driver and control circuits are powered from the higher
of the 4.5V regulator or EXTVCC voltage. Must be closely P-Drive: High Current Gate Drive for the Top P-Channel
decoupled to power ground. MOSFET. The P-drive pin(s) swing(s) from VCC to ground.
CT: External capacitor CT from this pin to ground sets the CAP: Charge Compensation Pin. A capacitor to VCC pro-
operating frequency. (The frequency is also dependent on vides charge required by the P-gate level-shift capacitor
the ratio VOUT/VIN.) during supply transitions. The charge compensation ca-
ITH: Gain Amplifier Decoupling Point. The current com- pacitor must be larger than the gate drive capacitor.
parator threshold increases with the ITH pin voltage. SHDN1: This pin shuts down the control circuitry only (VCC
is not affected). Taking SHDN1 pin high turns off the
VFB: For the LTC1159 adjustable version, the VFB pin
control circuitry and holds both MOSFETs off. This pin
receives the feedback voltage from an external resistive
must be at ground potential for normal operation.
divider used to set the output voltage.
SHDN2: Master Shutdown Pin. Taking SHDN2 high shuts
SENSE–: Connects to internal resistive divider which sets
down VCC and all control circuitry.
the output voltage in fixed output versions. The SENSE– pin
is also the (–) input of the current comparator.

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LTC1159
LTC1159-3.3/LTC1159-5
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FU CTIO AL DIAGRA Internal divider broken at VFB for adjustable versions.
VIN
VCC P-GATE
CAP
LOW DROPOUT 550k
SHDN2
4.5V REGULATOR
P-DRIVE
VCC 550k
LOW DROP SWITCH
EXTVCC
N-GATE

SENSE + SENSE –
PGND
–

V
+
R
Q –
SLEEP S
C
25mV TO 150mV

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+
– VOS
VTH1
–
T 13k
+ G
+ 100k
+
S
– VTH2 1.25V VFB LTC1159 • FD

OFF-TIME
SENSE –
CONTROL SGND REFERENCE SHDN1
CT ITH

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OPERATIO (Refer to Functional Diagram)

The LTC1159 uses a current mode, constant off-time level-shifting the P-drive signal via an internal 550k resistor
architecture to synchronously switch an external pair of and external capacitor.
complementary power MOSFETs. Operating frequency is
During the switch “ON” cycle in continuous mode, current
set by an external capacitor at the CT pin.
comparator C monitors the voltage between the SENSE+
The output voltage is sensed either by an internal voltage and SENSE– pins connected across an external shunt in
divider connected to the SENSE – pin (LTC1159-3.3 and series with the inductor. When the voltage across the shunt
LTC1159-5) or an external divider returned to the VFB pin reaches its threshold value, the P-gate output is switched
(LTC1159). A voltage comparator V, and a gain block G, to VIN, turning off the P-channel MOSFET. The timing
compare the divided output voltage with a reference volt- capacitor CT is now allowed to discharge at a rate deter-
age of 1.25V. To optimize efficiency, the LTC1159 auto- mined by the off-time controller. The discharge current is
matically switches between two modes of operation, burst made proportional to the output voltage to model the
and continuous. inductor current, which decays at a rate which is also
proportional to the output voltage. While the timing
A low dropout 4.5V regulator provides the operating volt-
capacitor is discharging, the N-gate output is high, turning
age VCC for the MOSFET drivers and control circuitry during
on the N-channel MOSFET.
start-up. During normal operation, the LTC1159 family
powers the drivers and control from the output via the When the voltage on CT has discharged past VTH1, compara-
EXTVCC pin to improve efficiency. The N-GATE pin is tor T trips, setting the flip-flop. This causes the N-gate output
referenced to ground and drives the N-channel MOSFET to go low (turning off the N-channel MOSFET) and the P-
gate directly. The P-channel gate drive must be referenced gate output to also go low (turning the P-channel MOSFET
to the main supply input VIN, which is accomplished by back on). The cycle then repeats. As the load current

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 LTC1159
LTC1159-3.3/LTC1159-5
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OPERATIO (Refer to Functional Diagram)

increases, the output voltage decreases slightly. This causes is turned off, dropping the supply current from several
the output of the gain stage to increase the current com- milliamps (with the MOSFETs switching) to 300µA. When
parator threshold, thus tracking the load current. the output capacitor has discharged by the amount of
hysteresis in comparator V, the P-channel MOSFET is
The sequence of events for Burst Mode operation is very
again turned on and this process repeats. To avoid the
similar to continuous operation with the cycle interrupted
operation of the current loop interfering with Burst Mode
by the voltage comparator. When the output voltage is at or
operation, a built-in offset is incorporated in the gain stage.
above the desired regulated value, the P-channel MOSFET
is held off by comparator V and the timing capacitor con- To prevent both the external MOSFETs from being turned
tinues to discharge below VTH1. When the timing capacitor on at the same time, feedback is incorporated to sense the
discharges past VTH2, voltage comparator S trips, causing state of the driver output pins. Before the N-gate output can
the internal SLEEP line to go low and the N-channel MOSFET go high, the P-drive output must also be high. Likewise, the
to turn off. P-drive output is prevented from going low when the

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N-gate output is high.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode, much of the circuitry

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APPLICATIO S I FOR ATIO
The LTC1159 Compared to the LTC1148/LTC1149 of 0.15V/RSENSE. The current comparator threshold sets
Families the peak of the inductor ripple current, yielding a maximum
output current IMAX equal to the peak value less half the
The LTC1159 family is closest in operation to the LTC1149
and shares much of the applications information. In addi- peak-to-peak ripple current. For proper Burst Mode opera-
tion to reduced quiescent and shutdown currents, the tion, IRIPPLE(P-P) must be less than or equal to the minimum
LTC1159 adds an internal switch which allows the driver current comparator threshold.
and control sections to be powered from an external Since efficiency generally increases with ripple current,
source for higher efficiency. This change affects Power the maximum allowable ripple current is assumed, i.e.,
MOSFET Selection, EXTVCC Pin Connection, Important IRIPPLE(P-P) = 0.025V/RSENSE (see CT and L Selection for
Information About LTC1159 Adjustable Applications, and Operating Frequency). Solving for RSENSE and allowing
Efficiency Considerations found in this section. a margin for variations in the LTC1159 and external
component values yields:
The basic LTC1159 application circuit shown in Figure 1
is limited to a maximum input voltage of 30V due to
MOSFET breakdown. If the application does not require RSENSE = 100 mΩ
IMAX
greater than 18V operation, then the LTC1148 or
LTC1148HV should be used. For higher input voltages A graph for selecting RSENSE versus maximum output
where quiescent and shutdown current are not critical, the current is given in Figure 2. The LTC1159 series works well
LTC1149 may be a better choice since it is set up to drive with values of RSENSE from 0.02Ω to 0.2Ω.
standard threshold MOSFETs.
The load current below which Burst Mode operation com-
RSENSE Selection for Output Current mences, IBURST, and the peak short-circuit current, ISC(PK),
both track IMAX. Once RSENSE has been chosen, IBURST and
RSENSE is chosen based on the required output current. The
ISC(PK) can be predicted from the following equations:
LTC1159 current comparator has a threshold range that
extends from a minimum of 0.025V/RSENSE to a maximum

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LTC1159
LTC1159-3.3/LTC1159-5
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APPLICATIO S I FOR ATIO
0.20 1400
VOUT = 5V
0.18
1200
0.16

CT CAPACITANCE (pF)
1000
0.14
RSENSE (Ω)

0.12 800
0.10 VIN = 48V
600
0.08
0.06 400 VIN = 24V

0.04
200
0.02 VIN = 12V

0 0
0 1 2 3 4 5 0 50 100 150 200 250
MAXIMUM OUTPUT CURRENT (A) FREQUENCY (kHz)
LTC1159 • F03
LTC1159 • F02

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Figure 2. RSENSE vs Maximum Output Current Figure 3. Timing Capacitor Selection

where tOFF = 1.3 • 104 • CT

IBURST ≈ 15mV
RSENSE Once the frequency has been set by CT, the inductor L
must be chosen to provide no more than 0.025V/RSENSE
ISC(PK) = 150mV of peak-to-peak inductor ripple current. This results in a
RSENSE minimum required inductor value of:
The LTC1159 automatically extends tOFF during a short LMIN = 5.1 • 105 • RSENSE • CT • VREG
circuit to allow sufficient time for the inductor current to As the inductor value is increased from the minimum value,
decay between switch cycles. The resulting ripple current the ESR requirements for the output capacitor are eased at
causes the average short-circuit current ISC(AVG) to be the expense of efficiency. If too small an inductor is used,
reduced to approximately IMAX. the LTC1159 may not enter Burst Mode operation and
L and CT Selection for Operating Frequency efficiency will be severely degraded at low currents.

The LTC1159 uses a constant off-time architecture with Inductor Core Selection
tOFF determined by an external timing capacitor CT. The
Once the minimum value for L is known, the type of
value of CT is calculated from the desired continuous mode
inductor must be selected. High efficiency converters
operating frequency, f:
generally cannot afford the core loss found in low cost

CT = 7.8 • 10
f
–5 V
1 – OUT
VIN ) ) powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy or Kool Mµ® cores. Actual core loss
is independent of core size for a fixed inductor value, but
A graph for selecting CT versus frequency including the it is very dependent on the inductance selected. As induc-
effects of input voltage is given in Figure 3. tance increases, core losses go down but copper (I2R)
As the operating frequency is increased the gate charge losses will increase.
losses will be higher, reducing efficiency (see Efficiency Ferrite designs have very low core loss, so design goals can
Considerations). The complete expression for operating concentrate on copper loss and preventing saturation.
frequency is given by: Ferrite core material saturates “hard,” which means that

) )
inductance collapses abruptly when the peak design cur-
f= 1 1 – VOUT rent is exceeded. This results in an abrupt increase in
tOFF VIN Kool Mµ is a registered trademark of Magnetics, Inc.

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 LTC1159
LTC1159-3.3/LTC1159-5
U U W U
APPLICATIO S I FOR ATIO
inductor ripple current and consequent output voltage The MOSFET dissipations at maximum output current are
ripple which can cause Burst Mode operation to be falsely given by:
triggered in the LTC1159. Do not allow the core to saturate!
VOUT
P-Ch PD = (I )2 (1 + ∂P) RDS(ON) +
Molypermalloy (from Magnetics, Inc.) is a low loss core VIN MAX
material for toroids, but it is more expensive than ferrite.
A reasonable compromise from the same manufacturer is k(VIN)2 (IMAX) (CRSS) (f)
Kool Mµ. Toroids are very space efficient, especially when
V –V
you can use several layers of wire. Because they generally N-Ch PD = IN OUT (IMAX)2 (1 + ∂N) RDS(ON)
lack a bobbin, mounting is more difficult. However, new VIN
surface mount designs available from Coiltronics do not where ∂ is the temperature dependency of RDS(ON) and k
increase the height significantly. is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the P-channel

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Power MOSFET Selection
equation includes an additional term for transition losses,
Two external power MOSFETs must be selected for use
which are highest at high input voltages. For VIN < 20V the
with the LTC1159: a P-channel MOSFET for the main
high current efficiency generally improves with larger
switch and an N-channel MOSFET for the synchronous
MOSFETs, while for VIN > 20V the transition losses rapidly
switch.
increase to the point that the use of a higher RDS(ON)
The peak-to-peak drive levels are set by the VCC voltage on device with lower CRSS actually provides higher effi-
the LTC1159. This voltage is typically 4.5V during start-up ciency. The N-channel MOSFET losses are the greatest at
and 5V to 7V during normal operation (see EXTVCC Pin high input voltage or during a short circuit when the
Connection). Consequently, logic-level threshold N-channel duty cycle is nearly 100%.
MOSFETs must be used in most LTC1159 family applica-
The term (1 + ∂) is generally given for a MOSFET in the form
tions. The only exception is applications in which EXTVCC
of a normalized RDS(ON) vs Temperature curve, but
is powered from an external supply greater than 8V, in
∂ = 0.007/°C can be used as an approximation for low
which standard threshold MOSFETs (VGS(TH) < 4V) may be
voltage MOSFETs. CRSS is usually specified in the MOSFET
used. Pay close attention to the BVDSS specification for the
electrical characteristics. The constant k = 5 can be used for
MOSFETs as well; many of the logic-level MOSFETs are
the LTC1159 to estimate the relative contributions of the
limited to 30V.
two terms in the P-channel dissipation equation.
Selection criteria for the power MOSFETs include the “ON”
The Schottky diode D1 shown in Figure 1 only conducts
resistance RDS(ON), reverse transfer capacitance CRSS,
during the dead time between the conduction of the two
input voltage and maximum output current. When the
power MOSFETs. D1 prevents the body diode of the
LTC1159 is operating in continuous mode, the duty cycle
N-channel MOSFET from turning on and storing charge
for the P-channel MOSFET is given by:
during the dead time, which could cost as much as 1% in
V efficiency (although there are no other harmful effects if
P-Ch Duty Cycle = OUT
VIN D1 is omitted). Therefore, D1 should be selected for a
forward voltage of less than 0.6V when conducting IMAX.
V –V
N-Ch Duty Cycle = IN OUT
VIN

9
LTC1159
LTC1159-3.3/LTC1159-5
U U W U
APPLICATIO S I FOR ATIO
CIN and COUT Selection if 200µF/10V is called for in an application requiring 3mm
height, two AVX 100µF/10V (P/N TPSD107K010) could be
In continuous mode, the source current of the P-channel
used. Consult the manufacturer for other specific recom-
MOSFET is a square wave of duty cycle VOUT/VIN.
mendations.
To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be At low supply voltages, a minimum value of COUT is
used. The maximum RMS capacitor current is given by: suggested to prevent an abnormal low frequency operating
mode (see Figure 4). When COUT is too small, the output
I [V (V – V )]1/2 ripple at low frequencies will be large enough to trip the
CIN Required IRMS ≈ MAX OUT IN OUT
VIN voltage comparator. This causes the Burst Mode operation
to be activated when the LTC1159 would normally be in
This formula has a maximum at VIN = 2VOUT, where continuous operation. The effect is most pronounced with
IRMS = IMAX/2. This simple worst-case condition is com- low values of RSENSE and can be improved by operating at
monly used for design because even significant deviations

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higher frequencies with lower values of L. The output
do not offer much relief. Note that capacitor manufacturer’s remains in regulation at all times.
ripple current ratings are often based on only 2000 hours
1000
of life. This makes it advisable to further derate the L = 50µH
capacitor, or to choose a capacitor rated at a higher RSENSE = 0.02Ω
800
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the 600 L = 25µH
COUT (µF)

RSENSE = 0.02Ω
design. An additional 0.1µF ceramic capacitor may also be
required on VIN for high frequency decoupling. 400
The selection of COUT is driven by the required effective L = 50µH
RSENSE = 0.05Ω
series resistance (ESR). The ESR of COUT must be less than 200

twice the value of RSENSE for proper operation of the

LTC1159: 0
0 1 2 3 4 5
(VIN – VOUT) VOLTAGE (V)
COUT Required ESR < 2RSENSE LTC1159 • TPC04

Optimum efficiency is obtained by making the ESR equal to Figure 4. Minimum Suggested COUT
RSENSE. Manufacturers such as Nichicon, Chemicon, and
Sprague should be considered for high performance ca- Load Transient Response
pacitors. The OS-CON semiconductor dielectric capacitor
available from Sanyo has the lowest ESR for its size at a Switching regulators take several cycles to respond to a
somewhat higher price. Once the ESR requirement for step in DC (resistive) load current. When a load step
COUT has been met, the RMS current rating generally far occurs, VOUT shifts by an amount equal to ∆ILOAD • ESR,
exceeds the IRIPPLE(P-P) requirement. where ESR is the effective series resistance of COUT. ∆ILOAD
also begins to charge or discharge COUT until the regulator
In surface mount applications, multiple capacitors may
loop adapts to the current change and returns VOUT to its
have to be paralleled to meet the capacitance, ESR or RMS
steady-state value. During this recovery time VOUT can be
current handling requirements of the application. Alumi-
monitored for overshoot or ringing which would indicate a
num electrolytic and dry tantalum capacitors are both
stability problem. The ITH external components shown in
available in surface mount configurations. In the case of
the Figure 1 circuit will provide adequate compensation for
tantalum, it is critical that the capacitors are surge tested
most applications.
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalums, available A second, more severe transient is caused by switching in
in case heights ranging from 2mm to 4mm. For example, loads with large (>1µF) supply bypass capacitors. The

10
 LTC1159
LTC1159-3.3/LTC1159-5
U U W U
APPLICATIO S I FOR ATIO
discharged bypass capacitors are effectively put in parallel MOSFET driver and control power to be derived from the
with COUT, causing a rapid drop in VOUT. No regulator can output during normal operation and from the internal
deliver enough current to prevent this problem if the load regulator when the output is out of regulation (start-up,
switch resistance is low and it is driven quickly. The only short circuit).
solution is to limit the rise time of the switch drive so that Significant efficiency gains can be realized by powering VCC
the load rise time is limited to approximately 25 • CLOAD. from the output, since the VIN current resulting from the
Thus a 10µF capacitor would require a 250µs rise time, driver and control currents will be scaled by a factor of
limiting the charging current to about 200mA. (Duty Cycle)/(Efficiency). For 5V regulators this simply
means connecting the EXTVCC pin directly to VOUT. How-
Line Transient Response
ever, for 3.3V and other low voltage regulators, additional
The LTC1159 has better than 60dB line rejection and is circuitry is required to derive VCC power from the output.
generally impervious to large positive or negative line
The following list summarizes the four possible connec-

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voltage transients. However, one rarely occurring condi-
tions for EXTVCC:
tion can cause the output voltage to overshoot if the proper
precautions are not observed. This condition is a negative 1. EXTVCC Left Open. This will cause VCC to be powered
VIN transition of several volts followed within 100µs by a only from the internal 4.5V regulator resulting in reduced
positive transition of greater than 0.5V/µs slew rate. MOSFET gate drive levels and an efficiency penalty of up to
10% at high input voltages.
The reason this condition rarely occurs is because it takes
tens of amps to slew the regulator input capacitor at this 2. EXTVCC Connected Directly to VOUT. This is the normal
rate! The solution is to add a diode between the cap and VIN connection for a 5V regulator and provides the highest
pins of the LTC1159 as shown in several of the typical efficiency.
application circuits. If you think your system could have 3. EXTVCC Connected to an Output-Derived Boost Net-
this problem, add the diode. Note that in surface mount work. For 3.3V and other low voltage regulators, efficiency
applications it can be combined with the P-gate diode by gains can still be realized by connecting EXTVCC to an
using a low cost common cathode dual diode. output-derived voltage which has been boosted to greater
than 4.5V. This can be done either with the inductive boost
EXTVCC Pin Connection winding shown in Figure 5a or the capacitive charge pump
The LTC1159 contains an internal PNP switch connected shown in Figure 5b. The charge pump has the advantage of
between the EXTVCC and VCC pins. The switch closes and simple magnetics and generally provides the highest effi-
supplies the VCC power whenever the EXTVCC pin is higher ciency at the expense of a slightly higher parts count.
in voltage than the 4.5V internal regulator. This allows the
VIN VIN

+ +
BAT85 VIN CIN
CIN
VIN P-GATE P-CH
L
+ L RSENSE
P-GATE P-CH 1µF VOUT
1:1 • P-DRIVE
P-DRIVE RSENSE
1 2 LTC1159-3.3
VOUT BAT85
• VN2222LL
LTC1159-3.3 3 4
N-GATE N-CH +
COUT
N-GATE N-CH
+ P-GND
P-GND COUT 0.22µF BAT85
BAT85
EXTVCC
EXTVCC + LTC1159 • F05b

LTC1159 • F05a 1µF

Figure 5a. Inductive Boost Circuit for EXTVCC Figure 5b. Capacitive Charge Pump for EXTVCC

11
LTC1159
LTC1159-3.3/LTC1159-5
U U W U
APPLICATIO S I FOR ATIO
4. EXTVCC Connected to an External Supply. If an external In LTC1159N and LTC1159S applications with VOUT >
supply is available in the 5V to 12V range, it may be used 5.5V, the VCC pin may self-power through the SENSE pins
to power EXTVCC providing it is compatible with the when SHDN2 is taken high, preventing shutdown. In these
MOSFET gate drive requirements. There are no restrictions applications, a pull-down must be added to the SENSE– pin
on the EXTVCC voltage relative to VIN. EXTVCC may be as shown in Figure 6. This pull-down effectively takes the
higher than VIN providing EXTVCC does not exceed the 15V place of the SHDN1 pin, ensuring complete shutdown.
absolute maximum rating. Note: For versions in which both the SHDN1 and SHDN2
When driving standard threshold MOSFETs, the exter- pins are available (LTC1159G and all fixed output ver-
nal supply must always be present during operation to sions), the two pins are simply connected to each other and
prevent MOSFET failure due to insufficient gate drive. The driven together to guarantee complete shutdown.
LTC1149 family should also be considered for applications The Figure 6 circuit cannot be used to regulate a VOUT which
which require the use of standard threshold MOSFETs. is greater than the maximum voltage allowed on the

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LTC1159 SENSE pins (13V). In applications with VOUT >
Important Information About LTC1159 Adjustable 13V, RSENSE must be moved to the ground side of the
Applications output capacitor and load. This operates the current sense
When an output voltage other than 3.3V or 5V is required, comparator at 0V common mode, increasing the off-time
the LTC1159 adjustable version is used with an external approximately 40% and requiring the use of a smaller
resistive divider from VOUT to the VFB pin (Figure 6). The timing capacitor CT.
regulated voltage is determined by:
Inverting Regular Applications
)
VOUT = 1 + R2 1.25V
R1 ) The LTC1159 can also be used to obtain negative output
voltages from positive inputs. In these inverting applica-
The VFB pin is extremely sensitive to pickup from the tions, the current sense resistor connects to ground while
inductor switching node. Care should be taken to isolate the LTC1159 and N-channel MOSFET connections, which
the feedback network from the inductor, and the 100pF would normally go to ground, instead ride on the negative
capacitor should be connected between the VFB and SGND output. This allows the negative output voltage to be set by
pins next to the package.
VIN

+ 100µF
VIN 1N4148
50V
CAP P-GATE Si4401DY RSENSE
0.15µF LTC1159 100µH 0.039Ω
0.1µF 5M 1 2
VOUT
+ VCC P-DRIVE 3 4
1µF
VCC N-GATE Si4840DY 1N5819

ITH PGND R2
3300pF CT EXTVCC
215k + 150µF
16V
CT VFB R1 OS-CON
1k
390pF 100pF 24.9k
SGND
100Ω
SENSE +
0.01µF 100Ω
0V = NORMAL
SHDN2 SENSE –
>3V = SHUTDOWN

( )
LTC1159 • F06

VN2222LL VOUT = 1 + R2 1.25

R1
VALUES SHOWN FOR VOUT = 12V/2.5A

Figure 6. High Efficiency Adjustable Regulator with 5.5V < VOUT < 13V

12
 LTC1159
LTC1159-3.3/LTC1159-5
U U W U
APPLICATIO S I FOR ATIO
the same process as in conventional applications, using By powering EXTVCC from an output-derived source, the
either the internal divider (LTC1159-3.3, LTC1159-5) or an additional VIN current resulting from the driver and control
external divider with the adjustable version. currents will be scaled by a factor of (Duty Cycle)/(Effi-
Figure 15 in the Typical Applications shows a synchronous ciency). For example in a 20V to 5V application, 10mA of
12V to –12V converter that can supply up to 1A with better VCC current results in approximately 3mA of VIN current.
than 85% efficiency. By grounding the EXTVCC pin in the This reduces the mid-current loss from 10% or more (if the
Figure 15 circuit, the entire 12V output voltage is placed driver was powered directly from VIN) to only a few percent.
across the driver and control circuits since the LTC1159 3. I2R losses are easily predicted from the DC resistances
ground pins are at –12V. During start-up or short-circuit of the MOSFET, inductor and current shunt. In continuous
conditions, operating power is supplied by the internal mode all of the output current flows through L and
4.5V regulator. The shutdown signal is level-shifted to the RSENSE, but is “chopped” between the P-channel and
negative output rail by Q3, and Q4 ensures that Q1 and Q2 N-channel MOSFETs. If the two MOSFETs have approxi-

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remain off during the entire shutdown sequence. mately the same RDS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of L
Efficiency Considerations and RSENSE to obtain I2R losses. For example, if each
The percent efficiency of a switching regulator is equal to RDS(ON) = 0.1Ω, RL = 0.15Ω, and RSENSE = 0.05Ω, then
the output power divided by the input power times 100%. the total resistance is 0.3Ω. This results in losses ranging
It is often useful to analyze individual losses to determine from 3% to 12% as the output current increases from
what is limiting the efficiency and which change would 0.5A to 2A. I2R losses cause the efficiency to roll-off at
produce the most improvement. Percent efficiency can be high output currents.
expressed as: 4. Transition losses apply only to the P-channel MOSFET,
and only when operating at high input voltages (typically
%Efficiency = 100 – (L1 + L2 + L3 + ...)
20V or greater). Transition losses can be estimated from:
where L1, L2, etc., are the individual losses as a percentage
Transition Loss ≈ 5(VIN)2(IMAX)(CRSS)(f)
of input power.
Other losses including CIN and COUT ESR dissipative losses,
Although all dissipative elements in the circuit produce
Schottky conduction losses during dead time, and inductor
losses, four main sources usually account for most of the
core losses, generally account for less than 2% total
losses in LTC1159 circuits: 1) LTC1159 VIN current, 2)
additional loss.
LTC1159 VCC current, 3) I2R losses and 4) P-channel
transition losses. Auxiliary Windings—Suppressing Burst Mode
1. LTC1159 VIN current is the DC supply current given in Operation
the electrical characteristics which excludes MOSFET driver The LTC1159 synchronous switch removes the normal
and control currents. VIN current results in a small (< 1%) limitation that power must be drawn from the inductor
loss which increases with VIN. primary winding in order to extract power from auxiliary
2. LTC1159 VCC current is the sum of the MOSFET driver windings. With synchronous switching, auxiliary out-
and control circuit currents. The MOSFET driver current puts may be loaded without regard to the primary output
results from switching the gate capacitance of the power load, providing that the loop remains in continuous
MOSFETs. Each time a MOSFET gate is switched from low mode operation.
to high to low again, a packet of charge dQ moves from VCC Burst Mode operation can be suppressed at low output
to ground. The resulting dQ/dt is a current out of VCC which currents with a simple external network that cancels the
is typically much larger than the control circuit current. In 0.025V minimum current comparator threshold. This tech-
continuous mode, IGATECHG ≈ f (QP + QN), where QP and QN nique is also useful for eliminating audible noise from
are the gate charges of the two MOSFETs.

13
LTC1159
LTC1159-3.3/LTC1159-5
U U W U
APPLICATIO S I FOR ATIO
certain types of inductors in high current (IOUT > 5A) If VOFFSET > 0.025V, the minimum threshold will be
applications when they are lightly loaded. cancelled and Burst Mode operation is prevented from
occurring. Since VOFFSET is constant, the maximum load
An external offset is put in series with the SENSE – pin to
current is also decreased by the same offset. Thus, to get
subtract from the built-in 0.025V offset. An example of this
back to the same IMAX, the value of the sense resistor must
technique is shown in Figure 7. Two 100Ω resistors are
be reduced:
inserted in series with the leads from the sense resistor.
With the addition of R3, a current is generated through R1
RSENSE ≈ 75 mΩ
causing an offset of: IMAX

VOFFSET = VOUT ) R1
R1 + R3 ) To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
the SENSE – and SENSE + pins.

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RSENSE
L 1 2 Board Layout Checklist
LTC1159 3 4 +
R2 COUT When laying out the printed circuit board, the following
9 100Ω
SENSE + checklist should be used to ensure proper operation of the
1000pF R1
100Ω
LTC1159. These items are also illustrated graphically in
8
SENSE – the layout diagram of Figure 8. Check the following in your
LTC1159 • F07

R3 layout:

Figure 7. Suppressing Burst Mode Operation

BOLD LINES INDICATE HIGH CURRENT PATHS

+

CIN
1N4148
+

P-CHANNEL
VIN
0.15µF D1

1µF
N-CHANNEL
+ –
1 16
P-GATE CAP
2 15
VIN SHDN2 SHUTDOWN
3 14
0.1 µF VCC EXTVCC
L
4 13
P-DRIVE N-GATE OUTPUT DIVIDER
5V EXTVCC
5 12 REQUIRED WITH
CONNECTION
VCC PGND ADJUSTABLE
VERSION ONLY
6 11
CT SGND –
7 10 100pF
ITH VFB R1 3
(SHDN1) COUT 1 VOUT
CT 3300pF 8 9 +
SENSE – SENSE + RSENSE
2
1k R2
4
1000pF +

LTC1159 • F08

Figure 8. LTC1159 Layout Diagram (N and S Packages)

14
 LTC1159
LTC1159-3.3/LTC1159-5
U U W U
APPLICATIO S I FOR ATIO
1) Are the signal and power grounds segregated? The 7) Is the SHDN1 pin actively pulled to ground during
LTC1159 signal ground must connect separately to the normal operation? SHDN1 is a high impedance pin and
(–) plate of COUT. The other ground pin(s) should return to must not be allowed to float.
the source of the N-channel MOSFET, anode of the Schot-
tky diode and (–) plate of CIN, which should have as short Troubleshooting Hints
lead lengths as possible. Since efficiency is critical to LTC1159 applications it is very
2) Does the LTC1159 SENSE– pin connect to a point close important to verify that the circuit is functioning correctly
to RSENSE and the (+) plate of COUT? In adjustable applica- in both continuous and Burst Mode operation. The wave-
tions, the resistive divider R1, R2 must be connected form to monitor is the voltage on the CT pin .
between the (+) plate of COUT and signal ground. In continuous mode (ILOAD > IBURST) the voltage should be
3) Are the SENSE – and SENSE + leads routed together a sawtooth with a 0.9VP-P swing. This voltage should never
with minimum PC trace spacing? The differential dip below 2V as shown in Figure 9a. When the load current

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decoupling capacitor between the two SENSE pins should is low (ILOAD < IBURST), Burst Mode operation should occur
with the CT waveform periodically falling to ground as
be as close as possible to the LTC1159. Up to 100Ω may
shown in Figure 9b.
be placed in series with each sense lead to help decouple
the SENSE pins. However, when these resistors are used, If the CT pin is observed falling to ground at high output
the capacitor should be no larger than 1000pF. currents, it indicates poor decoupling or improper ground-
4) Does the (+) plate of CIN connect to the source of the ing. Refer to the Board Layout Checklist.
P-channel MOSFET as closely as possible? An additional
3.3V
0.1µF ceramic capacitor between VIN and power ground
may be required in some applications.
0V
5) Is the VCC decoupling capacitor connected closely be- (a) CONTINUOUS MODE OPERATION

tween the VCC pins of the LTC1159 and power ground? 3.3V

This capacitor carries the MOSFET driver peak currents.

6) In adjustable versions, the feedback pin is very sensitive (b) Burst Mode OPERATION
0V
LTC1159 • F09

to pickup from the switch node. Care must be taken to

isolate VFB from possible capacitive coupling of the induc-
Figure 9. CT Pin 6 Waveforms
tor switch signal.

15
LTC1159
LTC1159-3.3/LTC1159-5
U
TYPICAL APPLICATIO S
VIN
5V 8V TO 20V

1N4148 1N4148
+ 47µF
1µF
25V × 2
IRF7205 WIMA
OS-CON

L* RSENSE**
1 16 15µH
P-GATE CAP 1 0.02Ω 2 VOUT
0.15µF 2 15 3 4 2.5V/5A
VIN SHDN2 SHUTDOWN
0.1µF
3 14
VCC EXTVCC + 330µF
6.3V × 3
4 13
P-DRIVE N-GATE IRF7201 IRF7201 MBRS330 AVX
LTC1159
5 12
+ VCC PGND
3.3µF 6 11
CT SGND
1000pF 100pF 10k 10k
7 10

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ITH VFB 1% 1%
0.047µF 8 9
SENSE – SENSE +
2k 10k 100Ω
1000pF
100Ω
LTC1159 • F10

*MAGNETICS 77120-A7 CORE, 16T 18GA. WIRE

**KRL SL-1-R020J

Figure 10. High Efficiency 8V to 20V Input 2.5/5A Output Regulator

VIN
4V TO 20V

1N4148 1N4148
+ 47µF
25V 0.1µF
Si9435DY OS-CON L* RSENSE**
20µH
1 0.04Ω 2 VOUT
1 16 3 4 3.3V/2.5A
P-GATE CAP
0.15µF 2 15 VN2222LL BAT85
VIN SHDN2
0.1µF
3 14 BAT85
VCC EXTVCC + 330µF
0.22µF BAT85 6.3V × 2
4 13
P-DRIVE N-GATE Si9410DY MBRS130LT3 AVX
5
LTC1159-3.3
12
+
+ VCC PGND 1µF
1µF 6 11
CT SGND
270pF 7 10
ITH SHDN1 SHUTDOWN
3300pF 8 9
SENSE – SENSE +
1k 0.01µF
LTC1159 • F11

*COILTRONICS CTX20-4
**KRL SL-1/2-R040J

Figure 11. 5:1 Input Range (4V to 20V) High Efficiency 3.3V/2.5A Regulator

16
 LTC1159
LTC1159-3.3/LTC1159-5
U
TYPICAL APPLICATIO S
VIN
12V 15V TO 40V

0.33µF + 1200µF
50V × 2 1µF
MPSA06 0.1µF 1N4148 1N4148
LXF WIMA
SMP40P06
HEAT SINK
MPSA56
1 16
P-GATE CAP L* RSENSE**
22µH
2 15 1 0.01Ω 2 VOUT
0.15µF VIN SHDN2
1N4148 3 4 5V/10A
3 14
VCC EXTVCC
4 13
+ 220µF
P-DRIVE N-GATE MPSA56 MTP75N05HD MBR350 10V × 3
LTC1159-5 OS-CON
5 12
VCC PGND

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6 11
CT SGND
7 10
+ ITH SHDN1 SHUTDOWN
10µF 750pF 0.047µF 8 100Ω
9
SENSE – SENSE +
470Ω 1000pF 100Ω
LTC1159 • F12

*HURRICANE LAB HL-KK122T/BB 18k

**DALE LVR-3-0.01

Figure 12. High Current, High Efficiency 15V to 40V Input 5V/10A Output Regulator

VIN
15V TO 40V

+ 100µF
1µF
1N4148 1N4148 63V × 2
WIMA
Si4401DY SXC

5M L* RSENSE**
50µH
1
P-GATE CAP
16 1 0.02Ω 2 VOUT
3 4 12V/5A
0.15µF 2 15
VIN SHDN2
0.1µF
3 14
VCC EXTVCC
4 13
P-DRIVE N-GATE Si4840DY MBR350 + 150µF
LTC1159 16V × 2
5 12
+ VCC PGND OS-CON
3.3µF 6 11
CT SGND
390pF 100pF 10.5k 90.9k
7 10
ITH VFB 1% 1%
3300pF 8 9
SENSE – SENSE +
470Ω 100Ω
1000pF
100Ω
LTC1159 • F13

0V = NORMAL
VN2222LL *COILTRONICS CTX50-5-KM
>3V = SHUTDOWN
**IRC LO-3-0.02 ±5%

Figure 13. High Efficiency 15V to 40V Input 12V/5A Output Regulator

17
LTC1159
LTC1159-3.3/LTC1159-5
U
TYPICAL APPLICATIO S
VIN
5.5V TO 24V

BAS16 BAS16 + 47µF 1µF

25V × 2 WIMA
Si9435DY Si9435DY OS-CON

T* 5V
1 16 • OUTPUT
P-GATE CAP
0.33µF 2 15 0V = NORMAL
VIN SHDN2 >2V = SHUTDOWN
0.22µF •
3 14 •
VCC EXTVCC
Si9410DY
4
P-DRIVE N-GATE
13
MBRS140T3 Si9410DY + 220µF
10V × 2
LTC1159 1µF BAS16 100k AVX
5 12 +
+ VCC PGND
2.2µF 6 11
CT SGND

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1000pF 56pF 24.9k 124k
7 10 0.01µF
ITH VFB 1% 1% 1k
220µF
2200pF 8 9 102k 10V × 4
SENSE – SENSE + 1%
+ AVX
1k
100Ω 3
1 BAS16
1000pF RSENSE**
100Ω 0.02Ω
2 3.3V
4 OUTPUT
BAS16
LTC1159 • F14
+
10µF *HURRICANE LAB HL-8700
**KRL SL-1-R020J

Figure 14. 17W Dual Output High Efficiency 5V and 3.3V Regulator

U
PACKAGE DESCRIPTIO
G Package
20-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)

7.07 – 7.33*
5.20 – 5.38** (.278 – .289)
(.205 – .212) 1.73 – 1.99 20 19 18 17 16 15 14 13 12 11
(.068 – .078)

0° – 8°

7.65 – 7.90
.65 (.301 – .311)
.13 – .22 .55 – .95
(.0256)
(.005 – .009) (.022 – .037)
BSC .05 – .21
NOTE: .25 – .38 (.002 – .008)
1. CONTROLLING DIMENSION: MILLIMETERS (.010 – .015)
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES) 1 2 3 4 5 6 7 8 9 10 G20 SSOP 0501

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

18
 LTC1159
LTC1159-3.3/LTC1159-5
U
PACKAGE DESCRIPTIO
N Package
16-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX

16 15 14 13 12 11 10 9

0.255 ± 0.015*
(6.477 ± 0.381)

1 2 3 4 5 6 7 8

0.130 ± 0.005

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0.300 – 0.325 0.045 – 0.065
(7.620 – 8.255) (3.302 ± 0.127) (1.143 – 1.651)

0.020
(0.508)
MIN 0.065
0.009 – 0.015
(1.651)
(0.229 – 0.381) TYP
+0.035
0.325 –0.015

( )
0.125 0.100 0.018 ± 0.003
+0.889 (3.175) (2.54) (0.457 ± 0.076)
8.255
–0.381 MIN BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) N16 1098

S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)

0.386 – 0.394*
(9.804 – 10.008)
16 15 14 13 12 11 10 9

0.228 – 0.244 0.150 – 0.157**

(5.791 – 6.197) (3.810 – 3.988)

1 2 3 4 5 6 7 8
0.010 – 0.020
× 45° 0.053 – 0.069
(0.254 – 0.508)
(1.346 – 1.752)
0.004 – 0.010
0.008 – 0.010
0° – 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

0.014 – 0.019 0.050

0.016 – 0.050
(0.355 – 0.483) (1.270)
(0.406 – 1.270) BSC
TYP S16 1098

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

19
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1159
LTC1159-3.3/LTC1159-5
U
TYPICAL APPLICATIO
VIN = 12V

Q1
+ 330µF
1N4148 0.1µF 35V
Si9435
NICHICON

0.15µF

Q2
1 16 Si9410
P-GATE CAP
2 15 MBRS140
VIN SHDN2
L*
3 14
0.1µF VCC EXTVCC 100µH
LTC1159
4 13
P-DRIVE N-GATE
1N5818
5 3.3µF 12
VCC PGND

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6
+ 11
CT SGND OUTPUT
–12V/1A
5V OR 3.3V 7 VFB 10 200pF 10.5k
ITH 150µF
(SHDN1)
CT 6800pF 16V × 2
390pF 8 9 +
Q3 SENSE – SENSE + Q4
OS-CON
SHUTDOWN 90.5k
TP0610L 1k 2N7002
1000pF
20k

100Ω 100Ω
3
5.1V 1
510k RSENSE**
1N5993 0.05Ω
2
4

1159 F15

*DALE TJ4-100-1µ
**IRC LR2512-01-R050-J

Figure 15. High Efficiency 12V to –12V 1A Converter

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1628 2-Phase, Dual Step-Down Controller VIN ≤ 36V, Minimum CIN, Current Mode
LTC1702 550kHz Dual, 2-Phase Step-Down Controller Minimum CIN, No Sense Resistor Required, VIN ≤ 7V
LTC1735 Synchronous Step-Down Controller 3.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 6V, Synchronizable
LTC1773 550kHz Synchronous Step-Down Controller 2.65V ≤ VIN ≤ 8.5V, 0.8V ≤ VOUT ≤ VIN, Synchronizable to 750kHz, MS10
LTC1778 No RSENSETM Step-Down Controller No Sense Resistor Required, tON(MIN) ≤ 100ns, Current Mode, GN16
LTC1876 Triple Output, 2-Phase Controller Two, 2-Phase Step-Down Controllers and Step-Up DC/DC Converter in One IC
No RSENSE is a trademark of Linear Technology Corporation.

1159fa LT/TP 0801 2K REV A • PRINTED IN USA

Linear Technology Corporation
20 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ●
www.linear.com  LINEAR TECHNOLOGY CORPORATION 1994