SPPI 2202

DIGITAL ELECTRONICS
• Course Content
1.Number systems:- decimal, octal, hexadecimal
systems and their conversions, 1s and 2s
complement, floating point, BCD and excess- 3
codes.
2. Introduction to logic gates and their logic
operations:- AND, OR, XOR, NOT, NAND, NOR, and
XNOR, their truth tables and their applications.
3. Boolean algebra and functions:-Boolean
theorems, De Morgan theorems, minimization and
manipulation of logic functions, Karnaugh maps
and their applications.
• 4. Combinational logic circuit designs,
programmable logic devices.:-adders,
subtractors, decoders, encoders, multiplexers,
DE multiplexers and error control circuits
• 5. Memory elements: flip-flops, latches, shift
registers and counters, Sequential circuits
design using flipflops and logic gates. State
diagrams and state tables, classification of
sequential circuits and applications.
Introduction to Data transmission.
• REFERENCES:
• Digital Electronics Part I – Combinational and
Sequential Logic Dr. I. J. Wassell
• -D. M. Harris and S. L. Harris, ‘Digital Design and
Computer Architecture,’ Morgan Kaufmann,
2007.
 introduction
• Digitization is the process of converting analog signals
into discrete states a process called digitization . The
states are well separated such electronic noise does
not create errors which allows
 Storage over arbitrary period of time without
deterioration
 Flawless retrieval and reproduction of stored
information
 Flawless transmission of information
Analog signals include temperature, pressure, velocity,
mass
digitization involves two steps;
i. sampling
ii. quantization
sampling is the process of recording an analog signal at regular discrete intervals of
time. The sampling rate is the number of samples per second also measured in
hertz (Hz).

quantization; representing amplitude of the individual samples as integers expressed

in binary

The quantizer approximates each

sample value in v[n] to its nearest
level value (shown on the left),
producing the quantized sequence
vQ[n]. Ultimately the sequence vQ[n]
can be written as a sequence of bits
using the 3-bit representations shown on the right.
• What is information?
• Books/letters
• Emails
• Transaction data
• Images
• Audio clips
• Videos
• Software program
• State secrets
• Radar signals
• Test questions
• What is Data?
• Information that has been translated into digital format,
into bits (1s and 0s). Binary digit
• Data must be interpreted to become information.
• Bit-Binary digit either 0 or 1
• Byte-8 bits
• Nibble-4 bits, half a byte 00000001.00110011.
• 1KB= 2^10 =1024 bits
1KBps=bandwith/frequency
• 1MB=2^20=1048576 bits
• 1Mbps=bandwidth/frequency 5Mbps f=1/T
• 1GB=2^30=1073741824 bits
• 64GB 64x1073741824 bits=
• TB =2^40=
 transistor
Electronics deals with circuits using transistors as main elements.
A transistor is a device with 3 terminals that regulates or voltage flow
and acts as a switch or a gate for signals or does amplification
Bipolar junction transistor-
JFET-Junction field effect transistors
MOSFET-Metal oxide FETS
Conductors-electric current
Semiconductors-Si, Ge,
Doping –add impurities Si 4 electrons
add Al 3 electrons hole
add N, P,
P-type, N-type-more electrons as charge carries
• Emitter base junction is forward biased as
emitter resistance is small. The collector base
junction is reverse biased and its resistance is a
bit higher. A small forward bias is sufficient at
the emitter junction whereas a high reverse
bias has to be applied at collector junction.
• The VEE provides negative potential which
repels electrons in N-type material at the
emitter to cross the EB junction to reach the
base region.
• A transistor conducts current across the CE path only when a voltage is
applied to the base. When no base voltage is present, switch is off.
 Transistor as switch
Design a simple electronic circuit
Consisting of
Transistor,
Small current (base)
Large current (CE) to drive device
Relay, motor or LEDs

Groups of 4 groups

Base current to flow, the Base input terminal must be made

more positive than the Emitter by increasing it above the 0.7
volts needed for a silicon device. By varying this Base-Emitter
voltage VBE, the Base current is also altered and which in turn
controls the amount of Collector current flowing through the
transistor
 Number systems
a. Decimal number system (Base/Radix 10)
• Digits (or symbols) allowed: 0-9; All higher
numbers after ‘9’are represented in terms of
these 10 digits only.
• 0, 1,2,3,4,5,6,7,8,9
• 10,11,12,13,14,15,16,17,18,19,
• 20, 21, 22, 23,24,,,,,,,,,,,29
• 30, 31…………………………39
• Weight. 345=3x102 +4x 101 + 5x 100 =345
a. Octal number system (Radix/ base 8)
Uses eight digits, 0,1,2,3,4,5,6,7
10,11,12,13,14,15,16,17
20,21,22,23,24,25,26,27
30,31…
318- 3x 8^1+1x8^0=24+1=25
125708 =
Quiz. Convert 127.428 to decimal no system
1x82 +2x81 +7x80 .4𝑥8−1 +2𝑥8−2 =87.53125
64+16+7 2/64=0.03125
c. Hexadecimal number system (Radix 16)
Uses 10 digits and six letters
0,1,2,3,4,5,6,7,8,9, A,B,C,D,E,F
10, 11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F
20,21,22,23,24,25,26,27,28,29,2A,2B,2C,2D,2E,2F
3016 3𝑋161 + 0𝑋16^0 = 48
Calculate decimal equivalent of 19FDE16=decimal
 quiz
a. Express (FFFF)16 to decimal number system. (show your working)
(2mks)
65535
b. Consider an arbitrary number system with the independent digits as 0, 1,2 and X.

i. Determine the radix of this number system?

(1mk)
4
ii. List the first 30 numbers in this number system
(4mks)
0, 1,2,3,X
10,11,12,13,1X
20,21,22,23,2X
30,31,32,33,3X
X0,X1,X2,X3,XX
d. Binary number system ( base 2)
Allowed digits 0 ,1
Why is binary number system the most
preferred in digital electronics?
All kinds of data could be conveniently be
represented in terms of 0s and 1s
 The mathematics of logic is based on binary
notation
 Circuits required for performing arithmetic
operations e.g subtraction, multiplication,
division are represented in form of 0s and 1
 0 1
10 11
100 101 110 111
1000 1001 1010 1011 1100 1101 1110
1111 are the first 7number
1 X2^3 +1X2^2+1X2^1+1X2^0
8 +4 + 2 +1=15
Convert the following binary numbers to decimal
23 22 21 20 =8 421=9
1 0 0 1 1 001

1010=
1011=
Conversion between bases(BASE 2)
• The integer and fractional parts are worked out
separately.
• divide decimal/integer value by 2 (the base) and record
the remainder until the quotient is 0
• The carry sequence written in 4ward order constitutes
the binary equivalent
• Write remainders from LAST to FIRST
• For the fractional part, successively multiply the
fractional part of the decimal number by 2 and record
the carry until the multiplication result is 0. The carry
sequence is written in 4ward order from FIRST to LAST
• 13 .37510 to binary
13 r
2 6 1
2 3 0
2 1 1
2 0 1 1101
0.375 x2=0.75 0
0.75 x2 =1.5 1
0.5 x2 =1.0 1
0X2=0

13.37510 =1101.011

20.24 (BASE 10 ) TO BASE 2

10100.0011
0.24X2=0.48 0
0.48X2=0.96 0
0.96X2= 1.92 1
0.92X2=1.84 1
0.84X2=1.68 1
0.68………..
20/2 =10 REM 0
10/2=5 REM 0
5/2=2REM 1
2/2=1REM 0
1/2=0REM 1
 Decimal to octal
• Progressive division in case of integer part and
progressive multiplication by 8 which is the radix
• (153)10 to octal
153 r
(8) 19 1
2 3
0 2 (231)8
• Quiz,
• Find the octal equivalent of (73.75)10
• 111.6
 Decimal to hexadecimal
Progressive division in case of integer part and
progressive multiplication by 16 which is the radix
(82.25)10 to hexadecimal
(16) 82 r convert 195.75
5 2 to base 16
195/16=12 r 3
12/16=0 re 12 (C)
0 5 C3.12
=52.416
0.25X16=4
 Binary to octal and hexacimal
conversion
• 23 = 8 group binary numbers into groups of 3
• 24 = 16 “ “ 4

100 010 111 =100 010 111

4 2 7 = 4278

1 0001 0111 = 0001 0001 0111

1 1 7 =11716
100111100111000 to hexadecimal
0100 1111 0011 1000
4 F 3 8 =4F38
 Quiz
1. Convert 1345 to base 10
2. An ip address allocated to PC to access the
internet is 192.168.10.5/24. convert the address
into its;
a. binary equivalent
b. Hexadecimal equivalent
 Binary arithmetic
a.

111
1101 +
1011
11000
11
519
145

1101_
1011
 Negative integers
a. sign-magnitude convention: It uses one bit
(usually the leftmost) to indicate the sign. "0"
indicates a positive integer, and "1" indicates a
negative integer. The rest of the bits are used for
the magnitude of the number
e.g +4=0100 while -4=1100
b. 1’s complement -The one’s complement of a
negative binary number is the complement of its
positive counterpart i.e 1 changes to 0 and 0 to 1.
i.e +=0100 while -4=1011
 1’s complement is implemented using NOT gates

c. 2’s complement
Preferred because it has only one value for 0
 Complement the bits
 Add one to the result
 Subtraction using 1’s complement
• Take 1‟s complement of the negative number
and the end around carry of the sum is added
to the least significant bit (LSB)
• Addition and subtraction in 2's complement
notation is performed by doing the simple binary
addition of the two numbers. Subtraction is
accomplished by first performing the 2's
complement operation on the number being
subtracted then adding the two numbers.i.e
3-2=0011 -0010 1101
0011+ 1
1110
10001 =0001
• The operation is carried out by means of the
following steps:
• (i) At first, 2’s complement of the subtrahend is
found.
• (ii) Then it is added to the minuend.
• (iii) If the final carry over of the sum is 1, it is
dropped and the result is positive.
• `(iv) If there is no carry over, the two’s
complement of the sum will be the result and it is
negative e.g
 assignment
1. Perform the following using 1’s complement
arithmetic
a. 1𝐴𝐵𝐶16 + 1𝐷𝐸𝐹16 (2mks)
b. +4310 − (−5310 ) (2mks)
c. 3𝐸9116 − 1𝐹9316 (2mks)
2. Repeat quiz 1 using 2’s compement (6mks)
 Binary codes
• Representing decimal numbers with their
decimal equivalent
Weighted codes-Binary coded decimal
Non-weighted codes-excess 3 , gray code
• 8421 Code or BCD Code The decimal numbers
0, 1, 2, 3, 4, 5, 6, 7, 8, 9 can be expressed in
Binary numbers as shown below. All these
binary numbers again expressed in the last
column by expanding into 4 bits. As per the
weighted binary digits, the 4 Bit binary
numbers can be expressed according to their
place value from left to right as 8421 (2³ 2² 2¹
2: = 8421).
 Floating point (FP) number
representation
• Real numbers are numbers that include
fractions/values after the decimal point.
• Used to represent a real number in a wide
range(very small to very large)
• For example, 123.75 is a real number. This type of
number is also known as a floating point
number.
• All floating point numbers are stored by a
computer system using a mantissa and
an exponent.
• 1.2375 x 102 = 123.75 M X 10E
In binary the number is 1111011.11=1.1110111x26
1.11101111 x 2110

0 0 1 1 0 1 1 1
sign Sign Magnitude bits Man
expo mag tissa

Represent the following as an 8 bit floating point

numbers
a. 0.0075
b. -13.9
 Overflow and undeflow in FP
• An overflow occurs when the number if too
large to fit in the frame. An underflow occurs
when the number is too small to fit in the
given frame.
• Converting a number to floating point involves the following steps:
• Set the sign bit - if the number is positive, set the sign bit to 0. If
the number is negative, set it to 1.
• Divide your number into two sections - the whole number part and
the fraction part.
• Convert to binary - convert the two numbers into binary then join
them together with a binary point.
• Work out the exponent - This is done by working out how many
spaces the binary point needs to be moved so that it is just after
the first 1 in the result. If you move the binary point to the left then
this number is positive. If you move it to the right then the number
is negative. Add 127 to this number then convert to binary.
• Format the mantissa - This is done by dropping the first 1 in the
number and recording the next 23 bits
• Special Cases
• There are a few special cases to consider.
• Zero
• Zero is represented by making the sign bit
either 1 or 0 and all the other bits 0
• eg. 1 00000000 00000000000000000000000 or 0
00000000 00000000000000000000000
• This would equal a mantissa of 1 with an exponent of -
127 which is the smallest number we may represent in
floating point. It's not 0 but it is rather close and
systems know to interpret it as zero exactly.
• Infinity
• It is possible to represent both positive and
negative infinity. It is simply a matter of
switching the sign bit.
• To represent infinity we have an exponent of
all 1's with a mantissa of all 0's.
• eg. 0 11111111 00000000000000000000000
or 1 11111111 00000000000000000000000
 Logic gates
• Basic building blocks of any digital system. Has
one or more inputs (voltages of 5V or 0V )
and only 1 output operating of logic
a. AND gate-an electronic circuit that gives
a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND
operation i.e. A.B
Logic diagram and truth table
Both Both transistors must be saturated “ON” Switch representation
for an output at Q. both switches must be closed, or at
logic “1” for the lamp to be “ON”.

Represents a multiplication logic

7408 quad 2 input AND gate
 OR gate
• The OR gate is an electronic circuit that gives a high
output (1) if one or more of its inputs are high. A
plus (+) is used to show the OR operation.
Switch representation of OR gate

either switch can be closed, or at logic “1” for the lamp to be “ON”.
Either transistor must be saturated
“ON” for an output at Q.
7432 quad OR gate
 NOT gate
The NOT gate is an electronic circuit that produces an
inverted version of the input at its output. It is also known
as an inverter.

Transistor NOT gate

When no voltage is present on the input

The transistor turns off. When transistor turns off
No current flows through the collector-emitter path thu
Current from the supply Vcc flows through the resistor
To the output
Switch representation of NOT gate

In Boolean algebra the inverting Logic NOT Function

follows the Complementation Law producing
inversion.
• NAND gate
• This is a NOT-AND gate which is equal to an
AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of
the inputs are low. The symbol is an AND gate
with a small circle on the output. The small
circle represents inversion.
Switch representation
Transistor NAND gate

Either transistor must be cut-off “OFF” for an

output at Q.
7400 quad NAND gate
 NAND gate as a universal gate
• NAND gates can also be used to produce any
other type of logic gate function
• NOR gate This is a NOT-OR gate which is equal
to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the
inputs are high. The symbol is an OR gate with
a small circle on the output. The small circle
represents inversion.
 Transistor NOR gate

Both transistors must be cut-off “OFF” for an output at Q.

Switch representation of NOR gate
 NOR gate as a Universal Gate
• Left as H/W for the student
 • EXOR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two
inputs are high. An encircled plus sign ( is used to show the EOR operation.
)

EXNOR gate

Giving the Boolean expression of:

EXOR gate equivalent
• EXNOR gate
• The 'Exclusive-NOR' gate circuit does the
opposite to the EOR gate. It will give a low
output if either, but not both, of its two
inputs are high. The symbol is an EXOR gate
with a small circle on the output. The small
circle represents inversion.
Equivalent circuit
Logic gate symbols
 Boolean laws
• 1. a. A.0=0
b. A+0=A (identity elements)
2.a. A.1=A b. A+1=1
3a. A+𝐴=1 b. A. 𝐴 =0 (complement law)
4. 𝐴=A double inversion(NOT NOT) returns any
variable to its previous state
• Boolean algebra finds its most practical use in the
simplification of logic circuits. If we translate a
logic circuit’s function into symbolic (Boolean)
form, and apply certain algebraic rules to the
resulting equation to reduce the number of terms
and/or arithmetic operations, the simplified
equation may be translated back into circuit form
for a logic circuit performing the same function
with fewer components. If equivalent function
may be achieved with fewer components, the
result will be increased reliability and decreased
cost of manufacture.
 examples
• A+AB=A
Write the simplified expression from
the circuit diagram shown below.
Simplified logic circuit
Simplify the electromechanical relay
circuit shown
 Boolean simplification examples
• Suppose the cash room at a store has access
restricted to certain employees, each of whom
has a key, which produces a logic 1 at particular
inputs to an unlocking circuit. Only the store
manager (M) can enter alone. The assistant
manager (A) and the cashier (C) also have access,
but only when accompanied by each other, or by
the store manager. Design a combinational logic
circuit that will allow access by producing a logic
1 when the above conditions are me
• Truth table
MAC
• 000 0
• 001 0
• 010 0
• 011 1
• 100 1
• 101 1
• 110 1
• 111 1
Q=M+ACM +AC
Q=M+AC
 quiz
John’s Automated Cafeteria orders a machine to
dispense coffee, tea, and milk. Design the
machine so that it has a button (input line) for
each choice and so that a customer can have at
most one of the three choices and draw the
corresponding circuit diagram.
Simplify the logic circuit shown
 De Morgan’s Theorem
Applies to group complementation, long bar
over more than one variable.

When a long bar is broken, the operation directly underneath the break changes
from addition to multiplication, or vice versa, and the broken bar pieces remain over
the individual variables.
• When multiple “layers” of bars exist in an
expression, you may only break one bar at a
time, and it is generally easier to begin
simplification by breaking the longest
(uppermost) bar first.
Quiz: simplify the circuit below
 Quiz 2

Design a logic circuit which will open the waste valve is opened if at least two out
of the three sensors show good flame
Simplify the circuit diagram below
 Simplification using K-maps
• Karnaugh Maps offer a graphical method of
reducing a digital circuit to its minimum
number of gates. It contains 2𝑛 cells
• The Karnaugh map uses the following rules for
the simplification of expressions by grouping
together adjacent cells containing ones
• A.
B.

C
D.

E.
F

G
• H.

Summmary:
1. No zeros allowed.
2. No diagonals.
3. Only power of 2 number of cells in each
group.
4. Groups should be as large as possible.
5. Every one must be in at least one group.
6. Overlapping allowed.
7. Wrap around allowed.
8. Fewest number of groups possible.
 examples
i

ii.
iii.

iv.
• Simplify the expression f(XYZ)=sum(2,3 ,7)

Simplify the expression (wxyz)=Sum(1,5,6,7,9,13)

 Combinational logic
• The outputs of Combinational Logic Circuits
are only determined by the logical function of
their current input state, logic “0” or logic “1”,
at any given instant in time.
• Its memoryless I.e no feedback
• They are decision making circuits
• Multiplexers, De-multiplexers, Encoders,
Decoders, Full and Half Adders etc
• Has several inputs but only one output
Consists of logic gates, Boolean algebra and truth tables
 Half adder
• Adds 2 bits with a sum and a carry

A B S C(out)
0 0 0 0

0 1 1 0
1 0 1 0

1 1 0 1
Half adder circuit
 Full adder
• The main difference between the Full Adder
and the previous Half Adder is that a full
adder has three inputs. The same two single
bit data inputs A and B as before plus an
additional Carry-in (C-in) input to receive the
carry from a previous stage as shown below.
 Half subtractor
• Half subtractor is a combination circuit with
two inputs and two outputs (difference and
borrow). It produces the difference between
the two binary bits at the input and also
produces an output (Borrow) to indicate if a 1
has been borrowed. In the subtraction (A-B), A
is called as Minuend bit and B is called as
Subtrahend bit.
Truth table
 Full subtractor
• The main difference between the Full
Subtractor and the previous Half Subtractor
circuit is that a full subtractor has three
inputs. The two single bit data inputs X
(minuend) and Y (subtrahend) the same as
before plus an additional Borrow-in (B-in)
input to receive the borrow generated by the
subtraction process from a previous stage as
shown below.
Truth table
Full adder circuit
Binary subtractor using 2’s
complement
 Programmable Logic Device(PLD)
• Each of the input variables, both in its
uncomplemented and complemented form,
are inputs to AND gates through fuses. (The S-
shaped lines in the circuit diagram represent
fuses.) The fuses can be “blown” or left in
place in order to program each AND gate to
output a product. Since every input, plus its
complement, is input to each AND gate, any of
the AND gates can be programmed to output
a minterm.
• Some are pre-programmed at the time of
manufacture. Others are programmed by the
manufacturer. And there are types that can be
programmed by a user. Some can even be erased
and reprogrammed.
• Programmable Logic Array (PLA)Both the AND
gate plane and the OR gate plane are
programmable.
• Read Only Memory (ROM)Only the OR gate plane
is programmable.
• Programmable Array Logic (PAL)Only the AND
gate plane is programmable.
 Multiplexers
• A device that selects one of multiple inputs to be
passed on as the output based on one or more
selection lines. Up to 2𝑛 inputs can be selected
by n selection lines.
• There are many places in the CPU where one of
several signals must be selected to pass onward.
E.g values to be added in the CPU may come from
a CPU register, come from memory, or actually be
stored as part of the instruction itself. The device
that allows this selection is essentially a switch.
Output Q=?
 Applications of MUX
• Communication System
• A communication system has both a
communication network and a transmission
system. By using a multiplexer, the efficiency
of the communication system can be
increased by allowing the transmission of
data, such as audio and video data from
different channels through single lines or
cables.
• Multiplexers are used in computer memory to maintain
a huge amount of memory in the computers, and also
to reduce the number of copper lines required to
connect the memory to other parts of the computer.
• In telephone networks, multiple audio signals are
integrated on a single line of transmission with the
help of a multiplexer
• The multiplexer is used to transmit the data signals
from the computer system of a spacecraft or a satellite
to the ground system by using a GSM satellite.
 Demultiplexer
• The demultiplexer takes one single input data
line and then switches it to any one of a
number of individual output lines one at a
time. The demultiplexer converts a serial data
signal at the input to a parallel data at its
output lines as shown below.
Logic circuit demux
 Applications of DEMUX
• Communication System
• Mux and demux both are used in communication systems to carry out the
process of data transmission. A De-multiplexer receives the output signals
from the multiplexer and at the receiver end, it converts them back to the
original form.
• Arithmetic Logic Unit
• The output of the ALU is fed as an input to the De-multiplexer, and the
output of the demultiplexer is connected to multiple registers. The output
of the ALU can be stored in multiple registers.
• Serial to Parallel Converter
• This converter is used to reconstruct parallel data. In this technique, serial
data is given as an input to the De-multiplexer at a regular interval, and a
counter is attached to the demultiplexer at the control input to detect the
data signal at the output of the demultiplexer. When all data signals are
stored, the output of the demux can be read out in parallel.
 encoder
• It has maximum of 2n input lines and ‘n’
output lines.
• Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 &
Y0 and two outputs A1 & A0. The block
diagram of 4 to 2 Encoder is shown in the
following figure.
 Boolean function

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary
code at the output.

2𝑛 𝑖𝑛𝑝𝑢𝑡𝑠 − 𝑛𝑜𝑢𝑡𝑝𝑢𝑡𝑠
N=1
2------------1
N=2
4------------2
N=3
8------------3
N=4
16-----------4
 23 = 8 𝑖𝑛𝑝𝑢𝑡𝑠
n =3 Outputs

Octal to Binary Encoder

Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to
binary encoder is nothing but 8 to 3 encoder. The block diagram of octal to binary
Encoder is shown in the following figure.

At any time, only one of these eight inputs can

be ‘1’ in order to get the respective binary
code. The Truth table of octal to binary
encoder is shown below.
 A B Q
0 0 0
0 1 1
1 0 1
1 1 1

The corresponding Boolean functions for each output.

We can implement the above Boolean
functions by using four input OR gates.
The circuit diagram of octal to binary encoder
is shown in the following figure.
• Drawbacks of Encoder
• Following are the drawbacks of normal encoder.
• There is an ambiguity, when all outputs of encoder are
equal to zero. Because, it could be the code
corresponding to the inputs, when only least significant
input is one or when all inputs are zero.
• If more than one input is active High, then the encoder
produces an output, which may not be the correct
code. For example, if both Y3 and Y6 are ‘1’, then the
encoder produces 111 at the output. This is neither
equivalent code corresponding to Y3, when it is ‘1’ nor
the equivalent code corresponding to Y6, when it is ‘1’.
• Drawbacks of Encoder
• Following are the drawbacks of normal encoder.
• There is an ambiguity, when all outputs of encoder are
equal to zero. Because, it could be the code corresponding
to the inputs, when only least significant input is one or
when all inputs are zero.
• If more than one input is active High, then the encoder
produces an output, which may not be the correct code.
For example, if both Y3 and Y6 are ‘1’, then the encoder
produces 111 at the output. This is neither equivalent code
corresponding to Y3, when it is ‘1’ nor the equivalent code
corresponding to Y6, when it is ‘1’.
i.e 011 Ored with 110= 111
• So, to overcome these difficulties, we should assign
priorities to each input of encoder. Then, the output of
encoder will be the binary code corresponding to the
active High inputs s, which has higher priority. This
encoder is called as priority encoder.
• A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 &
Y0 and two outputs A1 & A0. Here, the input, Y3 has the
highest priority, whereas the input, Y0 has the lowest
priority. In this case, even if more than one input is ‘1’
at the same time, the output will be the binary code
corresponding to the input, which is having higher
priority.
• A 4-to-2 priority encoder takes 4 input bits
and produces 2 output bits. In this truth table,
for all the non-explicitly defined input
combinations (i.e. inputs containing 2, 3, or 4
high bits) the lower priority bits are shown as
don't cares (X). Similarly when the inputs are
0000, the outputs are not valid and therefore
they are XX.
 X- invalid or don’t
care states

A priority encoder provide n bits of binary coded output

representing the position of the highest order active input of
2n inputs. If two or more inputs are high at the same time, the
input having the highest priority will take precedence.
It's applications includes
used to control interrupt requests by acting on the highest
priority request
to encode the output of a flash analog to digital converter
00 = 𝑦1 + 𝑦3

01 = 𝑦2 + 𝑦3
The Boolean function ;
Circuit diagram for 4-2 priority
encoder
Applications of encoders ; Keyboard
Encoder Priority encoders can be used to reduce the number of wires needed in a
particular circuits or application that have multiple inputs. For example, assume that a
microcomputer needs to read the 104 keys of a standard QWERTY keyboard where only
one key would be pressed either “HIGH” or “LOW” at any one time. One way would be to
connect all 104 wires from the individual keys on the keyboard directly to the computers
input but this would be impractical for a small home PC. Another alternative and better
way would be to interface the keyboard to the PC using a priority encoder. The 104
individual buttons or keys could be encoded into a standard ASCII code of only 7- bits (0
to 127 decimal) to represent each key or character of the keyboard and then input as a
much smaller 7-bit B.C.D code directly to the computer. Keypad encoders such as the
74C923 20-key encoder are available to do just that
Applications of the Encoder and Decoder
• Speed synchronization of multiple motors in
industries.
• War field flying robot with a night vision flying
camera.
• Robotic vehicle with the metal detector.
• RF based home automation system.
• Automatic health monitoring systems
 decoders
• A Binary Decoder converts coded inputs into
coded outputs, where the input and output
codes are different and decoders are available
to “decode” either a Binary or BCD (8421
code) input pattern to typically a Decimal
output code. Commonly available BCD-
to Decimal decoders include the TTL 7442 or
the CMOS 4028, 2-to-4, 3-to-8 and 4-to-16
line configurations.
• Some binary decoders have an additional input
pin labelled “Enable” that controls the outputs
from the device. This extra input allows the
decoders outputs to be turned “ON” or “OFF” as
required. These types of binary decoders are
commonly used as “memory address decoders”
in microprocessor memory applications. A, B and
C as address signals. Each combination of A, B or
C defines a unique memory address.
• `
 Boolean functions

Each output is having one product term. So, there are four
product terms in total. We can implement these four product
terms by using four AND gates having three inputs each & two
inverters. The circuit diagram of 2 to 4 decoder is shown in the
following figure.
2 to 4 decoder with enable
Implementation of Higher-order Decoders
• Now, let us implement the following two higher-order decoders using lower-order
decoders.
• 3 to 8 decoder
• 4 to 16 decoder
• 3 to 8 Decoder
• In this section, let us implement 3 to 8 decoder using 2 to 4 decoders. We know
that 2 to 4 Decoder has two inputs, A1 & A0 and four outputs, Y3 to Y0. Whereas, 3
to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0.
• We can find the number of lower order decoders required for implementing
higher order decoder using the following formula.
𝑚
• Required number of lower order decoders= 2
𝑚1
• Where m2=no of outputs of higher order decoders
• m1 =‘’ ‘’ ‘’ lower order decoders
Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder.
The block diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following
figure.