CS8122

CS8122
2% 5V, 750mA Low Dropout Linear
Regulator with Delayed RESET
Description Features
The CS8122 is a precision 5V linear reg- The regulator is protected against a ■ 5V +/- 2% Regulated
ulator capable of sourcing in excess of variety of fault conditions: i.e. reverse Output
750mA. The RESET Õs delay time is battery, overvoltage, short circuit and
externally programmed using a discrete thermal runaway conditions. The regu- ■ Low Dropout Voltage
RC network. During power up, or when lator is protected against voltage tran- (0.6V @ 0.5A)
the output goes out of regulation, the sients ranging from -50V to +40V. Short
RESET lead remains in the low state circuit current is limited to 1.2A (typ). ■ 750mA Output Current
for the duration of the delay. This func- Capability
The CS8122 is an improved replacement
tion is independent of the input voltage for the CS8126 and features a tighter tol- ■ Externally Programmed
and will function correctly as long as erance on its output voltage (2% vs 4%).
the output voltage remains at or above RESET Delay
1V. Hysteresis is included in the Delay The CS8122 is packaged in a 5 lead
TOÐ220 with copper tab. The copper tab
■ Fault Protection
and the RESET comparators to
can be connected to a heat sink if Reverse Battery
improve noise immunity. A latching
discharge circuit is used to discharge necessary. 60V Load Dump
the delay capacitor when it is triggered -50V Reverse Transient
by a brief fault condition. Short Circuit
Thermal Shutdown

Block Diagram

VIN Package Options

Over Voltage
Shutdown
VOUT 5 Lead TO-220
Pre- Regulated Supply
Regulator for Circuit Bias
Error Amplifier
Bandgap - Anti-Saturation
Reference and
+
Current Limit

Charge Thermal VOUTSENSE

Current Shutdown
Generator 1 VIN
2 VOUT
Latching Discharge
Delay 3 Gnd
Q S
- 4 Delay
+
5 RESET
R
-
1
+
Delay Comparator
VDISC +
RESET
-
Gnd

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 2/5/99 1 A ¨ Company
CS8122 Absolute Maximum Ratings

Input Operating Range..................................................................................................................................................-0.5 to 26V

Power Dissipation.............................................................................................................................................Internally Limited
Transient Input Voltage .................................................................................................................................................-50V, 60V
Output Current .................................................................................................................................................Internally Limited
ESD Susceptibility (Human Body Model)..............................................................................................................................4kV
Junction Temperature .............................................................................................................................................-55¡C to 150¡C
Storage Temperature...............................................................................................................................................-55¡C to 150¡C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak

Electrical Characteristics: -40ûC ² TA ² +125ûC, -40ûC ² TJ ² +150ûC, 6V ² VIN ² 26V, 5mA ² IOUT ² 500mA,
R RESET = 4.7k½ to VCC unless otherwise noted*

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

■ Output Stage (VOUT)

Output Voltage 4.9 5.0 5.1 V
Dropout Voltage IOUT = 500mA 0.35 0.60 V
Supply Current IOUT ² 10mA 2 7 mA
IOUT ² 100mA 6 12
IOUT ² 500mA 55 100
Line Regulation 6V ² VIN ² 26V, IOUT = 50mA 5 50 mV
Load Regulation 50mA ² IOUT ² 500mA, VIN = 14V 10 50 mV
Ripple Rejection f = 120Hz, VIN = 7 to 17V, 54 75 dB
IOUT = 250mA
Current Limit 0.75 1.20 A
Overvoltage Shutdown 32 40 V
Maximum Line Transient VOUT ² 5.5V 60 95 V
Reverse Polarity Input VOUT ³ -0.6V, 10½ Load -15 -30 V
Voltage DC
Reverse Polarity Input 1% Duty Cycle, T < 100ms, -50 -80 V
Voltage Transient 10½ Load
Thermal Shutdown Guaranteed by Design 150 180 210 ¡C

■ RESET and Delay Functions

Delay Charge Current VDELAY = 2V 5 10 15 µA
RESET Threshold VOUT Increasing, VRT(ON) 4.65 4.90 VOUT-0.01 V
VOUT Decreasing, VRT(OFF) 4.50 4.70 VOUT-0.16 V
RESET Hysteresis VRH = VRT(ON) - VRT(OFF) 150 200 250 mV
Delay Threshold Charge, VDC(HI) 3.25 3.50 3.75 V
Discharge, VDC(L) 2.85 3.10 3.35 V
Delay Hysteresis 200 400 800 mV
RESET Output Voltage Low 1V < VOUT < VRT(L), 3k½ to VOUT 0.1 0.4 V
RESET Output Leakage VOUT > VRT(H) 0 10 µA
Current
Delay Capacitor Discharge Latched ÒONÓ, 0.2 0.5 V
Discharge Voltage VOUT > VRT
Delay Time CDELAY = 0.1µF 16 32 48 ms
* To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
CDelay x VDelay Threshold Charge
Delay Time = = CDelay x 3.5 x 105 (typ)
ICharge

2
 CS8122
Package Lead Description

PACKAGE LEAD # LEAD SYMBOL FUNCTION

5Lead TO-220
1 VIN Unregulated supply voltage to IC.
2 VOUT Regulated 5V output.
3 Gnd Ground connection.
4 Delay Timing capacitor for RESET function.
5 RESET CMOS/TTL compatible output lead. RESET goes low whenev-
er VOUT drops below 6% of it's regulated value.

Typical Performance Characteristics

Quiescent Current vs Input Voltage over Temperature Quiescent Current vs Input Voltage over Load Resistance

55.0 120.0
Rload = 25W Room Temp.
50.0
Rload = 6.67W
45.0 100.0
Quiescent Current (mA)

40.0
Quiescent Current (mA)

35.0 80.0
30.0
125ûC 60.0
25.0 Rload = 10W
20.0
40.0
15.0 25ûC
10.0 20.0
-40ûC Rload = 25W
5.0 Rload = NO LOAD
0.0 0.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VIN (V) VIN (V)

Output Voltage vs Input Voltage over Temperature VOUT vs. VIN over RLOAD

Rload = 25W
5.5
5.5 Room Temp.
5.0
5.0 Rload=25½
4.5
4.5
4.0
4.0 Rload = 6.67W
3.5
3.5
VOUT (V)

3.0
VOUT (V)

3.0
125ûC 2.5
2.5
2.0 Rload =
2.0 NO LOAD
25ûC 1.5
1.5
-40ûC 1.0
1.0 Rload = 10W
0.5
0.5
0.0
0.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VIN (V)
VIN (V)

3
CS8122 Typical Performance Characteristics: continued

Line Regulation vs. Output Current Load Regulation vs. Output Current

100 6
80 4
TEMP = -40ûC
60 2

LOAD REGULATION (mV)

LINE REGULATION (mV)

VIN 6-26V
40 0
TEMP = 25ûC
20 -2 TEMP = 25ûC
TEMP = - 40ûC
0 -4
VIN = 14V
-20 -6
TEMP = 125ûC
-40 -8
TEMP = 125ûC
-60 -10
-80 -12
-100 -14
0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 800
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)

Dropout Voltage vs. Output Current Quiescent Current vs. Output Current

900 100
800 90
VIN = 14V
QUIESCENT CURRENT (mA)
125ûC
DROPOUT VOLTAGE (mV)

700 80
70
600 25ûC
25ûC 60
500
125ûC 50
400 -40ûC
40
300 30
-40ûC
200 20
100 10
0 0
0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 800
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)

Ripple Rejection Output Capacitor ESR

IOUT= 250mA 103

90
102
80
COUT= 10mF, ESR = 1 & 0.1mF,
ESR = 0 CO= 47/68mF
70 101
REJECTION (dB)

ESR (ohms)

60 Stable Region
50 100

40
COUT= 10mF, ESR = 1W
10-1 CO= 47mF
30
-2
20
10
CO= 68mF
COUT= 10mF, ESR = 10W
10 -3
10
0
10-4
100 101 102 103 104 105 106 107 108 100 101 102 103
FREQUENCY (Hz)
Output Current (mA)

4
 CS8122
RESET Circuit Waveform
VOUT
VRH
VRT(ON)
VRT(OFF)

(1) = No Delay Capacitor

(2) = With Delay Capacitor
RESET (1) (3) = Max: RESET Voltage (1.0V)

(3)
(2)
VRL

tDelay
Delay
VDH
VDC(HI)
VDC(LO)
(2) VDIS

Circuit Description

The CS8122 RESET function, has hysteresis on both the Reset Delay Circuit
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V. The Reset Delay Circuit provides a programmable (by
external capacitor) delay on the RESET output lead. The
The RESET circuit output is an open collector type with
Delay lead provides source current to the external delay
ON and OFF parameters as specified. The RESET output
capacitor only when the Low Voltage Inhibit circuit indi-
NPN transistor is controlled by the two circuits described
cates that output voltage is above VRT(ON). Otherwise, the
(see Block Diagram).
Delay lead sinks current to ground (used to discharge the
delay capacitor). The discharge current is latched ON
Low Voltage Inhibit Circuit when the output voltage is below VRT(OFF). The Delay
The Low Voltage Inhibit Circuit monitors output voltage, capacitor is fully discharged anytime the output voltage
and when output voltage is below the specified minimum, falls out of regulation, even for a short period of time. This
causes the RESET output transistor to be in the ON (satu- feature ensures that a controlled RESET pulse is generated
ration) state. When the output voltage is above the speci- following detection of an error condition. The circuit
fied level, this circuit permits the RESET output transistor allows the RESET output transistor to go to the OFF (open)
to go into the OFF state if allowed by the RESET Delay cir- state only when the voltage on the Delay lead is higher
cuit. than VDC(HI).

Test Circuit

VIN VOUT
CIN*
100nF RRST COUT**
CS8122 4.7kW
10mF

Delay RESET
Gnd

CDelay
0.1mF

*CIN required if regulator is far from power source filter.

**COUT required for stability.

5
CS8122 Application Notes

Stability Considerations for this tolerance plus the variation which will occur at
low temperatures. The ESR of the capacitor should be less
The output or compensation capacitor helps determine than 50% of the maximum allowable ESR found in step 3
three main characteristics of a linear regulator: start-up above.
delay, load transient response and loop stability.
The capacitor value and type should be based on cost, Calculating Power Dissipation
availability, size and temperature constraints. A tantalum
in a Single Output Linear Regulator
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instabil- The maximum power dissipation for a single output regu-
ity. The aluminum electrolytic capacitor is the least expen- lator (Figure 1) is:
sive solution, but, if the circuit operates at low tempera-
PD(max)={VIN(max)ÐVOUT(min)}IOUT(max)+VIN(max)IQ (1)
tures (-25¡C to -40¡C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufac- where
turers data sheet usually provides this information.
VIN(max) is the maximum input voltage,
The value for the output capacitor COUT shown in the test
and applications circuit should work for most applica- VOUT(min) is the minimum output voltage,
tions, however it is not necessarily the optimized solution. IOUT(max) is the maximum output current for the applica-
To determine an acceptable value for COUT for a particular tion, and
application, start with a tantalum capacitor of the recom- IQ is the quiescent current the regulator consumes at
mended value and work towards a less expensive alterna- IOUT(max).
tive part.
Step 1: Place the completed circuit with a tantalum capac-
Once the value of PD(max) is known, the maximum permis-
itor of the recommended value in an environmental cham-
sible value of RQJA can be calculated:
ber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the 150¡C - TA (2)
RQJA =
higher ESR of an aluminum capacitor. Leave the decade PD
box outside the chamber, the small resistance added by
the longer leads is negligible. The value of RQJA can then be compared with those in
the package section of the data sheet. Those packages
Step 2: With the input voltage at its maximum value, with RQJA's less than the calculated value in equation 2
increase the load current slowly from zero to full load will keep the die temperature below 150¡C.
while observing the output for any oscillations. If no oscil-
lations are observed, the capacitor is large enough to In some cases, none of the packages will be sufficient to
ensure a stable design under steady state conditions. dissipate the heat generated by the IC, and an external
heatsink will be required.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage condi-
tions. IIN
Step 5: If the capacitor is adequate, repeat steps 3 and 4 IOUT
VIN Smart
with the next smaller valued capacitor. A smaller capaci- Regulator VOUT
tor will usually cost less and occupy less board space. If
the output oscillates within the range of expected operat-
ing conditions, repeat steps 3 and 4 with the next larger
standard capacitor value.
Step 6: Test the load transient response by switching in
} Control
Features

various loads at several frequencies to simulate its real

working environment. Vary the ESR to reduce ringing. IQ
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regula- Figure 1: Single output regulator with key performance parameters
tor performance. Most good quality aluminum electrolytic labeled.
capacitors have a tolerance of ± 20% so the minimum
value found should be increased by at least 50% to allow

6
 CS8122
Application Notes: continued

Heat Sinks where:

RQJC = the junctionÐtoÐcase thermal resistance,
A heat sink effectively increases the surface area of the
RQCS = the caseÐtoÐheatsink thermal resistance, and
package to improve the flow of heat away from the IC and
into the surrounding air. RQSA = the heatsinkÐtoÐambient thermal resistance.
Each material in the heat flow path between the IC and the RQJC appears in the package section of the data sheet. Like
outside environment will have a thermal resistance. Like RQJA, it too is a function of package type. RQCS and RQSA
series electrical resistances, these resistances are summed are functions of the package type, heatsink and the inter-
to determine the value of RQJA: face between them. These values appear in heat sink data
sheets of heat sink manufacturers.
RQJA = RQJC + RQCS + RQSA (3)

7
CS8122 Package Specification
PACKAGE DIMENSIONS IN mm(INCHES) PACKAGE THERMAL DATA

Thermal Data 5 Lead TO-220

5 Lead TO-220 (T) Straight RQJC typ 2.1 ûC/W
RQJA typ 50 ûC/W

1.40 (.055)
4.83 (.190) 1.14 (.045)
5 Lead TO-220 (TVA) Vertical
10.54 (.415) 4.06 (.160)
9.78 (.385) 4.83 (.190)
3.96 (.156) 4.06 (.160)
2.87 (.113) 3.71 (.146)
6.55 (.258) 2.62 (.103) 3.96 (.156)
10.54 (.415)
5.94 (.234) 3.71 (.146) 1.40 (.055)
9.78 (.385) 1.14 (.045)
14.99 (.590)
14.22 (.560)
6.55 (.258)
5.94 (.234)
2.87 (.113) 14.99 (.590)
2.62 (.103) 14.22 (.560)

14.22 (.560)
13.72 (.540)
1.78 (.070)
2.92 (.115)
2.29 (.090)
1.02 (.040)
8.64 (.340)
0.76 (.030)
7.87 (.310)
4.34 (.171)
7.51 (.296)
0.56 (.022) 0.56 (.022)
1.02(.040) 1.83(.072) 1.68
0.36 (.014) 1.70 (.067) (.066) typ 0.36 (.014)
0.63(.025) 1.57(.062)

6.93(.273) 6.80 (.268)

2.92 (.115)
6.68(.263)
2.29 (.090) .94 (.037)
.69 (.027)

5 Lead TO-220 (THA) Horizontal

4.83 (.190)
10.54 (.415) 4.06 (.160)
1.40 (.055)
9.78 (.385) 3.96 (.156) 1.14 (.045)
3.71 (.146)
2.87 (.113)
2.62 (.103)

14.99 (.590)
6.55 (.258) 14.22 (.560)
5.94 (.234)

2.77 (.109)
6.83 (.269)

1.68 0.56 (.022) 2.92 (.115)

(.066) 2.29 (.090)
0.81(.032) 0.36 (.014)
TYP 6.60 (.260)
1.70 (.067) 5.84 (.230)
6.81(.268)

Ordering Information

Part Number Description

CS8122YT5 5 Lead TO-220 Straight Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
CS8122YTHA5 5 Lead TO-220 Horizontal
notice. Please contact Cherry Semiconductor
CS8122YTVA5 5 Lead TO-220 Vertical Corporation for the latest available information.
Rev. 2/5/99 © 1999 Cherry Semiconductor Corporation
8
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