VERILOG

Verilog is a Hardware Description Language (HDL). It is used to describe the

structure and behaviour of any electronic circuit.

Syntax :
1. Comments : It makes the code more readable.
// single line comment
/* */  multiline comment

2.Case Sensitive :
input x;
input X;
these both are different

3.keywords :
Special words used in verilog.

5. Identifier :
Used to identify an object like module, input or output port etc.
module ha
input a
6. Number Specification :
Syntax:
<size>'<base_format> <number>
base format : b -> binary
d -> decimal
h -> hexa
o -> octal
Example:
4'b 1001

Data types in verilog :

Desribes the type of data a variable can have.
1. net (wire, wand, wor)
2. register (reg, integer, real, time)
3. strings

1.net data type : It is used to connect 2 components (similar to electrical wire).

It is used when there is continuous assignment.
It's default value is z.
Example : wire [2:0] a

When multiple drivers are driving

a wire, outputs of the drivers are
shorted together.

wire
wor and wand insets an OR/AND gate at the connection

wor

wand
2.Register
a. reg : It can store value between assignments.
Example : reg a;
reg [2:0] a;

b. integer : It is a signed integer variable of 32 bits wide.

Example : interger a;

c. real : It is a signed floating point value.

Example : real f;
f = 4e10; //4x10^10

d. time : It is an unsigned integer variable and it is 64 bits wide. It is used to

store simulation time.
Example : time s;

3. strings : It is a sequence of characters enclosed in " ". It is stored in reg

variable.
Example :
reg [8*28 : 0] st; //st is 29 bytes long
Note: Each char is 1 byte long (8 bits).
Vectors and Arrays :
Vector:
It is a single element that is n bits wide
Example : reg [3:0] a; //stores 4 bit of data -->vector

Arrays:
Arrays are multiple elements which can either be 1-bit or n-bits
syntax : <datatype> <name> <row width> <column width>
Example:
integer count [0:7];
0
1
2
3
4
5
6
7

count[2] = 0
integer count [2:0] [3:0]; // here each element is single bit wide
2,3 2,2 2,1 2,0
1,3 1,2 1,1 1,0
0,3 0,2 0,1 0,0

[0:2] [0:3]
0,0 0,1 0,2 0,3
1,0 1,1 1,2 1,3
2,0 2,1 2,2 2,3

count [0][1] =1
integer [2:0] count [2:0] [3:0]; //same as above. But here each element is 3 bits
wide.
count [0][0] = 3’b 001;

Operators in verilog :
1. Bitwise operators --> unary, binary
a. unary bitwise operators : has only 1 operand
& - and
| - or
~ - not
~& - nand
~| - nor
Example :
a = 4'b 1001
&a = (1)&(0)&(0)&(1)
= (0)&(0)&(1)
=0&1
= 1'b 0

Note : Unary bitwise are also called as reduction operators beacuse they reduce
the no.of bits.

b. binary bitwise operators : have 2 operands

Example:
a = 2'b 10
b = 2'b 11
a&b = 10 & 11 = 2’b 10
a|b = 10 | 11 = 2’b 11

2. Arithmetic operators:
+, -, *, /, %

3. Relational operators :
It compares 2 values and returns either 1 or 0.
a = 3'b 001 b = 3'b 100
a>b --> 0
a<b -->1

4.Equality operators :
It compares 2 values and returns either 1 or 0.
a = 3'b 001 b = 3'b 100
a == b --> 0

5.Logical operators :
&&, ||, !
a = 3'b 101 (non zero)
b = 3'b 110 (non zero)
a && b = 1
a || b = 1
!a = 0
6. Concatenation operators :
{}
It combines 2 or more data
a = 3’b 101
b = 4’ b 1001
{a,b} = 7’b 1011001
{b,a} = 7’b 1001101

7.Replication operators :
It is used to replicate the data.
Y = {3{2’b10}} = 6’b 101010

8. Conditional operators : ?:
Syntax:
Output = condition to be checked ? True value : False value

9. Shift operators :
>>  right shift
<<  left shift
Shifted bits are lost and zeroes are filled.
a = 4’b 1010
a <<2 = 1000
b = 4’1010
b >> 1 = 4’b 0101
module :
It is the building block in Verilog.
Syntax :
module <module_name> (port_list);
<port declaration>
<functionality>
endmodule

Ports:
They are used to send or receive data from outside world.
input : design module receives data from outside world using input port.
output : design module sends data from this port.
inout : design module sends out data from this port

Modelling Styles in Verilog :

Three types:
1. Gate level : In this modelling, we design circuit using basic gates. This
modelling is used for small designs .

2. Data flow : Digital systems are designed in terms of its function. It uses
Boolean expression and operators.

3. Behavioural modelling : It defines the behaviour of a digital component.

It does not give any information of how the circuit will be implemented
in actual hardware. It is implemented using procedural block such as
always or initial block.
Example :
Implement half adder using
1. Gate level modelling :

module ha(a,b,sum,carry);
input a,b;
output sum,carry;

xor g1(sum,a,b);
and g2(carry,a,b);

endmodule

2. Data flow modelling :

module ha(a,b,sum,carry);
input a,b;
output sum,carry;

assign sum = a^b;

assign carry = a&b;

endmodule

3. Behavioural modelling :
module ha(a,b,sum,carry);
input a,b;
output reg sum,carry;

always@(a or b)begin
case({a,b})
2'b00:begin
sum = 1'b0;
carry = 1'b0;
end
 2'b01:begin
sum = 1'b1;
carry = 1'b0;
end

2'b10:begin
sum = 1'b1;
carry = 1'b0;
end

2'b11:begin
sum = 1'b0;
carry = 1'b1;
end

endcase
end
endmodule

Structural modelling :
It refers to describing a design using module instances.
Structural model is a module that instantiates other modules and verilog
primitives.
Example : FA using HA
4 bit ripple carry adder
Procedural Blocks :
1. always block :
o All statements inside always block is executed sequentially.
o A single module can have multiple always blocks and they all run
simultaneously at time = 0.
o always block executes continuously at t = 0 and repeatedly
thereafter.

2. initial block :
o All statements inside initial block is executed sequentially.
o There can be more than 1 initial block in a single module. All
initial blocks execute simultaneously at time = 0.They are
executed parallely.
o Initial block executes only once, starting at t = 0.

Example :
initial block
reg v1, v2, v3, v4;
initial begin
v1 = 1;
#2 v2 = v1 +1;
v3 = v2 +1;
#2 v4 = v3 +1;
v1 = v4 +1;
#2 v2 = v1 +1;
v3 = v2 +1;
end

V1 V2 V3 V4
0 1 x x x
2 1 2 3 x
4 5 2 3 4
6 5 6 7 4
always block :
reg v1, v2, v3, v4;
always begin
v1 = 1;
#2 v2 = v1 +1;
v3 = v2 +1;
#2 v4 = v3 +1;
v1 = v4 +1;
#2 v2 = v1 +1;
v3 = v2 +1;
end

V1 V2 V3 V4
0 1 x x x
2 1 2 3 x
4 5 2 3 4
6 1 6 7 4
Blocking and non -blocking assignments :
Blocking : One statement blocks the execution of other statements until it is
executed.
“=” operator is used to specify blocking assignments.
Used for combinational logic design.

Non-Blocking : Non-blocking assignments executes in parallel.

The execution of next statement is not blocked.
“<=” operator is used to specify non-blocking assignments.
Used for sequential logic design.

if else statement :
if (<expression>)
statement;
else
statement;

case statement : It will begin with a case and endcase. The expression within
parantheses will be evaluated exactly once and it is compared with the list of
alternatives in the order they are written and the statements for which the
alternative matches the given expression will be executed.
Example :
case({s1,s0})
2'b00:begin
y=i0;
end
2'b01:begin
y=i1;
end
2'b10:begin
 y=i2;
end
2'b11:begin
y=i3;
end
endcase

for loop :
Syntax:
for (initialization; condition; increment)
begin
<body of for loop>
end

while loop :
Syntax :
Initialization
while (condition)
begin
//statements
end

while (1)  runs forever

forever loop in Verilog :
It is equivalent to while (1). This loop does not contain any expression and
executes forever until $finish is encountered. It can be excited using disable
statements.
Example :
initial begin
clk_tb = 0;
forever
#10 clk_tb = ~clk_tb;
end

repeat block :
It is a loop which repeats a block of code or a given statement a fixed no. of
times (the no. of times we specify).
Example :
repeat(20) begin
a_tb=$random;
b_tb=$random;
c_tb=$random;
#10;
end
Generate block :
It is used when the same operation is repeated for multiple times.
It starts with keyword generate and endgenerate.
Generate loop
genvar is used as a loop variable.
Example :
genvar I;
generate
for (I=0; I<=n-1; I=I+1)
assign out [I] =a[I] &b [I];
endgenerate

Generate conditional
generate
if (mod == 1)
upcount uc (clk,reset,count);
else if (mod == 0)
downcount dc (clk,reset,count);
endgenerate

Generate case
generate
case (n)
1 : upcount uc (clk,reset,count);
2 : downcount dc (clk,reset,count);
endcase
endgenerate
fork-join :
Parallel blocks are specified by keywords fork and join. All the statements start
at the time when the block was entered. Thus the order in which the statements
are written in the block is not important.
Example :
fork
x = 1’b 0; //starts at time 0
#5 y =1’b1; //starts at time 5
#10 z = 2’b 10 ; //starts at time 10
join

Note :
Reference Link of that code:
https://www.fpga4student.com/2017/02/verilog-code-for-d-flip-flop.html
Testbench :
Once the design block is completed, it must be tested to check its functionality.
So testbenches are written to check the functionality.
Structure :
include design_file_name
module testbench_name
//data type declaration
//instantiation of the design to be tested
//test pattern generation
//monitoring the response

$monitor() : It is used to continuously monitor changes in the value of elements

in the sensitivity list.
It gets executed when there is a change in the argument.

$display() : It is used for displaying variables at a selected time.

It gets executed when the tool executes the particular statement.
It is used for debugging purpose.
We can have a no. of $display in our code.

$finish : It exits the simulation.

$stop : It suspends the simulation and puts the simulator in inactive state.
$random : It will generate a 32 bit random number. The LSB bit will be
assigned.