74AHC139 Nexperia
74AHC139 Nexperia
74AHC139 Nexperia
1. General description
The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
2. Features
n Balanced propagation delays
n All inputs have Schmitt-trigger actions
n Inputs accept voltages higher than VCC
n Input levels:
u For 74AHC139: CMOS level
u For 74AHCT139: TTL level
n ESD protection:
u HBM EIA/JESD22-A114E exceeds 2000 V
u MM EIA/JESD22-A115-A exceeds 200 V
u CDM EIA/JESD22-C101C exceeds 1000 V
n Multiple package options
n Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC139
74AHC139D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; SOT109-1
body width 3.9 mm
74AHC139PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
Nexperia 74AHC139; 74AHCT139
Dual 2-to-4 line decoder/demultiplexer
4. Functional diagram
1E DX 0 4 X/Y 0 4
4 2 2
1Y0 0 5 1 5
2 5 0 1 1
1A0 1Y1 3 G 3
1 3 6 2 6
3 6 1 2 1 2
1A1 1Y2 7 EN 7
7 3 3
1Y3
12
2Y0 12 12
14 11 DX 0 X/Y 0
2A0 2Y1 14 14
0 0 1 11 1 11
13 10 13 G 13 1
2A1 2Y2 1 3 10 2 10
9 15 2 15 2
2Y3 9 EN 9
2E 3 3
1Y0 4
2 1A0 1Y1 5
3 1A1 DECODER 1Y2 6
1Y3 7
1 1E
2Y0 12
14 2A0 2Y1 11
13 2A1 DECODER 2Y2 10
2Y3 9
15 2E
mna780
5. Pinning information
5.1 Pinning
1E 1 16 VCC
1A0 2 15 2E
1A1 3 14 2A0
1Y0 4 13 2A1
139
1Y1 5 12 2Y0
1Y2 6 11 2Y1
1Y3 7 10 2Y2
GND 8 9 2Y3
001aad029
6. Functional description
Table 3. Function table[1]
Control Input Output
nE nA0 nA1 nY0 nY1 nY2 nY3
H X X H H H H
L L L L H H H
H L H L H H
L H H H L H
H H H H H L
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
VI input voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] −20 +20 mA
IO output current VO = −0.5 V to (VCC + 0.5 V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C [2] - 500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC139
VIH HIGH-level VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
input voltage VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
input voltage VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level VI = VIH or VIL
output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
VI
nAn input VM
GND
t PHL t PLH
VOH
nYn output VM
VOL
mna782
VI
nE input VM
GND
tPHL tPLH
VOH
nYn output VM
VOL
mna783
tW
VI
90 %
negative
VM VM
pulse
10 %
GND
tf tr
tr tf
VI
90 %
positive
VM VM
pulse
10 %
GND tW
VCC
VI VO
G DUT
RT CL
001aah768
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D E A
X
y HE v M A
16 9
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
99-12-27
SOT109-1 076E07 MS-012
03-02-19
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D E A
X
y HE v M A
16 9
Q
A2 (A 3)
A
A1
pin 1 index
θ
Lp
L
1 8
detail X
w M
e bp
0 2.5 5 mm
scale
mm 1.1
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8o
0.25 0.65 1 0.2 0.13 0.1 o
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.06 0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
99-12-27
SOT403-1 MO-153
03-02-18
13. Abbreviations
Table 10. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14