74LVC139

Dual 2-to-4 line decoder/demultiplexer

Rev. 5 — 19 October 2011 Product data sheet

1. General description
The 74LVC139 is a dual 2-to-4 line decoder/demultiplexer. It has two independent
decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four
mutually exclusive outputs (nY0 to nY3) that are LOW when selected. Each decoder has
an active LOW input (nE). When nE is HIGH, every output is forced HIGH. The enable
input can be used as the data input for a 1-to-4 demultiplexer application.

2. Features and benefits

 Wide supply voltage range from 1.2 V to 3.6 V
 Inputs accept voltages up to 5.5 V
 CMOS low power consumption
 Direct interface with TTL levels
 Demultiplexing capability
 Two independent 2-to-4 decoders
 Multifunction capability
 Mutually exclusive outputs
 Output drive capability 50  transmission lines at 125 C
 Complies with JEDEC standard:
 JESD8-7A (1.65 V to 1.95 V)
 JESD8-5A (2.3 V to 2.7 V)
 JESD8-C/JESD36 (2.7 V to 3.6 V)
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-B exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Specified from 40 C to +85 C and from 40 C to +125 C
NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC139D 40 C to +125 C SO16 plastic small outline package; 16 leads; SOT109-1
body width 3.9 mm
74LVC139DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1
body width 5.3 mm
74LVC139PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74LVC139BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5  3.5  0.85 mm

4. Functional diagram

1E DX 0 4 X/Y 0 4
4 2 2
1Y0 0 5 1 5
2 5 0 1 1
1A0 1Y1 3 G 3
1 3 6 2 6
3 6 1 2 1 2
1A1 1Y2 7 EN 7
7 3 3
1Y3
12
2Y0 12 12
14 11 DX 0 X/Y 0
2A0 2Y1 14 14
0 0 1 11 1 11
13 10 13 G 13 1
2A1 2Y2 1 3 10 2 10
9 15 2 15 2
2Y3 9 EN 9
2E 3 3

15 mna779 (a) (b) mna781

a) demultiplexer
b) decoder
Fig 1. Logic symbol Fig 2. IEC logic symbol

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Product data sheet Rev. 5 — 19 October 2011 2 of 16

NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

1Y0 4
2 1A0 1Y1 5
3 1A1 DECODER 1Y2 6
1Y3 7

1 1E

2Y0 12
14 2A0 2Y1 11
13 2A1 DECODER 2Y2 10
2Y3 9

15 2E

mna780

Fig 3. Functional diagram

5. Pinning information

5.1 Pinning

16 VCC
1E 1 16 VCC terminal 1 1E
index area
1

1A0 2 15 2E
1A0 2 15 2E
1A1 3 14 2A0 3 14 2A0
1A1

1Y0 4 13 2A1 1Y0 4 13 2A1

139 139
1Y1 5 12 2Y0
1Y1 5 12 2Y0
1Y2 6 GND(1) 11 2Y1
1Y2 6 11 2Y1
1Y3 7 10 2Y2
8

1Y3 7 10 2Y2
GND

2Y3

GND 8 9 2Y3 001aad031

001aad029 Transparent top view

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as a
supply pin or input.
Fig 4. Pin configuration SO16 and (T)SSOP16 Fig 5. Pin configuration DHVQFN14

5.2 Pin description

Table 2. Pin description
Name Pin Description
1E 1 enable input (active LOW)
2E 15 enable input (active LOW)
1A[0:1] 2, 3 address input
2A[0:1] 14, 13 address input
1Y[0:3] 4, 5, 6, 7 output
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Product data sheet Rev. 5 — 19 October 2011 3 of 16

NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

Table 2. Pin description …continued

Name Pin Description
2Y[0:3] 12, 11, 10, 9 output
GND 8 ground (0 V)
VCC 16 positive supply voltage

6. Functional description
Table 3. Function table[1]
Input Output
nE nA0 nA1 nY0 nY1 nY2 nY3
H X X H H H H
L L L L H H H
L H L H L H H
L L H H H L H
L H H H H H L

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care

7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 50 - mA
VI input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA
VO output voltage [2] 0.5 VCC + 0.5 V
IO output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C [3] - 500 mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO16 packages: above 70 C derate linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C derate linearly with 4.5 mW/K.

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Product data sheet Rev. 5 — 19 October 2011 4 of 16

NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

8. Recommended operating conditions

Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V
VI input voltage 0 - 5.5 V
VO output voltage 0 - VCC V
Tamb ambient temperature in free air 40 +125 C
t/V input transition rise and fall VCC = 1.65 V to 2.7 V 0 - 20 ns/V
rate VCC = 2.7 V to 3.6 V 0 - 10 ns/V

9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min Max
VIH HIGH-level VCC = 1.2 V 1.08 - - 1.08 - V
input voltage VCC = 1.65 V to 1.95 V 0.65  VCC - - 0.65  VCC - V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level VCC = 1.2 V - - 0.12 - 0.12 V
input voltage VCC = 1.65 V to 1.95 V - - 0.35  VCC - 0.35  VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level VI = VIH or VIL
output IO = 100 A; VCC  0.2 - - VCC  0.3 - V
voltage VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V
IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V
IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level VI = VIH or VIL
output IO = 100 A; - - 0.2 - 0.3 V
voltage VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V
IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V
IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V
IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V
II input leakage VCC = 3.6 V; VI = 5.5 V or GND - 0.1 5 - 20 A
current

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Product data sheet Rev. 5 — 19 October 2011 5 of 16

NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

Table 6. Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min Max
ICC supply VCC = 3.6 V; VI = VCC or GND; - 0.1 10 - 40 A
current IO = 0 A
ICC additional per input pin ; - 5 500 - 5000 A
supply VCC = 2.7 V to 3.6 V;
current VI = VCC  0.6 V; IO = 0 A
CI input VCC = 0 V to 3.6 V; - 5.0 - - - pF
capacitance VI = GND to VCC

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.

10. Dynamic characteristics

Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min Max
tpd propagation delay nAn to Yn; see Figure 6 [2]

VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 0.5 4.7 10.4 0.5 11.3 ns
VCC = 2.3 V to 2.7 V 1.0 2.8 5.9 1.0 6.5 ns
VCC = 2.7 V 1.0 3.0 6.3 1.0 8.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.5 5.3 1.0 7.0 ns
nE to Yn; see Figure 7 [2]

VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 1.5 4.5 9.8 1.5 10.7 ns
VCC = 2.3 V to 2.7 V 2.1 2.7 5.6 2.1 6.1 ns
VCC = 2.7 V 1.0 2.8 5.4 1.0 7.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.4 5.0 1.0 6.5 ns
tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power dissipation VI = GND to VCC [4]

capacitance VCC = 1.65 V to 1.95 V - 5.6 - - - pF

VCC = 2.3 V to 2.7 V - 11.3 - - - pF
VCC = 3.0 V to 3.6 V - 16.4 - - - pF

[1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching,

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Dual 2-to-4 line decoder/demultiplexer

(CL  VCC2  fo) = sum of outputs.

11. Waveforms

VI VI

nAn input VM nE input VM

GND GND
t PHL t PLH tPHL tPLH
VOH VOH

nYn output VM nYn output VM

VOL VOL
mna782 mna783

VM = 1.5 V at VCC  2.7 V. VM = 1.5 V at VCC  2.7 V.

VM = 0.5  VCC at VCC < 2.7 V. VM = 0.5  VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage levels that VOL and VOH are the typical output voltage levels that
occur with the output load. occur with the output load.
Fig 6. Input (nAn) to output (nYn) propagation delays Fig 7. Enable input (nE) to output (nYn) propagation
delays

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NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr

tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW

VCC

VI VO
PULSE
DUT
GENERATOR
RT CL RL

001aaf615

Test data is given in Table 8.

Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 8. Load circuitry for switching times

Table 8. Test data

Supply voltage Input Load
VI tr, tf CL RL
1.2 V VCC  2 ns 30 pF 1 k
1.65 V to 1.95 V VCC  2 ns 30 pF 1 k
2.3 V to 2.7 V VCC  2 ns 30 pF 500 
2.7 V 2.7 V  2.5 ns 50 pF 500 
3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500 

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Product data sheet Rev. 5 — 19 October 2011 8 of 16

NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

12. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

D E A
X

y HE v M A

16 9

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 8 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8o
o
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT109-1 076E07 MS-012
03-02-19

Fig 9. Package outline SOT109-1 (SO16)

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NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

D E A
X

c
y HE v M A

16 9

Q
A2 A
A1 (A 3)

pin 1 index
θ
Lp
L

1 8 detail X

w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.

mm 2
0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.00 8o
0.25 0.65 1.25 0.2 0.13 0.1 o
0.05 1.65 0.25 0.09 6.0 5.2 7.6 0.63 0.7 0.55 0

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT338-1 MO-150
03-02-19

Fig 10. Package outline SOT338-1 (SSOP16)

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Dual 2-to-4 line decoder/demultiplexer

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

D E A
X

y HE v M A

16 9

Q
A2 (A 3)
A
A1
pin 1 index

θ
Lp
L
1 8
detail X
w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.

mm 1.1
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8o
0.25 0.65 1 0.2 0.13 0.1 o
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.06 0

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT403-1 MO-153
03-02-18

Fig 11. Package outline SOT403-1 (TSSOP16)

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Dual 2-to-4 line decoder/demultiplexer

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm SOT763-1

D B A

A
A1
E c

terminal 1 detail X
index area

terminal 1 C
e1
index area
e b v M C A B y1 C y
w M C
2 7

1 8

Eh e

16 9

15 10
Dh
X

0 2.5 5 mm

scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT
max.
A1 b c D (1) Dh E (1) Eh e e1 L v w y y1

mm 0.05 0.30 3.6 2.15 2.6 1.15 0.5

1 0.2 0.5 2.5 0.1 0.05 0.05 0.1
0.00 0.18 3.4 1.85 2.4 0.85 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

02-10-17
SOT763-1 --- MO-241 ---
03-01-27

Fig 12. Package outline SOT763-1 (DHVQFN16)

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Dual 2-to-4 line decoder/demultiplexer

13. Abbreviations
Table 9. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic

14. Revision history

Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC139 v.5 20111019 Product data sheet - 74LVC139 v.4
Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.
74LVC139 v.4 040315 Product specification - 74LVC139 v.3
74LVC139 v.3 030519 Product specification - 74LVC139 v.2
74LVC139 v.2 980428 Product specification - 74LVC139 v.1
74LVC139 v.1 - - - -

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Dual 2-to-4 line decoder/demultiplexer

15. Legal information

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Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
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information is available on the Internet at URL http://www.nxp.com.

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Limited warranty and liability — Information in this document is believed to Limiting values — Stress above one or more limiting values (as defined in
be accurate and reliable. However, NXP Semiconductors does not give any the Absolute Maximum Ratings System of IEC 60134) will cause permanent
representations or warranties, expressed or implied, as to the accuracy or damage to the device. Limiting values are stress ratings only and (proper)
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contract or any other legal theory. sale, as published at http://www.nxp.com/profile/terms, unless otherwise
Notwithstanding any damages that customer might incur for any reason agreed in a valid written individual agreement. In case an individual
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards agreement is concluded only the terms and conditions of the respective
customer for the products described herein shall be limited in accordance agreement shall apply. NXP Semiconductors hereby expressly objects to
with the Terms and conditions of commercial sale of NXP Semiconductors. applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without No offer to sell or license — Nothing in this document may be interpreted or
limitation specifications and product descriptions, at any time and without construed as an offer to sell products that is open for acceptance or the grant,
notice. This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or
to the publication hereof. other industrial or intellectual property rights.

Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein
authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior
safety-critical systems or equipment, nor in applications where failure or authorization from competent authorities.

74LVC139 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 5 — 19 October 2011 14 of 16

NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

Non-automotive qualified products — Unless this data sheet expressly NXP Semiconductors’ specifications such use shall be solely at customer’s
states that this specific NXP Semiconductors product is automotive qualified, own risk, and (c) customer fully indemnifies NXP Semiconductors for any
the product is not suitable for automotive use. It is neither qualified nor tested liability, damages or failed product claims resulting from customer design and
in accordance with automotive testing or application requirements. NXP use of the product for automotive applications beyond NXP Semiconductors’
Semiconductors accepts no liability for inclusion and/or use of standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer 15.4 Trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the
Notice: All referenced brands, product names, service names and trademarks
product for such automotive applications, use and specifications, and (b)
are the property of their respective owners.
whenever customer uses the product for automotive applications beyond

16. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVC139 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 5 — 19 October 2011 15 of 16

NXP Semiconductors 74LVC139
Dual 2-to-4 line decoder/demultiplexer

17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2011. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 October 2011
Document identifier: 74LVC139
Mouser Electronics

Authorized Distributor

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