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    Soc Updated Practical List

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    pankaj chandankhede
    This document outlines the experiments for the Advanced Communication Engineering laboratory course. The course objectives are to teach students SOC modeling, interfacing, design, prototyping, verification, testing and physical design. The 10 listed experiments will have students write VHDL code to design a CPU, memory modules, FIFO and UART peripherals and integrate them onto a SOC. Students will simulate the design and verify functionality on an FPGA board. Open ended experiments include measuring power consumption and evaluating performance improvements from a co-processor. The course is intended to help students achieve outcomes of designing real-life SOC prototypes and analyzing design issues.

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    Soc Updated Practical List

    Uploaded by

    pankaj chandankhede
    47 views2 pages
    This document outlines the experiments for the Advanced Communication Engineering laboratory course. The course objectives are to teach students SOC modeling, interfacing, design, prototyping, verification, testing and physical design. The 10 listed experiments will have students write VHDL code to design a CPU, memory modules, FIFO and UART peripherals and integrate them onto a SOC. Students will simulate the design and verify functionality on an FPGA board. Open ended experiments include measuring power consumption and evaluating performance improvements from a co-processor. The course is intended to help students achieve outcomes of designing real-life SOC prototypes and analyzing design issues.

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    SOC UPDATED PRACTICAL LIST

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    This document outlines the experiments for the Advanced Communication Engineering laboratory course. The course objectives are to teach students SOC modeling, interfacing, design, prototyping, verification, testing and physical design. The 10 listed experiments will have students write VHDL code to design a CPU, memory modules, FIFO and UART peripherals and integrate them onto a SOC. Students will simulate the design and verify functionality on an FPGA board. Open ended experiments include measuring power consumption and evaluating performance improvements from a co-processor. The course is intended to help students achieve outcomes of designing real-life SOC prototypes and analyzing design issues.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    47 views2 pages

    Soc Updated Practical List

    Uploaded by

    pankaj chandankhede
    This document outlines the experiments for the Advanced Communication Engineering laboratory course. The course objectives are to teach students SOC modeling, interfacing, design, prototyping, verification, testing and physical design. The 10 listed experiments will have students write VHDL code to design a CPU, memory modules, FIFO and UART peripherals and integrate them onto a SOC. Students will simulate the design and verify functionality on an FPGA board. Open ended experiments include measuring power consumption and evaluating performance improvements from a co-processor. The course is intended to help students achieve outcomes of designing real-life SOC prototypes and analyzing design issues.

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    DEPARTMENT OF ELECTRONICS ENGINEERING AND ELECTRONICS &

    TELECOMMUNICATION ENGINEERING

    B.TECH IN ELECTRONICS ENGINEERING AND ELECTRONICS &


    TELECOMMUNICATION ENGINEERING

    LIST OF EXPERIMENTS
    Name of Laboratory: Advanced Communication Engg, VLSI Location: E-15 (A) , E-28
    Course Code:UECP417 Course Name : System on Chip Semester: VII
    Session: 2023-24: (Winter-23)
    Course Objectives: Course Outcomes: Student shall be able to:
    1. The student will study SOC modelling and
    interfacing CO-1: Design the SOC prototype for real life applications.
    2. The student will learn SOC system design.
    3. SOC design, SOC prototyping, verification, CO-2: Analyse the various SOC design issues like clock
    testing and physical design. domain crossing.
    4. The student will able to design, implement
    CO-3 Perform power and timing analysis.
    and test SOC.

    Sr. Name of Experiments Mapping with


    No. Course Outcomes
    1 Understand the Concept of System on Chip and Its Significance In Modern Electronic Devices CO1
    2 Write the VHDL code for the CPU, including the instruction set and the control unit. CO1, CO2
    3 Design the memory module for the SoC. Implement different types of memory like RAM, CO1, CO2
    ROM, and cache (optional) using VHDL.
    4 Write the VHDL code for the FIFO module and verify its functionality through simulation. CO1, CO2
    5 Design the peripheral module (UART) using VHDL and implement its functionalities like CO1, CO2
    data transmission and reception.
    6 Implement the interconnections between CPU, memory, and peripheral modules using VHDL, CO1, CO2
    typically using a bus architecture.
    7 Simulate the entire SoC design using the VHDL simulation software. CO1, CO2
    8 Verify the functionality of the SoC on the physical FPGA board. CO1, CO2,CO3
    Open Ended Experiments
    9 Measure and analyze the power consumption of the SoC during simulation and/or FPGA CO3
    implementation to assess the effectiveness of the low-power techniques.
    10 Evaluate the performance improvement achieved by using the co-processor for specific CO1, CO2,CO3
    applications.

    Dr. Pankaj Chandankhede Dr.Abhijit Titarmare


    Dr. Wani Patil Dr. Swati Sorte Dr. Laxman Thakre Dr. Atul Deshmukh
    Course Teachers Lab Incharges HOD ETRX Dept. HOD ETC Dept.

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