Pic32mx1xx2xx283644-Pin Datasheet Ds60001168l
Pic32mx1xx2xx283644-Pin Datasheet Ds60001168l
Pic32mx1xx2xx283644-Pin Datasheet Ds60001168l
Packages
Type SOIC SSOP SPDIP QFN VTLA TQFP
Pin Count 28 28 28 28 44 36 44 44
I/O Pins (up to) 21 21 21 21 34 25 34 34
Contact/Lead Pitch 1.27 0.65 0.100'' 0.65 0.65 0.50 0.50 0.80
Dimensions 17.90x7.50x2.65 10.2x5.3x2 1.365''x.285''x.135'' 6x6x0.9 8x8x0.9 5x5x0.9 6x6x0.9 10x10x1
Note: All dimensions are in millimeters (mm) unless specified.
Timers(2)/Capture/Compare
External Interrupts(3)
DMA Channels
Remappable Pins
Packages
I/O Pins
Device
CTMU
RTCC
JTAG
PMP
Pins
I2C
SPI/I2S
UART
SOIC,
SSOP,
PIC32MX110F016B 28 16+3 4 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y
SPDIP,
QFN
PIC32MX110F016C 36 16+3 4 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA
VTLA,
PIC32MX110F016D 44 16+3 4 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP,
QFN
SOIC,
SSOP,
PIC32MX120F032B 28 32+3 8 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y
SPDIP,
QFN
PIC32MX120F032C 36 32+3 8 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA
VTLA,
PIC32MX120F032D 44 32+3 8 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP,
QFN
SOIC,
SSOP,
PIC32MX130F064B 28 64+3 16 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y
SPDIP,
QFN
PIC32MX130F064C 36 64+3 16 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA
VTLA,
PIC32MX130F064D 44 64+3 16 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP,
QFN
SOIC,
SSOP,
PIC32MX150F128B 28 128+3 32 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y
SPDIP,
QFN
PIC32MX150F128C 36 128+3 32 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA
VTLA,
PIC32MX150F128D 44 128+3 32 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP,
QFN
SSOP,
PIC32MX130F256B 28 256+3 16 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y SPDIP,
QFN
VTLA,
PIC32MX130F256D 44 256+3 16 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP,
QFN
SOIC,
SSOP,
PIC32MX170F256B 28 256+3 64 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y
SPDIP,
QFN
VTLA,
PIC32MX170F256D 44 256+3 64 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP,
QFN
Note 1: This device features 3 KB of boot Flash memory.
2: Four out of five timers are remappable.
3: Four out of five external interrupts are remappable.
Timers(2)/Capture/Compare
External Interrupts(3)
DMA Channels
Remappable Pins
Packages
I/O Pins
Device
CTMU
RTCC
JTAG
PMP
Pins
SPI/I2S
I2C
UART
SOIC,
SSOP,
PIC32MX210F016B 28 16+3 4 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y
SPDIP,
QFN
PIC32MX210F016C 36 16+3 4 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 25 Y VTLA
VTLA,
PIC32MX210F016D 44 16+3 4 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP,
QFN
SOIC,
SSOP,
PIC32MX220F032B 28 32+3 8 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y
SPDIP,
QFN
PIC32MX220F032C 36 32+3 8 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA
VTLA,
PIC32MX220F032D 44 32+3 8 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP,
QFN
SOIC,
SSOP,
PIC32MX230F064B 28 64+3 16 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y
SPDIP,
QFN
PIC32MX230F064C 36 64+3 16 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA
VTLA,
PIC32MX230F064D 44 64+3 16 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP,
QFN
SOIC,
SSOP,
PIC32MX250F128B 28 128+3 32 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y
SPDIP,
QFN
PIC32MX250F128C 36 128+3 32 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA
VTLA,
PIC32MX250F128D 44 128+3 32 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP,
QFN
SSOP,
PIC32MX230F256B 28 256+3 16 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y SPDIP,
QFN
VTLA,
PIC32MX230F256D 44 256+3 16 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP,
QFN
SOIC,
SSOP,
PIC32MX270F256B 28 256+3 64 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y
SPDIP,
QFN
VTLA,
PIC32MX270F256D 44 256+3 64 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP,
QFN
Note 1: This device features 3 KB of boot Flash memory.
2: Four out of five timers are remappable.
3: Four out of five external interrupts are remappable.
1 28 1 28 1 28
SSOP SOIC SPDIP
PIC32MX110F016B
PIC32MX120F032B
PIC32MX130F064B
PIC32MX130F256B
PIC32MX150F128B
PIC32MX170F256B
1 MCLR 15 PGEC3/RPB6/PMD6/RB6
2 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 16 TDI/RPB7/CTED3/PMD5/INT0/RB7
3 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 17 TCK/RPB8/SCL1/CTED10/PMD4/RB8
4 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 18 TDO/RPB9/SDA1/CTED4/PMD3/RB9
5 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 19 VSS
6 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 20 VCAP
7 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 21 PGED2/RPB10/CTED11/PMD2/RB10
8 VSS 22 PGEC2/TMS/RPB11/PMD1/RB11
9 OSC1/CLKI/RPA2/RA2 23 AN12/PMD0/RB12
10 OSC2/CLKO/RPA3/PMA0/RA3 24 AN11/RPB13/CTPLS/PMRD/RB13
11 SOSCI/RPB4/RB4 25 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
12 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 26 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
13 VDD 27 AVSS
14 PGED3/RPB5/PMD7/RB5 28 AVDD
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: Shaded pins are 5V tolerant.
1 28 1 28 1 28
SSOP SOIC SPDIP
PIC32MX210F016B
PIC32MX220F032B
PIC32MX230F064B
PIC32MX230F256B
PIC32MX250F128B
PIC32MX270F256B
1 MCLR 15 VBUS
2 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 16 TDI/RPB7/CTED3/PMD5/INT0/RB7
3 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 17 TCK/RPB8/SCL1/CTED10/PMD4/RB8
4 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 18 TDO/RPB9/SDA1/CTED4/PMD3/RB9
5 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 19 VSS
6 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 20 VCAP
7 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 21 PGED2/RPB10/D+/CTED11/RB10
8 VSS 22 PGEC2/RPB11/D-/RB11
9 OSC1/CLKI/RPA2/RA2 23 VUSB3V3
10 OSC2/CLKO/RPA3/PMA0/RA3 24 AN11/RPB13/CTPLS/PMRD/RB13
11 SOSCI/RPB4/RB4 25 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
12 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 26 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
13 VDD 27 AVSS
14 TMS/RPB5/USBID/RB5 28 AVDD
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more informa-
tion.
3: Shaded pins are 5V tolerant.
PIC32MX110F016B
PIC32MX120F032B
PIC32MX130F064B
PIC32MX130F256B
PIC32MX150F128B 28 1
PIC32MX170F256B
1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 15 TDO/RPB9/SDA1/CTED4/PMD3/RB9
2 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 16 VSS
3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 17 VCAP
4 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 18 PGED2/RPB10/CTED11/PMD2/RB10
5 VSS 19 PGEC2/TMS/RPB11/PMD1/RB11
6 OSC1/CLKI/RPA2/RA2 20 AN12/PMD0/RB12
7 OSC2/CLKO/RPA3/PMA0/RA3 21 AN11/RPB13/CTPLS/PMRD/RB13
8 SOSCI/RPB4/RB4 22 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
9 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 23 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
10 VDD 24 AVSS
11 PGED3/RPB5/PMD7/RB5 25 AVDD
12 PGEC3/RPB6/PMD6/RB6 26 MCLR
13 TDI/RPB7/CTED3/PMD5/INT0/RB7 27 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
14 TCK/RPB8/SCL1/CTED10/PMD4/RB8 28 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: Shaded pins are 5V tolerant.
PIC32MX210F016B
PIC32MX220F032B
PIC32MX230F064B
PIC32MX230F256B
PIC32MX250F128B
28 1
PIC32MX270F256B
1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 15 TDO/RPB9/SDA1/CTED4/PMD3/RB9
2 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 16 VSS
3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 17 VCAP
4 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 18 PGED2/RPB10/D+/CTED11/RB10
5 VSS 19 PGEC2/RPB11/D-/RB11
6 OSC1/CLKI/RPA2/RA2 20 VUSB3V3
7 OSC2/CLKO/RPA3/PMA0/RA3 21 AN11/RPB13/CTPLS/PMRD/RB13
8 SOSCI/RPB4/RB4 22 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
9 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 23 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
10 VDD 24 AVSS
11 TMS/RPB5/USBID/RB5 25 AVDD
12 VBUS 26 MCLR
13 TDI/RPB7/CTED3/PMD5/INT0/RB7 27 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0
14 TCK/RPB8/SCL1/CTED10/PMD4/RB8 28 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: Shaded pins are 5V tolerant.
PIC32MX110F016C
PIC32MX120F032C
PIC32MX130F064C
PIC32MX150F128C
1
36
1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 19 TDO/RPB9/SDA1/CTED4/PMD3/RB9
2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 20 RPC9/CTED7/RC9
3 PGED4(4)/AN6/RPC0/RC0 21 VSS
4 PGEC4(4)/AN7/RPC1/RC1 22 VCAP
5 VDD 23 VDD
6 VSS 24 PGED2/RPB10/CTED11/PMD2/RB10
7 OSC1/CLKI/RPA2/RA2 25 PGEC2/TMS/RPB11/PMD1/RB11
8 OSC2/CLKO/RPA3/PMA0/RA3 26 AN12/PMD0/RB12
9 SOSCI/RPB4/RB4 27 AN11/RPB13/CTPLS/PMRD/RB13
10 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 28 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
11 RPC3/RC3 29 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
12 VSS 30 AVSS
13 VDD 31 AVDD
14 VDD 32 MCLR
15 PGED3/RPB5/PMD7/RB5 33 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0
16 PGEC3/RPB6/PMD6/RB6 34 VREF-/CVREF-/AN1/RPA1/CTED2/RA1
17 TDI/RPB7/CTED3/PMD5/INT0/RB7 35 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
18 TCK/RPB8/SCL1/CTED10/PMD4/RB8 36 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: This pin function is not available on PIC32MX110F016C and PIC32MX120F032C devices.
5: Shaded pins are 5V tolerant.
PIC32MX210F016C
PIC32MX220F032C
PIC32MX230F064C
PIC32MX250F128C
1
36
1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 19 TDO/RPB9/SDA1/CTED4/PMD3/RB9
2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 20 RPC9/CTED7/RC9
3 PGED4(4)/AN6/RPC0/RC0 21 VSS
4 PGEC4(4)/AN7/RPC1/RC1 22 VCAP
5 VDD 23 VDD
6 VSS 24 PGED2/RPB10/D+/CTED11/RB10
7 OSC1/CLKI/RPA2/RA2 25 PGEC2/RPB11/D-/RB11
8 OSC2/CLKO/RPA3/PMA0/RA3 26 VUSB3V3
9 SOSCI/RPB4/RB4 27 AN11/RPB13/CTPLS/PMRD/RB13
10 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 28 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
11 AN12/RPC3/RC3 29 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
12 VSS 30 AVSS
13 VDD 31 AVDD
14 VDD 32 MCLR
15 TMS/RPB5/USBID/RB5 33 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0
16 VBUS 34 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1
17 TDI/RPB7/CTED3/PMD5/INT0/RB7 35 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0
18 TCK/RPB8/SCL1/CTED10/PMD4/RB8 36 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: This pin function is not available on PIC32MX210F016C and PIC32MX120F032C devices.
5: Shaded pins are 5V tolerant.
PIC32MX110F016D
PIC32MX120F032D
PIC32MX130F064D
PIC32MX130F256D
PIC32MX150F128D
PIC32MX170F256D
44 1
1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0
4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1
5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2
6 VSS 28 VDD
7 VCAP 29 VSS
8 PGED2/RPB10/CTED11/PMD2/RB10 30 OSC1/CLKI/RPA2/RA2
9 PGEC2/RPB11/PMD1/RB11 31 OSC2/CLKO/RPA3/RA3
10 AN12/PMD0/RB12 32 TDO/RPA8/PMA8/RA8
11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4
12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4
13 PGEC4(4) /TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9
14 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 36 RPC3/RC3
15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4
16 AVSS 38 RPC5/PMA3/RC5
17 AVDD 39 VSS
18 MCLR 40 VDD
19 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 41 PGED3/RPB5/PMD7/RB5
20 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 42 PGEC3/RPB6/PMD6/RB6
21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7
22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices.
5: Shaded pins are 5V tolerant.
PIC32MX210F016D
PIC32MX220F032D
PIC32MX230F064D
PIC32MX230F256D
PIC32MX250F128D
PIC32MX270F256D
44 1
Pin # Full Pin Name Pin # Full Pin Name
1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0
4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1
5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2
6 VSS 28 VDD
7 VCAP 29 VSS
8 PGED2/RPB10/D+/CTED11/RB10 30 OSC1/CLKI/RPA2/RA2
9 PGEC2/RPB11/D-/RB11 31 OSC2/CLKO/RPA3/RA3
10 VUSB3V3 32 TDO/RPA8/PMA8/RA8
11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4
12 PGED4/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4
13 PGEC4/TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9
14 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 36 AN12/RPC3/RC3
15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4
16 AVSS 38 RPC5/PMA3/RC5
17 AVDD 39 VSS
18 MCLR 40 VDD
19 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 41 RPB5/USBID/RB5
20 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 42 VBUS
21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7
22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices.
5: Shaded pins are 5V tolerant.
PIC32MX110F016D
PIC32MX120F032D
PIC32MX130F064D
PIC32MX130F256D
PIC32MX150F128D
PIC32MX170F256D
44
1
Pin # Full Pin Name Pin # Full Pin Name
1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0
4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1
5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2
6 VSS 28 VDD
7 VCAP 29 VSS
8 PGED2/RPB10/CTED11/PMD2/RB10 30 OSC1/CLKI/RPA2/RA2
9 PGEC2/RPB11/PMD1/RB11 31 OSC2/CLKO/RPA3/RA3
10 AN12/PMD0/RB12 32 TDO/RPA8/PMA8/RA8
11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4
12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4
13 PGEC4(4)/TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9
14 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 36 RPC3/RC3
15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4
16 AVSS 38 RPC5/PMA3/RC5
17 AVDD 39 VSS
18 MCLR 40 VDD
19 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 41 PGED3/RPB5/PMD7/RB5
20 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 42 PGEC3/RPB6/PMD6/RB6
21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7
22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices.
5: Shaded pins are 5V tolerant.
PIC32MX210F016D
PIC32MX220F032D
PIC32MX230F064D
PIC32MX230F256D
PIC32MX250F128D
PIC32MX270F256D
44
1
1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0
4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1
5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2
6 VSS 28 VDD
7 VCAP 29 VSS
8 PGED2/RPB10/D+/CTED11/RB10 30 OSC1/CLKI/RPA2/RA2
9 PGEC2/RPB11/D-/RB11 31 OSC2/CLKO/RPA3/RA3
10 VUSB3V3 32 TDO/RPA8/PMA8/RA8
11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4
12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4
13 (4)
PGEC4 /TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9
14 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 36 AN12/RPC3/RC3
15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4
16 AVSS 38 RPC5/PMA3/RC5
17 AVDD 39 VSS
18 MCLR 40 VDD
19 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 41 RPB5/USBID/RB5
20 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 42 VBUS
21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7
22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: This pin function is not available on PIC32MX210F016D and PIC32MX220F032D devices.
5: Shaded pins are 5V tolerant.
PIC32MX110F016D
PIC32MX120F032D
PC32MX130F064D
PIC32MX130F256D
PIC32MX150F128D
PIC32MX170F256D
1
44
1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0
4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1
5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2
6 VSS 28 VDD
7 VCAP 29 VSS
8 PGED2/RPB10/CTED11/PMD2/RB10 30 OSC1/CLKI/RPA2/RA2
9 PGEC2/RPB11/PMD1/RB11 31 OSC2/CLKO/RPA3/RA3
10 AN12/PMD0/RB12 32 TDO/RPA8/PMA8/RA8
11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4
12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4
13 PGEC4(4)/TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9
14 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 36 RPC3/RC3
15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4
16 AVSS 38 RPC5/PMA3/RC5
17 AVDD 39 VSS
18 MCLR 40 VDD
19 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 41 PGED3/RPB5/PMD7/RB5
20 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 42 PGEC3/RPB6/PMD6/RB6
21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7
22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices.
5: Shaded pins are 5V tolerant.
PIC32MX210F016D
PIC32MX220F032D
PIC32MX230F064D
PIC32MX230F256D
PIC32MX250F128D
PIC32MX270F256D
44
1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0
4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1
5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2
6 VSS 28 VDD
7 VCAP 29 VSS
8 PGED2/RPB10/D+/CTED11/RB10 30 OSC1/CLKI/RPA2/RA2
9 PGEC2/RPB11/D-/RB11 31 OSC2/CLKO/RPA3/RA3
10 VUSB3V3 32 TDO/RPA8/PMA8/RA8
11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4
12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4
13 (4)
PGEC4 /TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9
14 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 36 AN12/RPC3/RC3
15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4
16 AVSS 38 RPC5/PMA3/RC5
17 AVDD 39 VSS
18 MCLR 40 VDD
19 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 41 RPB5/USBID/RB5
20 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 42 VBUS
21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7
22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin
Select” for restrictions.
2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information.
3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
4: This pin function is not available on PIC32MX210F016D and PIC32MX220F032D devices.
5: Shaded pins are 5V tolerant.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
PORTB OC1-OC5
DMAC
USB
ICD
EJTAG INT 32
® ® IC1-IC5
MIPS32 M4K
PORTC CPU Core
IS DS
32 32 32
32 SPI1-SPI2
32 32
Remappable
Pins Bus Matrix
32 32 I2C1-I2C2
32
32
Peripheral Bridge
Data RAM
PMP
10-bit ADC
UART1-UART2
Controller
32-bit Wide
Flash
Comparators 1-3
Note: Some features are not available on all devices. Refer to the family features tables (Table 1 and Table 2) for availability.
VSS
VDD
VCAP
AVSS
VDD
VSS
Ceramic
For example, as illustrated in Figure 2-2, it is
Connect(2) recommended that the capacitor C, be isolated from
0.1 µF 0.1 µF
Ceramic Ceramic
the MCLR pin during programming and debugging
operations.
L1(2)
Place the components illustrated in Figure 2-2 within
Note 1: If the USB module is not used, this pin must be one-quarter inch (6 mm) from the MCLR pin.
connected to VDD.
2: As an option, instead of a hard-wired connection, an FIGURE 2-2: EXAMPLE OF MCLR PIN
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
CONNECTIONS
impedance should be less than 3 and the inductor VDD
capacity greater than 10 mA.
Where: R 10k
R1(1)
MCLR
F CNV 1 k
f = -------------- (i.e., ADC conversion rate/2) 0.1 µF(2) C
2
PIC32
1
f = ----------------------- 1
2 LC 5
PGECx(3)
4
ICSP™
1 - 2 PGEDx(3)
L = ---------------------
2
VDD
2f C 3
VSS
6
NC
1: Aluminum or electrolytic capacitors should not be
used. ESR 3 from -40ºC to 125ºC @ SYSCLK
Note 1: 470 R1 1 will limit any current flowing into
frequency (i.e., MIPS).
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
2.2.1 BULK CAPACITORS (ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
The use of a bulk capacitor is recommended to improve interfering with the Debug/Programmer tools.
power supply stability. Typical values range from 4.7 µF 2: The capacitor can be sized to prevent unintentional
to 47 µF. This capacitor should be located as close to Resets from brief glitches or to extend the device
the device as possible. Reset period during POR.
3: No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
2.3 Capacitor on Internal Voltage
Regulator (VCAP)
2.5 ICSP Pins
2.3.1 INTERNAL REGULATOR MODE
The PGECx and PGEDx pins are used for ICSP and
A low-ESR (3 ohm) capacitor is required on the VCAP debugging purposes. It is recommended to keep the
pin, which is used to stabilize the internal voltage trace length between the ICSP connector and the ICSP
regulator output. The VCAP pin must not be connected
pins on the device as short as possible. If the ICSP con-
to VDD, and must have a CEFC capacitor, with at least a
nector is expected to experience an ESD event, a
6V rating, connected to ground. The type can be
series resistor is recommended, with the value in the
ceramic or tantalum. Refer to 30.0 “Electrical
Characteristics” for additional information on CEFC range of a few tens of Ohms, not to exceed 100 Ohms.
specifications.
C2
C1
loading capacitance
1M
• Estimated PCB stray capacitance, (i.e.,12 mm
length) = 2.5 pF
OSC2 OSC1
EXAMPLE 2-1: CRYSTAL LOAD CAPACITOR
CALCULATION Circuit B
Crystal manufacturer recommended: C1 = C2 = 15 pF
Typical HS
(10-25 MHz)
Therefore:
CLOAD = {( [CIN + C1] * [COUT + C2] ) / [CIN + C1 + C2 + COUT] }
+ estimated oscillator PCB stray capacitance
C1
C2
= {( [5 + 15][5 + 15] ) / [5 + 15 + 15 + 5] } + 2.5 pF
= {( [20][20]) / [40] } + 2.5
= 10 + 2.5 = 12.5 pF
Rounded to the nearest standard value or 12 pF in this example for OSC2 OSC1
Primary Oscillator crystals “C1” and “C2”.
Circuit C
The following tips are used to increase oscillator gain,
(i.e., to increase peak-to-peak oscillator signal): Typical XT/HS
(4-25 MHz)
• Select a crystal with a lower “minimum” power drive
rating
• Select an crystal oscillator with a lower XTAL
C1
C2
Rs
manufacturing “ESR” rating.
• Add a parallel resistor across the crystal. The smaller
1M
the resistor value the greater the gain. It is recom-
mended to stay in the range of 600k to 1M
OSC2 OSC1
• C1 and C2 values also affect the gain of the oscillator.
The lower the values, the higher the gain.
• C2/C1 ratio also affects gain. To increase the gain, Circuit D
make C1 slightly smaller than C2, which will also help Not Recommended
start-up performance.
Note: Do not add excessive gain such that the
oscillator signal is clipped, flat on top of
the sine wave. If so, you need to reduce
the gain or add a series resistor, RS, as 1M
shown in circuit “C” in Figure 2-4. Failure Rs
to do so will stress and age the crystal,
which can result in an early failure. Adjust
the gain to trim the max peak-to-peak to OSC2 OSC1
~VDD-0.6V. When measuring the oscilla-
tor signal you must use a FET scope Circuit E
probe or a probe with 1.5 pF or the
Not Recommended
scope probe itself will unduly change the
gain and peak-to-peak levels.
PIC32MX120F032D
Current Source
To AN6 To AN7 To AN8 To AN9 To AN11
To AN0
CTMU
AN0 R1 R1 R1 R1 R1
C1 C2 C3 C4 C5
AN1 To AN1
ADC
R2 R2 R2 R2 R2
Read the Touch Sensors C1 C2 C3 C4 C5
Microchip
mTouch™
Library AN9
Display Data
LCD Controller
PMPD<7:0>
Microchip Parallel Display
Frame LCD
Graphics Master PMPWR Controller
Buffer Panel
Library Port
PMPD<7:0>
USB
USB PMP
Host Display
PMPWR
PIC32MX220F032D
3 Stereo Headphones
I2S
Audio
Codec
3
SPI Speaker
3
MMC SD
SDI
Analog/Digital Switch
Capacitive Coupling
Inductive Coupling
Optional Coupling
0.1 μF 0.1 μF
VDD
VSS
VDD
VSS
VSS
VSS VDD
VDD
VSS 0.1 μF
0.1 μF
PIC32 VDD
VSS 0.1 μF
VSS
VDD VUSB3V3
0.1 μF
AVDD
AVSS
VDD
VSS
0.1 μF
CPU
EJTAG
MDU
Execution Core
FMT Bus Interface Dual Bus Interface Bus Matrix
(RF/ALU/Shift)
System Power
Co-processor Management
Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1
0xBF800000
Reserved
0xBD004000
0xBD003FFF
Program Flash(2)
0xBD000000
Reserved
0xA0001000
0xA0000FFF
RAM(2)
0xA0000000 0x1FC00C00
Device 0x1FC00BFF
Reserved
0x9FC00C00 Configuration
0x9FC00BFF Device Registers 0x1FC00BF0
Configuration 0x1FC00BEF
Registers
0x9FC00BF0 Boot Flash
0x9FC00BEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0
0x9D004000 0x1F800000
0x9D003FFF
Program Flash(2) Reserved
0x9D000000 0x1D004000
0x1D003FFF
Reserved
0x80001000 Program Flash(2)
0x80000FFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00001000
0x00000FFF
Reserved RAM(2)
0x00000000 0x00000000
Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1
0xBF800000
Reserved
0xBD008000
0xBD007FFF
Program Flash(2)
0xBD000000
Reserved
0xA0002000
0xA0001FFF
RAM(2)
0xA0000000 0x1FC00C00
Device 0x1FC00BFF
Reserved
0x9FC00C00 Configuration
0x9FC00BFF Device Registers 0x1FC00BF0
Configuration 0x1FC00BEF
0x9FC00BF0 Registers Boot Flash
0x9FC00BEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
0x9D008000 0x1F800000
KSEG0
0x9D007FFF
Program Flash(2) Reserved
0x9D000000 0x1D008000
0x1D007FFF
Reserved
0x80002000 Program Flash(2)
0x80001FFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00002000
0x00001FFF
Reserved RAM(2)
0x00000000 0x00000000
Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1
0xBF800000
Reserved
0xBD010000
0xBD00FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0004000
0xA0003FFF
RAM(2)
0xA0000000 0x1FC00C00
Device 0x1FC00BFF
Reserved
0x9FC00C00 Configuration
0x9FC00BFF Device Registers 0x1FC00BF0
Configuration 0x1FC00BEF
Registers
0x9FC00BF0 Boot Flash
0x9FC00BEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0
0x9D010000 0x1F800000
0x9D00FFFF
Program Flash(2) Reserved
0x9D000000 0x1D010000
0x1D00FFFF
Reserved
0x80004000 Program Flash(2)
0x80003FFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00004000
0x00003FFF
Reserved RAM(2)
0x00000000 0x00000000
Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1
0xBF800000
Reserved
0xBD020000
0xBD01FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0008000
0xA0007FFF
RAM(2)
0xA0000000 0x1FC00C00
Device 0x1FC00BFF
Reserved
0x9FC00C00 Configuration
0x9FC00BFF Device Registers 0x1FC00BF0
Configuration 0x1FC00BEF
0x9FC00BF0 Registers Boot Flash
0x9FC00BEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0
0x9D020000 0x1F800000
0x9D01FFFF
Program Flash(2) Reserved
0x9D000000 0x1D020000
0x1D01FFFF
Reserved
0x80008000 Program Flash(2)
0x80007FFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00008000
0x00007FFF
Reserved RAM(2)
0x00000000 0x00000000
Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1
0xBF800000
Reserved
0xBD040000
0xBD03FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0010000
0xA000FFFF
RAM(2)
0xA0000000 0x1FC00C00
Device 0x1FC00BFF
Reserved
0x9FC00C00 Configuration
0x9FC00BFF Device Registers 0x1FC00BF0
Configuration 0x1FC00BEF
Registers
0x9FC00BF0 Boot Flash
0x9FC00BEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0
0x9D040000 0x1F800000
0x9D03FFFF
Program Flash(2) Reserved
0x9D000000 0x1D040000
0x1D03FFFF
Reserved
0x80010000 Program Flash(2)
0x8000FFFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00010000
0x0000FFFF
Reserved RAM(2)
0x00000000 0x00000000
Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1
0xBF800000
Reserved
0xBD040000
0xBD03FFFF
Program Flash(2)
0xBD000000
Reserved
0xA0004000
0xA0003FFF
RAM(2)
0xA0000000 0x1FC00C00
Device 0x1FC00BFF
Reserved
0x9FC00C00 Configuration
0x9FC00BFF Device Registers 0x1FC00BF0
Configuration 0x1FC00BEF
0x9FC00BF0 Registers Boot Flash
0x9FC00BEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0
0x9D040000 0x1F800000
0x9D03FFFF
Program Flash(2) Reserved
0x9D000000 0x1D040000
0x1D03FFFF
Reserved
0x80004000 Program Flash(2)
0x80003FFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00004000
0x00003FFF
Reserved RAM(2)
0x00000000 0x00000000
Bits
Bit Range
(BF88_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 4-6: BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS
REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
— — — — BMXPUPBA<19:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
15:8
BMXPUPBA<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
BMXPUPBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXPFMSZ.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
F400 NVMCON(1)
15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — NVMOP<3:0> 0000
31:16 0000
F410 NVMKEY NVMKEY<31:0>
15:0 0000
31:16 0000
F420 NVMADDR(1) NVMADDR<31:0>
15:0 0000
31:16 0000
F430 NVMDATA NVMDATA<31:0>
15:0 0000
31:16 0000
F440 NVMSRCADDR NVMSRCADDR<31:0>
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R-0 R-0 R-0 U-0 U-0 U-0
15:8
WR WREN WRERR(1) LVDERR(1) LVDSTAT(1) — — —
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — — NVMOP<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is cleared by setting NVMOP == ‘b0000, and initiating a Flash operation (i.e., WR).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: The bits in this register are only reset by a Power-on Reset (POR).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
MCLR
MCLR
Glitch Filter
Brown-out BOR
Reset
Configuration
Mismatch
Reset CMR
SWR
Software Reset
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
F600 RCON
15:0 — — — — — — CMR VREGS EXTR SWR — WDTO SLEEP IDLE BOR POR xxxx(2)
31:16 — — — — — — — — — — — — — — — — 0000
F610 RSWRST
15:0 — — — — — — — — — — — — — — — SWRST 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 6-1: RCON: RESET CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0
15:8
— — — — — — CMR VREGS
R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS
7:0 (1) (1)
EXTR SWR — WDTO SLEEP IDLE BOR POR
Note 1: User software must clear this bit to view next detection.
Note 1: The system unlock sequence must be performed before the SWRST bit is written. Refer to Section 6.
“Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.
Vector Number
Priority Level
Bit Range
(BF88_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
1000 INTCON
15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT(3)
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
31:16 0000
1020 IPTMR IPTMR<31:0>
15:0 0000
31:16 FCEIF RTCCIF FSCMIF AD1IF OC5IF IC5IF IC5EIF T5IF INT4IF OC4IF IC4IF IC4EIF T4IF INT3IF OC3IF IC3IF 0000
1030 IFS0
15:0 IC3EIF T3IF INT2IF OC2IF IC2IF IC2EIF T2IF INT1IF OC1IF IC1IF IC1EIF T1IF INT0IF CS1IF CS0IF CTIF 0000
31:16 DMA3IF DMA2IF DMA1IF DMA0IF CTMUIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF 0000
1040 IFS1
15:0 CNCIF CNBIF CNAIF I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF USBIF(2) CMP3IF CMP2IF CMP1IF 0000
31:16 FCEIE RTCCIE FSCMIE AD1IE OC5IE IC5IE IC5EIE T5IE INT4IE OC4IE IC4IE IC4EIE T4IE INT3IE OC3IE IC3IE 0000
1060 IEC0
15:0 IC3EIE T3IE INT2IE OC2IE IC2IE IC2EIE T2IE INT1IE OC1IE IC1IE IC1EIE T1IE INT0IE CS1IE CS0IE CTIE 0000
31:16 DMA3IE DMA2IE DMA1IE DMA0IE CTMUIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE 0000
1070 IEC1
15:0 CNCIE CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE USBIE(2) CMP3IE CMP2IE CMP1IE 0000
31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
1090 IPC0
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000
10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
2011-2019 Microchip Technology Inc.
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000
10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
31:16 — — — CMP1IP<2:0> CMP1IS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
10F0 IPC6
15:0 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR,
SET and INV Registers” for more information.
2: These bits are not available on PIC32MX1XX devices.
3: This register does not have associated CLR, SET, INV registers.
TABLE 7-2: INTERRUPT REGISTER MAP (CONTINUED)
2011-2019 Microchip Technology Inc.
Bit Range
(BF88_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit
definitions.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit
definitions.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
USB PLL(4)
USB Clock (48 MHz)
UFIN
div x PLL x24 div 2
UFRCEN
UFIN 4 MHz
UPLLEN
UPLLIDIV<2:0>
ROTRIM<8:0>
REFCLKI (M) OE
POSC
FRC
LPRC REFCLKO
System PLL SOSC 2 N + ---------
M
512
-
PBCLK
4 MHz FIN 5 MHz
SYSCLK
FIN
div x PLL To SPI
RODIV<14:0>
(N)
FPLLIDIV<2:0> ROSEL<3:0>
COSC<2:0> PLLMULT<2:0>
div y
XTPLL, HSPLL,
ECPLL, FRCPLL
PLLODIV<2:0>
Primary Oscillator (POSC)
C1(2) OSC1
Postscaler Peripherals
To Internal POSC (XT, HS, EC)
div x PBCLK (TPB)
XTAL Logic
RP(1) 3x 1x
HS XT FRC
PBDIV<1:0>
C2(2) RS(1) OSC2(3) div 16
div 2 FRC/16
To ADC
CPU and Select Peripherals
FRC
Oscillator Postscaler SYSCLK
8 MHz typical FRCDIV
TUN<5:0> FRCDIV<2:0>
Secondary Oscillator (SOSC)
SOSCO 32.768 kHz
SOSC
SOSCEN and FSOSCEN
LPRC
SOSCI Oscillator 31.25 kHz typical LPRC
NOSC<2:0>
COSC<2:0>
FSCMEN<1:0> OSWEN
WDT, PWRT
Timer1, RTCC
Notes: 1. A series resistor, RS, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain,
add a parallel resistor, RP, with a value of 1 M
2. Refer to Section 6. “Oscillator Configuration” (DS60001112) in the “PIC32 Family Reference Manual” for help in determining the
best oscillator components.
3. The PBCLK out is only available on the OSC2 pin in certain clock modes.
4. The USB PLL is only available on PIC32MX2XX devices.
TABLE 8-1:
Virtual Address OSCILLATOR CONTROL REGISTER MAP
Bits
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized, nor tested.
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may
result.
2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.
3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ’1’.
Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may
result.
2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.
3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ’1’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: While the ON (REFOCON<15>) bit is ‘1’, writes to this register do not take effect until the DIVSWEN bit is
also set to ‘1’.
Address SE
Channel 0
Peripheral Bus
Decoder Control I0 L
I2
Channel Priority
Arbitration
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3000 DMACON
15:0 ON — — SUSPEND DMABUSY — — — — — — — — — — — 0000
31:16 — — — — — — — — — — — — — — — — 0000
3010 DMASTAT
15:0 — — — — — — — — — — — — RDWR DMACH<2:0>(2) 0000
31:16 0000
3020 DMAADDR DMAADDR<31:0>
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more
information.
Bits
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
TABLE 9-3: DMA CHANNELS 0-3 REGISTER MAP
2011-2019 Microchip Technology Inc.
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3060 DCH0CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
3070 DCH0ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — —
0000
3150 DCH1SSA CHSSA<31:0>
15:0 0000
31:16 0000
3160 DCH1DSA CHDSA<31:0>
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
DS60001168L-page 90
TABLE 9-3: DMA CHANNELS 0-3 REGISTER MAP (CONTINUED)
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3170 DCH1SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3180 DCH1DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3190 DCH1SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31A0 DCH1DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31B0 DCH1CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31C0 DCH1CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31D0 DCH1DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31E0 DCH2CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
31F0 DCH2ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
3200 DCH2INT
15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
3210 DCH2SSA CHSSA<31:0>
15:0 0000
31:16 0000
3220 DCH2DSA CHDSA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
2011-2019 Microchip Technology Inc.
3230 DCH2SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3240 DCH2DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3250 DCH2SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3260 DCH2DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3270 DCH2CSIZ
15:0 CHCSIZ<15:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
TABLE 9-3: DMA CHANNELS 0-3 REGISTER MAP (CONTINUED)
2011-2019 Microchip Technology Inc.
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3280 DCH2CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3290 DCH2DAT
more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 9-1: DMACON: DMA CONTROLLER CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0
15:8 (1)
ON — — SUSPEND DMABUSY — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
Note 1: See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 9-11: DCHxDSA: DMA CHANNEL ‘x’ DESTINATION START ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
CHDSA<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CHDSA<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CHDSA<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CHDSA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: When in Pattern Detect mode, this register is reset on a pattern detect.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: When in Pattern Detect mode, this register is reset on a pattern detect.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
FRC
Oscillator
8 MHz Typical
TUN<5:0>(3)
Primary Oscillator
(POSC) UFIN(4)
Div x PLL Div 2
OSC1 UFRCEN(2)
UPLLIDIV (5) UPLLEN(5)
OSC2
USB Module
USB
SRP Charge Voltage
Bus Comparators
SRP Discharge
D+(1)
Registers
and
Control
Host Pull-down Interface
SIE
Transceiver
Low Speed Pull-up
D-(1)
DMA System
RAM
Host Pull-down
ID Pull-up
ID(1)
VBUSON(1)
Note 1: Pins can be used as digital input/output when USB is not enabled.
2: This bit field is contained in the OSCCON register.
3: This bit field is contained in the OSCTRM register.
4: USB PLL UFIN requirements: 4 MHz.
5: This bit field is contained in the DEVCFG2 register.
6: A 48 MHz clock is required for proper USB operation.
TABLE 10-1:
Virtual Address USB REGISTER MAP
Bits
All Resets
Bit Range
(BF88_#)
Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
5040 U1OTGIR(2)
15:0 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
5280 U1FRML(3)
15:0 — — — — — — — — FRML<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5290 U1FRMH(3)
15:0 — — — — — — — — — — — — — FRMH<2:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52A0 U1TOK
15:0 — — — — — — — — PID<3:0> EP<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52B0 U1SOF
15:0 — — — — — — — — CNT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52C0 U1BDTP2
15:0 — — — — — — — — BDTPTRH<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52D0 U1BDTP3
15:0 — — — — — — — — BDTPTRU<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52E0 U1CNFG1
15:0 — — — — — — — — UTEYE UOEMON — USBSIDL — — — UASUSPND 0001
31:16 — — — — — — — — — — — — — — — — 0000
5300 U1EP0
15:0 — — — — — — — — LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5310 U1EP1
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5320 U1EP2
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5330 U1EP3
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5340 U1EP4
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
2011-2019 Microchip Technology Inc.
5350 U1EP5
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5360 U1EP6
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5370 U1EP7
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5380 U1EP8
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8, and 0xC respectively.
See Section 11.2 “CLR, SET and INV Registers” for more information.
2: This register does not have associated SET and INV registers.
3: This register does not have associated CLR, SET and INV registers.
4: Reset value for this bit is undefined.
TABLE 10-1: USB REGISTER MAP (CONTINUED)
2011-2019 Microchip Technology Inc.
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
5390 U1EP9
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
53A0 U1EP10
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all USB
module registers produce undefined results.
Note 1: This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for
2.5 µs, and the current bus state is not SE0.
2: When not in Suspend mode, this interrupt should be disabled.
3: Clearing this bit will cause the STAT FIFO to advance.
4: Only error conditions enabled through the U1EIE register will set this bit.
5: Device mode.
6: Host mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: For an interrupt to propagate USBIF, the UERRIE (U1IE<1>) bit must be set.
2: Device mode.
3: Host mode.
7:0 CRC5EF(4)
BTSEF BMXEF DMAEF(1) BTOEF(2) DFN8EF CRC16EF PIDEF
EOFEF(3,5)
Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
4: Device mode.
5: Host mode.
Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
4: Device mode.
5: Host mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: For an interrupt to propagate the USBIF register, the UERRIE (U1IE<1>) bit must be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only
valid when the TRNIF (U1IR<3>) bit is active. Clearing the TRNIF bit advances the FIFO. Data in register
is invalid when the TRNIF bit = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 10-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then
clear it to enable remote wake-up. In Host mode, the USB module will append a Low-Speed EOP to the
RESUME signaling when this bit is cleared.
4: Device mode.
5: Host mode.
Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 10-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then
clear it to enable remote wake-up. In Host mode, the USB module will append a Low-Speed EOP to the
RESUME signaling when this bit is cleared.
4: Device mode.
5: Host mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: All other values are reserved and must not be used.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Data Bus D Q
SYSCLK CK ODC
EN Q
WR ODC
1 I/O Cell
RD TRIS 0
0
1
D Q
TRIS 1
CK
EN Q 0
WR TRIS
Output Multiplexers
D Q
CK LAT I/O Pin
EN Q
WR LAT
WR PORT
RD LAT
1
RD PORT
Q D Q D
0
Sleep Q CK Q CK
PBCLK
Synchronization
Peripheral Input R
Peripheral Input Buffer
Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
Note: This block diagram is a general representation of a shared port/peripheral structure and is only provided for illustration purposes. The
actual structure for any specific port/peripheral combination may be different than it is shown here.
14
15
TABLE 11-3:
Virtual Address PORTA REGISTER MAP
Bits
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6000 ANSELA
15:0 — — — — — — — — — — — — — — ANSA1 ANSA0 0003
All Resets
Bit Range
(BF88_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6100 ANSELB
15:0 ANSB15 ANSB14 ANSB13 ANSB12(2) — — — — — — — — ANSB3 ANSB2 ANSB1 ANSB0 E00F
31:16 — — — — — — — — — — — — — — — — 0000
6110 TRISB
15:0 TRISB15 TRISB14 TRISB13 TRISB12(2) TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6(2) TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
31:16 — — — — — — — — — — — 0000
6120 PORTB
15:0 RB15 RB14 RB13 RB12(2) RB11 RB10 RB9 RB8 RB7 RC6(2) RB5 RB4 RB3 RB2 RB1 RB0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6130 LATB
15:0 LATB15 LATB14 LATB13 LATB12(2) LATB11 LATB10 LATB9 LATB8 LATB7 LATB6(2) LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6140 ODCB
15:0 ODCB15 ODCB14 ODCB13 ODCB12(2) ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
31:16 — — — — — — — — — — — — — — — — 0000
6150 CNPUB
15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12(2) CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6(2) CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
31:16 — — — — — — — — — — — — — — — — 0000
6160 CNPDB
15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12(2) CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6(2) CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
31:16 — — — — — — — — — — — — — — — — 0000
6170 CNCONB
15:0 ON — SIDL — — — — — — — — — — — — — 0000
31:16 — — — — — — — — — — — — — — — — 0000
6180 CNENB
15:0 CNIEB15 CNIEB14 CNIEB13 CNIEB11(2) CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6(2) CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
31:16 — — — — — — — — — — — — — — — — 0000
6190 CNSTATB CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN
15:0 0000
STATB15 STATB14 STATB13 STATB12(2) STATB11 STATB10 STATB9 STATB8 STATB7 STATB6(2) STATB5 STATB4 STATB3 STATB2 STATB1 STATB0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2: This bit is not available on PIC32MX2XX devices. The reset value for the TRISB register when this bit is not available is 0x0000EFBF.
2011-2019 Microchip Technology Inc.
TABLE 11-5: PORTC REGISTER MAP
2011-2019 Microchip Technology Inc.
All Resets
Bit Range
Name(1,2)
(BF88_#)
Register 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6200 ANSELC
15:0 — — — — — — — — — — — — ANSC3(4) ANSC2(3) ANSC1 ANSC0 000F
31:16 — — — — — — — — — — — — — — — — 0000
6210 TRISC
Virtual Address
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
FA04 INT1R
15:0 — — — — — — — — — — — — INT1R<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA08 INT2R
15:0 — — — — — — — — — — — — INT2R<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA0C INT3R
15:0 — — — — — — — — — — — — INT3R<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA10 INT4R
15:0 — — — — — — — — — — — — INT4R<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA18 T2CKR
15:0 — — — — — — — — — — — — T2CKR<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA1C T3CKR
15:0 — — — — — — — — — — — — T3CKR<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA20 T4CKR
15:0 — — — — — — — — — — — — T4CKR<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA24 T5CKR
15:0 — — — — — — — — — — — — T5CKR<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA28 IC1R
15:0 — — — — — — — — — — — — IC1R<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA2C IC2R
15:0 — — — — — — — — — — — — IC2R<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FA30 IC3R
2011-2019 Microchip Technology Inc.
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
FA54 U1CTSR
15:0 — — — — — — — — — — — — U1CTSR<3:0> 0000
31:16 — — — — — — — — — — — — — — — —
Virtual Address
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
FB00 RPA0R
15:0 — — — — — — — — — — — — RPA0<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB04 RPA1R
15:0 — — — — — — — — — — — — RPA1<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB08 RPA2R
15:0 — — — — — — — — — — — — RPA2<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB0C RPA3R
15:0 — — — — — — — — — — — — RPA3<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB10 RPA4R
15:0 — — — — — — — — — — — — RPA4<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB20 RPA8R(1)
15:0 — — — — — — — — — — — — RPA8<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB24 RPA9R(1)
15:0 — — — — — — — — — — — — RPA9<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB2C RPB0R
15:0 — — — — — — — — — — — — RPB0<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB30 RPB1R
15:0 — — — — — — — — — — — — RPB1<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB34 RPB2R
15:0 — — — — — — — — — — — — RPB2<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB38 RPB3R
15:0 — — — — — — — — — — — — RPB3<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
2011-2019 Microchip Technology Inc.
FB3C RPB4R
15:0 — — — — — — — — — — — — RPB4<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB40 RPB5R
15:0 — — — — — — — — — — — — RPB5<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB44 RPB6R(2)
15:0 — — — — — — — — — — — — RPB6<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB48 RPB7R
15:0 — — — — — — — — — — — — RPB7<3:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register is only available on 44-pin devices.
2: This register is only available on PIC32MX1XX devices.
3: This register is only available on 36-pin and 44-pin devices.
TABLE 11-7: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
2011-2019 Microchip Technology Inc.
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
FB4C RPB8R
15:0 — — — — — — — — — — — — RPB8<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB88 RPC7R(1)
15:0 — — — — — — — — — — — — RPC7<3:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register is only available on 44-pin devices.
2: This register is only available on PIC32MX1XX devices.
3: This register is only available on 36-pin and 44-pin devices.
DS60001168L-page 144
TABLE 11-7: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
Virtual Address
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
FB8C RPC8R(1)
15:0 — — — — — — — — — — — — RPC8<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
FB90 RPC9R(3)
15:0 — — — — — — — — — — — — RPC9<3:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register is only available on 44-pin devices.
2: This register is only available on PIC32MX1XX devices.
3: This register is only available on 36-pin and 44-pin devices.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 11-1: [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — — [pin name]R<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Register values can only be changed if the Configuration bit, IOLOCK (CFGCON<13>), = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Register values can only be changed if the Configuration bit, IOLOCK (CFGCON<13>), = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Data Bus<31:0>
1 Sync
Reset
TMR1
0
16-bit Comparator
Equal
PR1
0
T1IF
Event Flag 1 Q D TGATE
Q
TCS
TGATE
ON
SOSCO/T1CK x1
Gate Prescaler
SOSCEN
Sync 10 1, 8, 64, 256
SOSCI
PBCLK 00
2
TCKPS<1:0>
Note: The default state of the SOSCEN (OSCCON<1>) bit during a device Reset is controlled by the
FSOSCEN bit in Configuration Word, DEVCFG1.
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
0600 T1CON
15:0 ON — SIDL TWDIS TWIP — — — TGATE — TCKPS<1:0> — TSYNC TCS — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0610 TMR1
15:0 TMR1<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0620 PR1
15:0 PR1<15:0> FFFF
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 12-1: T1CON: TYPE A TIMER CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0
15:8
ON(1) — SIDL TWDIS TWIP — — —
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
7:0
TGATE — TCKPS<1:0> — TSYNC TCS —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Note 1: When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
<15:0> <15:0>
Reset
TMRx Sync
ADC Event
Trigger(1) Comparator x 16
Equal
PRx
0
TxIF
Event Flag 1 Q D TGATE
Q TCS
TGATE
ON
TxCK x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256
PBCLK 00
3
Note 1: ADC event trigger is available on Timer3 only. TCKPS
Data Bus<31:0>
<31:0>
Reset
TMRy(1) TMRx(1) Sync
PRy PRx
TyIF Event 0
Flag
1 Q D TGATE
Q TCS
TGATE
ON
TxCK x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256
PBCLK 00
3
TCKPS
Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the
use of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: ADC event trigger is available only on the Timer2/3 pair.
TABLE 13-1:
Virtual Address TIMER2-TIMER5 REGISTER MAP
Bits
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
0800 T2CON
15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> T32 — TCS — 0000
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is available only on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3, and Timer5). All
timer functions are set through the even numbered timers.
4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is available only on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3, and Timer5). All
timer functions are set through the even numbered timers.
4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
Clock
25-bit Counter
WDTCLR = 1
WDT Enable 25
Wake 0 Device Reset
WDT Counter Reset
WDT Enable 1 NMI (Wake-up)
Reset Event
Power Save
Decoder
FWDTPS<4:0> (DEVCFG1<20:16>)
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
0000 WDTCON
15:0 ON — — — — — — — — SWDTPS<4:0> WDTWINEN WDTCLR 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 14-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8 (1,2)
ON — — — — — — —
U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0
7:0
— SWDTPS<4:0> WDTWINEN WDTCLR
Note 1: A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.
2: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
FEDGE ICM<2:0>
Specified/Every
Edge Mode 110
C32 || ICTMR
Prescaler Mode 100
(4th Rising Edge)
ICxBUF
ICI<1:0>
ICM<2:0>
Edge Detection 001
Mode
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
2000 IC1CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2010 IC1BUF IC1BUF<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
2200 IC2CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2210 IC2BUF IC2BUF<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
2400 IC3CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2410 IC3BUF IC3BUF<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
2600 IC4CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2610 IC4BUF IC4BUF<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
2800 IC5CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2810 IC5BUF IC5BUF<31:0>
15:0 xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 15-1: ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8 (1)
ON — SIDL — — — FEDGE C32
R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0
7:0
ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown) P = Programmable bit r = Reserved bit
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
OCxRS(1)
Output S Q
OCxR(1) OCx(1)
Logic R
0 1 OCTSEL 0 1
16 16
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
3000 OC1CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3010 OC1R OC1R<31:0>
15:0 xxxx
31:16 xxxx
3020 OC1RS OC1RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3200 OC2CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3210 OC2R OC2R<31:0>
15:0 xxxx
31:16 xxxx
3220 OC2RS OC2RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3400 OC3CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3410 OC3R OC3R<31:0>
15:0 xxxx
31:16 xxxx
3420 OC3RS OC3RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3600 OC4CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3610 OC4R OC4R<31:0>
15:0 xxxx
31:16 xxxx
3620 OC4RS OC4RS<31:0>
2011-2019 Microchip Technology Inc.
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3800 OC5CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3810 OC5R OC5R<31:0>
15:0 xxxx
31:16 xxxx
3820 OC5RS OC5RS<31:0>
15:0 xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 16-1: OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
15:8 (1)
ON — SIDL — — — — —
U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — OC32 OCFLT(2) OCTSEL OCM<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is only used when OCM<2:0> = ‘111’. It is read as ‘0’ in all other modes.
SPIxBUF
Read Write
FIFOs Share Address SPIxBUF
Transmit
Receive
SPIxSR
SDIx bit 0
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF 0000
5800 SPI1CON
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000
31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000
5810 SPI1STAT
15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
31:16 0000
5820 SPI1BUF DATA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5830 SPI1BRG
15:0 — — — BRG<12:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5840 SPI1CON2 SPI FRM SPI SPI AUD
15:0 — — IGNROV IGNTUR AUDEN — — — — AUDMOD<1:0> 0000
SGNEXT ERREN ROVEN TUREN MONO
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF 0000
5A00 SPI2CON
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000
31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000
5A10 SPI2STAT
15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
31:16 0000
5A20 SPI2BUF DATA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5A30 SPI2BRG
15:0 — — — BRG<12:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5A40 SPI2CON2 SPI FRM SPI SPI AUD
15:0 — — IGNROV IGNTUR AUDEN — — — — AUDMOD<1:0> 0000
SGNEXT ERREN ROVEN TUREN MONO
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV
2011-2019 Microchip Technology Inc.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value
of CKP.
When AUDEN = 0:
MODE32 MODE16 Communication
1 x 32-bit
0 1 16-bit
0 0 8-bit
bit 9 SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
To write a '1' to this bit, the MSTEN value = 1 must first be written.
bit 8 CKE: SPI Clock Edge Select bit(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see the CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see the CKP bit)
bit 7 SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode, pin controlled by port function.
bit 6 CKP: Clock Polarity Select bit(4)
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value
of CKP.
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value
of CKP.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx Clock
I2CxRSR
LSB
I2CxMSK
Write Read
I2CxADD
Read
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSB
Shift Clock Read
Reload
Control
Write
Read
PBCLK
TABLE 18-1:
Virtual Address I2C1 AND I2C2 REGISTER MAP
Bits
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
5000 I2C1CON
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV
Registers” for more information.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 18-1: I2CXCON: I2C CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
15:8 (1)
ON — SIDL SCLREL STRICT A10M DISSLW SMEN
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
7:0
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
IrDA®
UxRTS/BCLKx
Hardware Flow Control
UxCTS
Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
6000 U1MODE(1)
15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6010 U1STA(1)
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
31:16 — — — — — — — — — — — — — — — — 0000
6020 U1TXREG
15:0 — — — — — — — Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6030 U1RXREG
15:0 — — — — — — — Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6040 U1BRG(1)
15:0 Baud Rate Generator Prescaler 0000
31:16 — — — — — — — — — — — — — — — — 0000
6200 U2MODE(1)
15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6210 U2STA(1)
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
31:16 — — — — — — — — — — — — — — — — 0000
6220 U2TXREG
15:0 — — — — — — — Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6230 U2RXREG
15:0 — — — — — — — Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6240 U2BRG(1)
15:0 Baud Rate Generator Prescaler 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 19-1: UxMODE: UARTx MODE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
15:8 (1)
ON — SIDL IREN RTSMD — UEN<1:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Read to
UxRXREG
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
Write to
UxTXREG
TSR
BCLK/16 Pull from Buffer
(Shift Clock)
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10
Address Bus
Data Bus
Control Lines
PIC32MX1XX/2XX
Parallel PMA<0>
Master Port PMALL
PMA<1>
PMALH Up to 12-bit Address Flash
EEPROM
PMA<10:2>
SRAM
PMA<14>
PMCS1
PMRD
PMRD/PMWR
FIFO
PMWR Microcontroller LCD
PMENB Buffer
PMD<7:0>
8-bit Data (with or without multiplexed addressing)
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
7000 PMCON
15:0 ON — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP — CS1P — WRSP RDSP 0000
31:16 — — — — — — — — — — — — — — — — 0000
7010 PMMODE
15:0 BUSY IRQM<1:0> INCM<1:0> — MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
7020 PMADDR CS1 0000
15:0 — — — — ADDR<10:0>
ADDR14
31:16 0000
7030 PMDOUT DATAOUT<31:0>
15:0 0000
31:16 0000
7040 PMDIN DATAIN<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
7050 PMAEN
15:0 — PTEN14 — — — PTEN<10:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
7060 PMSTAT
15:0 IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8 (1)
ON — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
7:0
CSF<1:0>(2) ALP(2) — CS1P(2) — WRSP RDSP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
00 = Wait of 1 TPB (default)
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
3: These bits only control generating the Parallel Master Port (PMP) interrupt. The Parallel Master Port Error
(PMPE) is always generated.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The use of this pin as PMA14 or CS1 is selected by the CSF<1:0> bits in the PMCON register.
2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by bits ADRMUX<1:0> in the PMCON register.
CAL<9:0>
32.768 kHz Input
from Secondary
Oscillator (SOSC)
RTCC Prescalers
RTCTIME
0.5s
HR, MIN, SEC
RTCC Timer RTCVAL
RTCDATE
Alarm
YEAR, MONTH, DAY, WDAY
Event
Comparator
ALRMTIME
HR, MIN, SEC
Compare Registers ALRMVAL
with Masks ALRMDATE
MONTH, DAY, WDAY
Repeat Counter
RTSECSEL
RTCOE
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.
Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10s place digit; contains a value from 0 to 9
bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1s place digit; contains a value from 0 to 9
bit 23-21 Unimplemented: Read as ‘0’
bit 20 MONTH10: Binary-Coded Decimal Value of Months bits, 10s place digit; contains a value of 0 or 1
bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1s place digit; contains a value from 0 to 9
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 DAY10<1:0>: Binary-Coded Decimal Value of Days bits, 10s place digit; contains a value of 0 to 3
bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1s place digit; contains a value from 0 to 9
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 WDAY01<2:0>: Binary-Coded Decimal Value of Weekdays bits; contains a value from 0 to 6
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
AN0
AN12(2)
VCFG<2:0>
CTMUT(3)
ADC1BUF0
IVREF(4)
ADC1BUF1
Open(5)
ADC1BUF2
S&H VREFH VREFL
Channel
Scan +
CH0SA<4:0> CH0SB<4:0> SAR ADC
-
CSCNA
AN1
ADC1BUFE
VREFL
ADC1BUFF
CH0NA CH0NB
Alternate
Input Selection
Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs.
2: The AN8 pin is only available on 44-pin devices. The AN6 and AN7pins are not available on 28-pin devices. The
AN12 pin is available on all General Purpose Devices as well as 36 and 44 pin USB Devices.
3: Connected to the CTMU module. See Section 25.0 “Charge Time Measurement Unit (CTMU)” for more
information.
4: Internal precision voltage reference (1.2V).
ADRC
FRC(1) Div 2 1
TAD
ADCS<7:0> 0
ADC Conversion
Clock Multiplier
TPB(2)
2, 4,..., 512
Note 1: See Section 30.0 “Electrical Characteristics” for the exact FRC clock value.
2: Refer to Figure 8-1 in Section 8.0 “Oscillator Configuration” for more information.
TABLE 22-1:
Virtual Address ADC REGISTER MAP
Bits
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
9000 AD1CON1(1)
15:0 ON — SIDL — — FORM<2:0> SSRC<2:0> CLRASAM — ASAM SAMP DONE
15:0 0000
31:16 0000
9100 ADC1BUF9 ADC Result Word 9 (ADC1BUF9<31:0>)
15:0 0000
31:16 0000
9110 ADC1BUFA ADC Result Word A (ADC1BUFA<31:0>)
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for details.
DS60001168L-page 216
TABLE 22-1: ADC REGISTER MAP (CONTINUED)
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
9120 ADC1BUFB ADC Result Word B (ADC1BUFB<31:0>)
15:0 0000
31:16 0000
9130 ADC1BUFC ADC Result Word C (ADC1BUFC<31:0>)
15:0 0000
31:16 0000
9140 ADC1BUFD ADC Result Word D (ADC1BUFD<31:0>)
15:0 0000
31:16 0000
9150 ADC1BUFE ADC Result Word E (ADC1BUFE<31:0>)
15:0 0000
31:16 0000
9160 ADC1BUFF ADC Result Word F (ADC1BUFF<31:0>)
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for details.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8 (1)
ON — SIDL — — FORM<2:0>
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC
7:0 (2) (3)
SSRC<2:0> CLRASAM — ASAM SAMP DONE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ‘0’, this
bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ‘0’, this
bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111.
2: This bit is not used if the ADRC (AD1CON3<15>) bit = 1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This selection is only used with CTMU capacitive and time measurement.
2: See Section 24.0 “Comparator Voltage Reference (CVREF)” for more information.
3: See Section 25.0 “Charge Time Measurement Unit (CTMU)” for more information.
4: The AN8 pin is only available on the 44-pin devices. The AN6 and AN7 pins are not available on the 28-pin
devices. The AN12 pin is available on all General Purpose Devices as well as 36 and 44 pin USB Devices.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: CSSL = ANx, where ‘x’ = 0-12; CSSL13 selects CTMU input for scan; CSSL14 selects IVREF for scan;
CSSL15 selects VSS for scan.
2: On devices with less than 13 analog inputs, all CSSLx bits can be selected; however, inputs selected for
scan without a corresponding input on the device will convert to VREFL.
C1INC
COE
C1IND
CMP1 C1OUT
CREF
CPOL CMSTAT<C1OUT>
C1INA CM1CON<COUT>
C2INC
COE
C2IND
CMP2 C2OUT
CREF
CPOL CMSTAT<C2OUT>
C2INA CM2CON<COUT>
C3INB CCH<1:0>
C3INC
COE
C3IND
CMP3 C3OUT
CREF
C3INA CMSTAT<C3OUT>
CPOL
CM3CON<COUT>
CVREF(1)
Note 1: Internally connected. See Section 24.0 “Comparator Voltage Reference
(CVREF)” for more information.
2: Internal precision voltage reference (1.2V).
IVREF(2)
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
A000 CM1CON
15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3
31:16 — — — — — — — — — — — — — — — — 0000
A010 CM2CON
15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3
31:16 — — — — — — — — — — — — — — — — 0000
A020 CM3CON
15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3
31:16 — — — — — — — — — — — — — — — — 0000
A060 CMSTAT
15:0 — — SIDL — — — — — — — — — — C3OUT C2OUT C1OUT 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 23-1: CMXCON: COMPARATOR CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R-0
15:8 (1) (2)
ON COE CPOL — — — — COUT
R/W-1 R/W-1 U-0 R/W-0 U-0 U-0 R/W-1 R/W-1
7:0
EVPOL<1:0> — CREF — — CCH<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CVRSS = 1
VREF+ CVRSRC
AVDD
CVRSS = 0 8R
CVR<3:0> CVREF
CVREN R
R
16-to-1 MUX
16 Steps
CVREFOUT
CVRCON<CVROE>
R
R
R
CVRR 8R
CVRSS = 1
VREF-
AVSS
CVRSS = 0
All Resets
Bit Range
(BF80_#)
Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
9800 CVRCON
15:0 ON — — — — — — — — CVROE CVRR CVRSS CVR<3:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8 (1)
ON — — — — — — —
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— CVROE CVRR CVRSS CVR<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
25.0 CHARGE TIME The CTMU module includes the following key features:
MEASUREMENT UNIT (CTMU) • Up to 13 channels available for capacitive or time
measurement input
Note: This data sheet summarizes the features • On-chip precision current source
of the PIC32MX1XX/2XX 28/36/44-pin
• 16-edge input trigger sources
Family of devices. It is not intended to be
a comprehensive reference source. To • Selection of edge or level-sensitive inputs
complement the information in this data • Polarity control for each edge source
sheet, refer to Section 37. “Charge Time • Control of edge sequence
Measurement Unit (CTMU)” • Control of response to edges
(DS60001167), which is available from the • High precision time measurement
Documentation > Reference Manual
• Time delay of external or internal signal asynchro-
section of the Microchip PIC32 web site
nous to system clock
(www.microchip.com/pic32).
• Integrated temperature sensing diode
The Charge Time Measurement Unit (CTMU) is a flex- • Control of current source during auto-sampling
ible analog module that has a configurable current • Four current source ranges
source with a digital configuration circuit built around it.
• Time measurement resolution of one nanosecond
The CTMU can be used for differential time measure-
ment between pulse sources and can be used for gen- A block diagram of the CTMU is shown in Figure 25-1.
erating an asynchronous pulse. By working with other
on-chip analog modules, the CTMU can be used for
high resolution time measurement, measure capaci-
tance, measure relative changes in capacitance or
generate output pulses with a specific time delay. The
CTMU is ideal for interfacing with capacitive-based
sensors.
CTMUCON1 or CTMUCON2
CTMUCON
ITRIM<5:0>
IRNG<1:0>
Current Source
CTED1
• Edge
• Control CTMU ADC
• Logic EDG1STAT
TGEN Control Trigger
CTED13 EDG2STAT
Current Logic
Control
Timer1
OC1
CTMUP Pulse CTPLS
IC1-IC3
Generator
CMP1-CMP3
CTMUI
PBCLK (To ADC S&H capacitor)
CTMUT
(To ADC)
C2INB
Temperature
Sensor
CDelay
Comparator 2
External capacitor
for pulse generation
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0> — — 0000
A200 CTMUCON
15:0 ON — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG ITRIM<5:0> IRNG<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for
more information.
2011-2019 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to ‘1110’ to select
C2OUT.
2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
3: Refer to the CTMU Current Source Specifications (Table 30-41) in Section 30.0 “Electrical
Characteristics” for current values.
4: This bit setting is not available for the CTMU temperature diode.
Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to ‘1110’ to select
C2OUT.
2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
3: Refer to the CTMU Current Source Specifications (Table 30-41) in Section 30.0 “Electrical
Characteristics” for current values.
4: This bit setting is not available for the CTMU temperature diode.
Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to ‘1110’ to select
C2OUT.
2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
3: Refer to the CTMU Current Source Specifications (Table 30-41) in Section 30.0 “Electrical
Characteristics” for current values.
4: This bit setting is not available for the CTMU temperature diode.
NOTES:
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 — — — — — — — — — — — — — — — — 0000
F240 PMD1
15:0 — — — CVRMD — — — CTMUMD — — — — — — — AD1MD 0000
31:16 — — — — — — — — — — — — — — — — 0000
F250 PMD2
All Resets
Bit Range
(BFC0_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Bits
All Resets(1)
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
— —
31:16 0000
F230 SYSKEY(3) SYSKEY<31:0>
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset values are dependent on the device variant.
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
REGISTER 27-1: DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P
31:24
— — — CP — — — BWP
r-1 r-1 r-1 r-1 r-1 R/P R/P R/P
23:16
— — — — — PWP<8:6>(3)
R/P R/P R/P R/P R/P R/P r-1 r-1
15:8
PWP<5:0> — —
r-1 r-1 r-1 R/P R/P R/P R/P R/P
7:0
— — — ICESEL<1:0>(2) JTAGEN(1) DEBUG<1:0>
Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register.
2: The PGEC4/PGED4 pin pair is not available on all devices. Refer to the “Pin Diagrams” section for
availability.
3: The PWP<8:7> bits are only available on devices with 256 KB Flash.
Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register.
2: The PGEC4/PGED4 pin pair is not available on all devices. Refer to the “Pin Diagrams” section for
availability.
3: The PWP<8:7> bits are only available on devices with 256 KB Flash.
Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 6. “Oscillator”
(DS60001112) in the “PIC32 Family Reference Manual” for details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID
values.
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
FRC Cycles
D136 TRW Row Write Cycle Time — 6675 — See Note 2,4
D137 TPE Page Erase Cycle Time — 20011 — See Note 4
TCE Chip Erase Cycle Time — 80180 — See Note 4
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus
loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The
default Arbitration mode is mode 1 (CPU has lowest priority).
3: Refer to the “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programming and erase cycles.
4: Translating this value to seconds depends on the FRC accuracy (See Table 30-19) and FRC tuning values
(See Register 8-2).
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins
VSS 50 pF for OSC2 pin (EC mode)
OSC1
OS30 OS31
For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
D CLK D CLK
EffectiveJitter = -------------- = --------------
40 1.41
------
20
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 30-1 for load conditions.
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
(Note 1)
VPOR (TSYSDLY)
SY02
Power-up Sequence
(Note 2)
Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
2: Includes interval voltage regulator stabilization delay.
MCLR
TMCLR
(SY20)
BOR
TBOR (TSYSDLY)
(SY30) SY02
Reset Sequence
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRx
IC10 IC11
IC15
OCx
(Output Compare
or PWM mode) OC11 OC10
OC20
OCFA/OCFB
OC15
SCKx
(CKP = 1)
SP31 SP30
SP40 SP41
SCKX
(CKP = 1)
SP35
SP20 SP21
SP30,SP31
SSX
SP50 SP52
SCKX
(CKP = 0)
SP71 SP70
SP73 SP72
SCKX
(CKP = 1)
SP72 SP73
SP35
SP30,SP31 SP51
SP50 SP52
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SP35
SP72 SP73
SP30,SP31 SP51
SDI
SDIx
MSb In Bit 14 - - - -1 LSb In
SP40 SP41
SCLx
IM31 IM34
IM30 IM33
SDAx
Start Stop
Condition Condition
SDAx
Out
SCLx
IS31 IS34
IS30 IS33
SDAx
Start Stop
Condition Condition
SDAx
Out
Param.
Symbol Characteristics Min. Max. Units Conditions
No.
IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns —
Hold Time 400 kHz mode 600 — ns
1 MHz mode 250 ns
(Note 1)
IS40 TAA:SCL Output Valid from 100 kHz mode 0 3500 ns —
Clock 400 kHz mode 0 1000 ns
1 MHz mode 0 350 ns
(Note 1)
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s The amount of time the bus
400 kHz mode 1.3 — s must be free before a new
transmission can start
1 MHz mode 0.5 — s
(Note 1)
IS50 CB Bus Capacitive Loading — 400 pF —
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
CHX
ANx
SHA ADC
ANx CHX
SHA ADC
ANx or VREF-
Note 1: External VREF- and VREF+ pins must be used for correct operation.
2: These parameters are characterized, but not tested in manufacturing.
3: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise
stated, module functionality is tested, but not characterized.
AD50
ADCLK
Instruction
Execution Set SAMP Clear SAMP
SAMP
ch0_dischrg
ch0_samp
eoc
AD61
AD60
CONV
ADxIF
Buffer(0)
Buffer(1)
1 2 3 4 5 6 7 8 5 6 7 8
AD50
ADCLK
Instruction
Execution Set ADON
SAMP
ch0_dischrg
ch0_samp
eoc
TSAMP TSAMP
AD55 AD55 TCONV
CONV
ADxIF
Buffer(0)
Buffer(1)
1 2 3 4 5 6 7 3 4 5 6 8 3 4
2 – Sampling starts after discharge period. 6 – One TAD for end of conversion.
TSAMP is described in Section 17. “10-bit Analog-to-Digital
Converter (ADC)” (DS60001104). 7 – Begin conversion of next channel.
4 – Convert bit 8.
CS
PS5
RD
PS6
WR
PS4 PS7
PMD<7:0>
PS1
PS3
PS2
PB Clock
PM4
PMA<13:18> Address
PM6
PMD<7:0> Address<7:0>
Address<7:0> Data
Data
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
PB Clock
PMA<13:18> Address
PM2 + PM3
PM12
PM13
PMRD
PM11
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TTCKcyc
TTCKhigh TTCKlow
Trf
TCK
Trf
TMS
TDI
TDO
TTRST*low
TTDOout TTDOzstate
TRST*
Defined Undefined
Trf
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
VOH (V)
-0.050 VOL(V)
0.050
-0.045 3.6V
0.045 3.6V
-0.040
3.3V 0.040 3.3V
-0.035
0.035 3V
-0.030 3V
0.030
IOH(A)
IOH(A)
-0.025 0.025
-0.020 0.020
-0.015 Absolute Maximum 0.015 Absolute Maximum
-0.010 0.010
-0.005 0.005
0.000 0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
DS60001168L-page 311
DS60001168L-page 312
FIGURE 32-3: TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 32-5: TYPICAL IIDLE CURRENT @ VDD = 3.3V
300 6
200
4
150
3
IID
100
2
50
0 1
MIPS
25
20
2011-2019 Microchip Technology Inc.
15
IDD (mA)
10
0
0 10 20 30 40
MIPS
FIGURE 32-6: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 32-8: TYPICAL CTMU TEMPERATURE DIODE
2011-2019 Microchip Technology Inc.
FORWARD VOLTAGE
8000
7990 0.850
7980 0.800
A, VF
0.700 VF = 0.721 V
R = -1.5
7900 0.350
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
33
LPRC Frequency (kHz)
32
31
DS60001168L-page 313
30
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (Celsius)
PIC32MX1XX/2XX 28/36/44-PIN FAMILY
NOTES:
XXXXXXXXXXXXXXXXXXXX PIC32MX220F
XXXXXXXXXXXXXXXXXXXX 032B-I/SO e3
XXXXXXXXXXXXXXXXXXXX 1130235
YYWWNNN
XXXXXXXXXXXXXXXXX PIC32MX220F
XXXXXXXXXXXXXXXXX 032B-I/SP e3
YYWWNNN 1130235
XXXXXXXXXXXX PIC32MX220F
XXXXXXXXXXXX 032B-I/SS e3
YYWWNNN 1130235
28-Lead QFN
Example
XXXXXXXX 32MX220F
XXXXXXXX 032BE/ML e3
YYWWNNN 1130235
Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
XXXXXXXX 32MX220F
XXXXXXXX 032CE/TL e3
YYWWNNN 1130235
XXXXXXXXXX PIC32
XXXXXXXXXX MX120F0
XXXXXXXXXX 32DI/TL e3
YYWWNNN 1130235
XXXXXXXXXX 32MX220F
XXXXXXXXXX 032D-E/ML e3
XXXXXXXXXX 1130235
YYWWNNN
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“32-bit Microcontrollers (up to 128 KB Split the existing Features table into two: PIC32MX1XX General Purpose
Flash and 32 KB SRAM) with Audio Family Features (Table 1) and PIC32MX2XX USB Family Features (Table 2).
and Graphics Interfaces, USB, and
Added the SPDIP package reference (see Table 1, Table 2, and “Pin
Advanced Analog”
Diagrams”).
Added the new devices to the applicable pin diagrams.
Changed PGED2 to PGED1 on pin 35 of the 36-pin VTLA diagram for
PIC32MX220F032C, PIC32MX220F016C, PIC32MX230F064C, and
PIC32MX250F128C devices.
1.0 “Device Overview” Added the SPDIP package reference and updated the pin number for AN12
for 44-pin QFN devices in the Pinout I/O Descriptions (see Table 1-1).
Added the PGEC4/PGED4 pin pair and updated the C1INA-C1IND and
C2INA-C2IND pin numbers for 28-pin SSOP/SPDIP/SOIC devices in the
Pinout I/O Descriptions (see Table 1-1).
2.0 “Guidelines for Getting Started Updated the Recommended Minimum Connection diagram (see Figure 2-1).
with 32-bit Microcontrollers”
4.0 “Memory Organization” Added Memory Maps for the new devices (see Figure 4-3 and Figure 4-4).
Removed the BMXCHEDMA bit from the Bus Matrix Register map (see
Table 4-1).
Added the REFOTRIM register, added the DIVSWEN bit to the REFOCON
registers, added Note 4 to the ULOCK and SOSCEN bits and added the
PBDIVRDY bit in the OSCCON register in the in the System Control Register
map (see Table 4-16).
Removed the ALTI2C1 and ALTI2C2 bits from the DEVCFG3 register and
added Note 1 to the UPLLEN and UPLLIDIV<2:0> bits of the DEVCFG2
register in the Device Configuration Word Summary (see Table 4-17).
Updated Note 1 in the Device and Revision ID Summary (see Table 4-18).
Added Note 2 to the PORTA Register map (see Table 4-19).
Added the ANSB6 and ANSB12 bits to the ANSELB register in the PORTB
Register map (see Table 4-20).
Added Notes 2 and 3 to the PORTC Register map (see Table 4-21).
Updated all register names in the Peripheral Pin Select Register map (see
Table 4-23).
Added values in support of new devices (16 KB RAM and 32 KB RAM) in the
Data RAM Size register (see Register 4-5).
Added values in support of new devices (64 KB Flash and 128 KB Flash) in
the Data RAM Size register (see Register 4-5).
8.0 “Oscillator Configuration” Added Note 5 to the PIC32MX1XX/2XX Family Clock Diagram (see
Figure 8-1).
Added the PBDIVRDY bit and Note 2 to the Oscillator Control register (see
Register 8-1).
Added the DIVSWEN bit and Note 3 to the Reference Oscillator Control
register (see Register 8-3).
Added the REFOTRIM register (see Register 8-4).
21.0 “10-bit Analog-to-Digital Updated the ADC1 Module Block Diagram (see Figure 21-1).
Converter (ADC)”
Updated the Notes in the ADC Input Select register (see Register 21-4).
24.0 “Charge Time Measurement Updated the CTMU Block Diagram (see Figure 24-1).
Unit (CTMU)”
Added Note 3 to the CTMU Control register (see Register 24-1)
26.0 “Special Features” Added Note 1 and the PGEC4/PGED4 pin pair to the ICESEL<1:0> bits in
DEVCFG0: Device Configuration Word 0 (see Register 26-1).
Removed the ALTI2C1 and ALTI2C2 bits from the Device Configuration
Word 3 register (see Register 26-4).
Removed 26.3.3 “Power-up Requirements”.
Added Note 3 to the Connections for the On-Chip Regulator diagram (see
Figure 26-2).
Updated the Block Diagram of Programming, Debugging and Trace Ports
diagram (see Figure 26-3).
29.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings (removed Voltage on VCORE with
respect to VSS).
Added the SPDIP specification to the Thermal Packaging Characteristics
(see Table 29-2).
Updated the Typical values for parameters DC20-DC24 in the Operating
Current (IDD) specification (see Table 29-5).
Updated the Typical values for parameters DC30a-DC34a in the Idle Current
(IIDLE) specification (see Table 29-6).
Updated the Typical values for parameters DC40i and DC40n and removed
parameter DC40m in the Power-down Current (IPD) specification (see
Table 29-7).
Removed parameter D320 (VCORE) from the Internal Voltage Regulator
Specifications and updated the Comments (see Table 29-13).
Updated the Minimum, Typical, and Maximum values for parameter F20b in
the Internal FRC Accuracy specification (see Table 29-17).
Removed parameter SY01 (TPWRT) and removed all Conditions from Resets
Timing (see Table 29-20).
Updated all parameters in the CTMU Specifications (see Table 29-39).
31.0 “Packaging Information” Added the 28-lead SPDIP package diagram information (see 31.1 “Package
Marking Information” and 31.2 “Package Details”).
“Product Identification System” Added the SPDIP (SP) package definition.
“32-bit Microcontrollers (up to 128 KB Revised the source/sink on I/O pins (see “Input/Output” on page 1).
Flash and 32 KB SRAM) with Audio
Added the SPDIP package to the PIC32MX220F032B device in the
and Graphics Interfaces, USB, and
PIC32MX2XX USB Family Features (see Table 2).
Advanced Analog”
4.0 “Memory Organization” Removed ANSB6 from the ANSELB register and added the ODCB6,
ODCB10, and ODCB11 bits in the PORTB Register Map (see Table 4-20).
29.0 “Electrical Characteristics” Updated the minimum value for parameter OS50 in the PLL Clock Timing
Specifications (see Table 29-16).
“32-bit Microcontrollers (up to 128 Corrected a part number error in all pin diagrams.
KB Flash and 32 KB SRAM) with
Updated the DMA Channels (Programmable/Dedicated) column in the
Audio and Graphics Interfaces, USB,
PIC32MX1XX General Purpose Family Features (see Table 1).
and Advanced Analog”
1.0 “Device Overview” Added the TQFP and VTLA packages to the 44-pin column heading and
updated the pin numbers for the SCL1, SCL2, SDA1, and SDA2 pins in the
Pinout I/O Descriptions (see Table 1-1).
7.0 “Interrupt Controller” Updated the Note that follows the features.
Updated the Interrupt Controller Block Diagram (see Figure 7-1).
29.0 “Electrical Characteristics” Updated the Maximum values for parameters DC20-DC24, and the Minimum
value for parameter DC21 in the Operating Current (IDD) DC Characteristics
(see Table 29-5).
Updated all Minimum and Maximum values for the Idle Current (IIDLE) DC
Characteristics (see Table 29-6).
Updated the Maximum values for parameters DC40k, DC40l, DC40n, and
DC40m in the Power-down Current (IPD) DC Characteristics (see Table 29-7).
Changed the minimum clock period for SCKx from 40 ns to 50 ns in Note 3 of
the SPIx Master and Slave Mode Timing Requirements (see Table 29-26
through Table 29-29).
30.0 “DC and AC Device Updated the Typical IIDLE Current @ VDD = 3.3V graph (see Figure 30-5).
Characteristics Graphs”
32-bit Microcontrollers (up to 256 Added new devices to the family features (see Table 1 and Table 2).
KB Flash and 64 KB SRAM) with
Updated pin diagrams to include new devices (see Pin Diagrams).
Audio and Graphics Interfaces,
USB, and Advanced Analog
2.0 “Guidelines for Getting Updated these sections: 2.2 “Decoupling Capacitors”, 2.3 “Capacitor on
Started with 32-bit MCUs” Internal Voltage Regulator (VCAP)”, 2.4 “Master Clear (MCLR) Pin”,
2.8.1 “Crystal Oscillator Design Consideration”
4.0 “Memory Organization” Added Memory Map for new devices (see Figure 4-6).
14.0 “Watchdog Timer (WDT)” New chapter created from content previously located in the Special Features
chapter.
30.0 “Electrical Characteristics” Removed parameter D312 (TSET) from the Comparator Specifications (see
Table 30-12).
Added the Comparator Voltage Reference Specifications (see Table 30-13).
Updated Table 30-12.
2.0 “Guidelines for Getting Section 2.9 “Sosc Design Recommendation” was removed.
Started with 32-bit MCUs”
8.0 “Oscillator Configuration” The Primary Oscillator (POSC) logic in the Oscillator diagram was updated (see
Figure 8-1).
30.0 “Electrical Characteristics” The Power-Down Current (IPD) DC Characteristics parameter DC40k was
updated (see Table 30-7).
Table 30-9: “DC Characteristics: I/O Pin Input Injection current
Specifications” was added.
“32-bit Microcontrollers (up to The PIC32MX270FDB device and Note 4 were added to TABLE 2: “PIC32MX2XX
256 KB Flash and 64 KB 28/36/44-pin USB Family Features”.
SRAM) with Audio and
Graphics Interfaces, USB, and
Advanced Analog”
2.0 “Guidelines for Getting EXAMPLE 2-1: “Crystal Load Capacitor Calculation” was updated.
Started with 32-bit MCUs”
30.0 “Electrical Parameter DO50a (CSOSC) was removed from the Capacitive Loading
Characteristics” Requirements on Output Pins AC Characteristics (see Table 30-16).
“Product Identification The device mapping was updated to include type B for Software Targeting.
System”
“32-bit Microcontrollers (up to The PIC32MX270F256DB device and Note 4 were removed from the
256 KB Flash and 64 KB PIC32MX2XX 28/36/44-Pin USB Family Features (see Table 2).
SRAM) with Audio and
Graphics Interfaces, USB, and
Advanced Analog”
“Product Identification Type B for Software Targeting was removed.
System”
Section 2.10 “Considerations A new section has been added.
When Interfacing To Remotely
Powered Circuits”
2.0 “Guidelines for Getting Added new section 2.11 “EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2)
Started with 32-bit MCUs” Suppression Considerations”
17.0 “Serial Peripheral Updated information for the FRMPOL bit for Register 17-1: “SPIx CON: SPI
Interface (SPI)” Control Register”
20.0 “Parallel Master Port • Updated Register 20-2: “PMMODE: Parallel Port Mode Register” with a new
(PMP)” Note 3
• Updated Register Register 20-5: “PMSTAT: Parallel Port Status Register
(Slave modes only)”with a new Note 1
22.0 “10-bit Analog-to-Digital • Updated Note 2 of FIGURE 22-1: “ADC1 Module Block Diagram”
Converter (ADC)” • Updated Note 4 of Register 22-4: “AD1CHS: ADC Input Select Register”
Temperature Range
Package
Pattern
Speed () = 40 MHz – ( ) indicates a blank field; package markings for 40 MHz devices do not include the Speed
50 = 50 MHz
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
== ISO/TS 16949 ==
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