TABLE OF CONTENTS

Unit No Contents Page No

1 MOS TRANSISTOR PRINCIPLES 1

1.1 Introduction 1
1.2 MOS Transistor Technology 1
1.2.1 Enhancement and Depletion Mode 3
1.3 CMOS Logic 7
1.4 MOSFET Current-Voltage Characteristics 10
1.5 CMOS Devices 15
1.5.1 PMOS 16
1.5.2 CMOS Logic Gates 19
1.5.3 CMOS Inverter 20
1.5.4 CMOS NAND 21
1.5.5 CMOS NOR 23
1.6 MOSFET – Static and Dynamic Conditions 27
1.6.1 Operating Regions - MOSFET 31
1.6.2 Beta Ratio 31
1.7 Technology Scaling 32
1.7.1 Types of Scaling 33

2 COMBINATIONAL LOGIC CIRCUITS 36

2.1 Delay Estimation 36

2.2 Layout Design Rules 37
2.2.1 Encodings for NMOS Process 40
2.2.2 CMOS Layout Encoding 41
2.2.3 nMOS Inverter 43
2.2.4 CMOS Inverter 44
2.2.5 Threshold Voltage 46
2.3 Combinational Logic Design - Examples 47
2.3.1 Complex Gates in CMOS Logic 47
2.4 RC Delay Model 51
2.4.1 Elmore Delay – Implementation 52
2.4.2 Parasitic Delay and Logic Effort 53
2.5 Circuit Families : Static CMOS 55
2.5.1 Static Logic Design of Logic Gates 59
2.5.2 Pass Transistor 60
2.5.3 Transmission Gate 62
2.5.4 CMOS Domino Logic 63
2.5.5 Complementary Pass Transistor Logic 64
2.5.6 DCVSL Logic Gate 66
 2.5.7 Double Pass Transistor Logic 66
2.6 Power Supply IR Drops 71
2.7 Power in Combinational Logic Circuits 74
2.7.1 Dynamic Power 75
2.7.2 Static Power 77
2.8 Low Power VLSI Chip Design 81
2.9 Sources of Power Dissipation 82
2.10 Low Power Design Techniques 82
2.10.1 VLSI Circuit Design for Low Power 83
2.10.2 Logic Design For Low Power 85
2.10.3 Short Circuit Power Suppression 91

3 SEQUENTIAL LOGIC CIRCUITS AND 93

CLOCKING STRATEGIES

3.1 Static Latches and Registers 93

3.1.1 Introduction 93
3.1.2 Timing Metrics for Sequential Circuits 94
3.1.3 Latches vs Registers 96
3.1.4 Static Latches 97
3.1.5 Multiplexer Based Latches 98
3.1.6 Master – Slave Edge Triggered Register 100
3.17 Timing Properties of Multiplexer 101
3.2 Dynamic Latches and Registers 105
3.2.1 Dynamic Transmission Gate 106
3.2.2 MOS Register 107
109
3.2.3 Dual Edge Triggered Registers 110
3.2.4 True Single Phased Clock Register 113
3.2.5 Pulse Registers 115
3.26 Sense-Amplifier based Registers
3.3 Pipelining in Sequential Circuits 116
3.3.1 Latches vs. Register Based Pipelines 118
3.4 Schmitt Trigger 119
3.4.1 Mono stable Sequential Circuits 121
3.4.2 Astable Sequential Circuits 122
3.5 Timing Issues 123
3.5.1 Synchronous Interconnect 124
3.5.2 Mesochronous Interconnect 125
3.5.3 Plesiochronous Interconnect 126
3.5.4 Asynchronous Interconnect 127
3.5.5 Synchronous Timing Basics 127
3.5.6 Clock Skew 129
3.5.7 Clock Jitter 132
3.6 Self Timed Circuit Design 138
 3.6.1 Synchronous vs Asynchronous Design 143
4 INTERCONNECT,MEMORY 145
ARCHITECTURE AND ARITHMETIC
CIRCUITS

4.1 Introduction to Wires 145

4.2 Interconnect Parameters 146
4.2.1 Wire Resistance 146
4.2.2 Wire Capacitance 148
4.2.3 Wire Inductance 152
4.3 Wire Delay Modeling 153
4.3.1 The Lumped Model 154
4.3.2 Capacitive Cross talk 155
4.3.3 Other Wire Effects 157
4.3.4 Optimizing Wire Geometry 158
4.3.5 Repeaters 160
4.3.6 Advanced Signaling Techniques 161
4.4 Sequential Logic Circuits 163
4.4.1 Adders 163
4.4.2 Multipliers 174
4.4.3 Shifters 183
4.5 Logic Implementation – Programmable Device 188
4.5.1 Read only Memory (ROM) 188
4.5.2 Types of ROM 191
4.6 Programmable Logic Array (PLA) 193
4.6.1 Design Procedure with PLA 196
4.7 Field Programmable Gate Arrays (FPGA) 200
4.7.1 FPGA Architecture 200
4.8 Semiconductor Memory Classification 203
4.8.1 Memory Functional Classification 204
4.8.2 Hierarchial Memory Architecture 207
4.8.3 Memory Core 210
4.9 Memory Peripheral Circuitry 212

5 ASIC DESIGN AND TESTING 215

5.1 Wafer to Chip Fabrication Process 215

5.1.1 Silicon Wafer Manufacturing 216
5.2 Microchip Design Process 222
5.3 Embedded Cores and SOC’S 225
5.4 Issues in Testing and Fault Models 228
5.4.1 Ad Hoc Testing 228
5.4.2 Various Process During Testing 229
5.4.3 Fault Models 230
5.4.4 DFT Techniques 234
 5.4.5 Scan Path Design 238
5.5 ASIC Design Flow 240
5.5.1 ASIC Design Cycle Working 241
5.6 Introduction to ASIC’s 247
5.6.1 Types of ASIC’s 247
5.6.2 Gate Array Based ASIC 251
5.6.3 Structured Gate Arrays 253
5.6.4 Programmable ASIC’s 255
5.7 Introduction to Test Benches 256
5.7.1 Generating Clock Signals 258
5.7.2 Automating Design through Test bench 259
5.7.3 VHDL Time Type 262
5.8 Writing Test Benches in Verilog HDL 264
5.8.1 Verilog Test Bench – Examples 264
5.8.2 Test Bench with Test Vectors 267
5.9 Automatic Test Pattern Generation 272
5.9.1 ATPG Classification 273
5.9.2 Stages of ATPG 274
5.10 Implementation – Design for Testability 276
5.10.1 Built-In Self Test 276
5.10.2 LSRG 277
5.10.3 Design For Manufacturability 280
5.10.4 Boundary Scan 282
5.10.5 Elementary Boundary Scan Cell 284