CMOS RF Transceiver for WLAN IEEE 802.

11a
Low Noise Amplifier (LNA)

Prepared By
Eng. Mahmoud Hashem Mahmed Hamad
Email: mahmoud.hashem645@gmail.com

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 Low Noise Amplifier

3.1 GENERAL CONSIDERATIONS

LNA is one of the most critical blocks in the receiver chain. It can be considered as the first block that the
signal faces, so it has a critical role in the overall performance of the Rx. Various kinds of LNAs are
available for different applications, such as narrow band, multiple bands and wide-band LNAs. So there are
some parameters we have to take in considerations while designing the LNA.

The noise figure of the LNA is one of the parameters that must be taken into considerations. Since the LNA
is the first block, so its NF is directly added to the total noise figure of the circuit., and this due to Friis
formula (3.1):

(3.1)

The total noise factor is the sum of contribution from all stages, where the noise factor of stage N is divided
by the total gain from input to stage N. In case of radio receiver where the first stage is a LNA the formula
(3.1) can be rewritten to (3.2), where FREST is the noise figure of the subsequent stages.

(3.2)

We can see from the formula (3.2) that if the gain is sufficiently high the overall noise figure is dominated
by the noise figure of the first stage, normally a LNA.

Another parameter that should be taken into considerations is the input return loss. Since the LNA is
connected to the antenna, then an input matching must be made to the LNA so that the energy of the
received signal is totally absorbed and not reflected back causing an ineffective reception. However, in
most cases there is a band select filter between antenna and LNA. The performances of those filters are
heavily depended on the correct termination. The input matching can be measured by measuring the input
return loss (S11). For proper matching in the LNA, S11 parameter should be < -10dB.

The linearity of the LNA is another vital parameter. Although the main function of the LNA is providing
maximum amplification without adding much noise, the LNA must remain linear, independent of the signal
strength received. The linearity of the LNA plays a most important role in the case when receiving a weak
signal in presence of a strong interfering one because the nonlinearities then will result in intermodulation
distortion, desensitization (blocking) and cross-modulation. The most common used measures for linearity
are 1-dB compression point (P1dB) and third-order intercept point (IP3).
P1 dB can be used to determine the gain desensitization. It is defined as the input signal level that causes
the gain to drop by 1-dB.

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 Figure 3.1: 1-dB compression point.

Third-order intercept point is the measure of intermodulation products and indicates how well the receiver
performs in the presence of strong interferers. The IP3 is important as third-order nonlinearity products
tend to fall within wanted frequency band and interfere with the wanted signal.

There is no fixed relationship between measures of P1dB and IP3 as they characterize linearity in two
distinctive regimes. However, the IP3 or P1dB can be easily estimate by using following approximation:

(3.3)

We have always to check the stability of the low noise amplifier since it could be converted to an oscillator
instead its function of amplifying. the LNA must remain stable for all source impedances at all frequencies
not only in the frequency band of interest. Thus the LNA should be stable in the frequency range where it
operates as amplifier (frequency until gain = 0dB). The most common measurement that is used to measure
the stability is the “Stern stability factor” and it’s defined as:

, where (3.4)

If K > 1 and < 1, then the circuit is unconditionally stable, i.e., it does not oscillate with any combination of
source and load impedances.

Figure 3.2: Third order intercept point (IIP3).

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3.2 CASCODED COMMON SOURCE WITH INDUCTIVE DEGENERATION
Low noise amplifier is an important and critical part in analog front end of receiver, as it the first part in
receiver and interface. its role is amplification of weak signal without adding noise through narrow band
width.so that it controls receiver sensitivity which depends on noise figure, gain, band width, linearity and
dynamic range. Also, it limits the performance of the communication receiver system. designers need to get
the optimized performance of low noise amplifier through getting high gain, low power consumption, small
chip area, good input matching and low cost. Optimization is a complex task as all parameters have
tradeoff between them. there are several topologies to achieve design parameters with difference
performance.

3.2.1 Common Source Topologies

Common source CMOS transistors in which input is driven to gate and output is taken from drain.
Common source has voltage gain, and current gain and its input impedance equal to infinity .
3.2.1.1 parallel resistive termination
We can use resistive termination of 50 ohms to match the LNA to the input resistance of 50 ohms.it
provide perfect matching, but gives higher noise figure due to presence of resistance and low gain.

3.2.1.2 resistive feedback

It is based on using a feedback resistor located between the drain and the gate of the amplifying device. By
placing this resistor, the input impedance presents a real part that can be used for impedance matching. As
compared to performing input impedance matching by using a parallel resistance, the signal is not
attenuated at the input and therefore provides a better noise figure. Nevertheless, the feedback resistor adds

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thermal noise which, depending on the required value of the resistor to provide input impedance matching,
may become a dominant factor in the total noise generated by the amplifier. When using resistive feedback,
reverse isolation is degraded even when using a cascade topology, therefore it is important to ensure that
the circuit is stable within the desired frequency range.

3.2.1.3 cascade common source inductively degenerated

Common source inductively degenerated is the most frequently used topology .and it is the best choice for
narrow bandwidth application due to its low noise figure, higher gain, low power consumption. In this
architecture input matching is provided by inductive termination. there is no resistive termination in signal
path which provides low noise figure. Cascade is used to avoid positive feedback and provides isolation of
output.

3.2.2 Target specification

In our design we need to introduce a full-on chip LNA with using tsmc65nm technology for
implementation. To be suitable to work in IEEE802.11 standard with center frequency 5.5 GHZ.
and band width 800 MHZ, which means that we need to get high quality factor. LNA will work with
different modulation techniques which have different sensitivity and different data rates. LNA will receive
different power levels, so we need to extend the back off area to avoid saturation.
As receiver gain extend from 30dB to 82dB, so receiver must add enough gain.

Specifications Value
VDD 1V
Center Frequency 5.5GHZ
Band Width 800MHZ
Gain >14dB
Noise figure <4dB
S11 <-10dB
IIP,3 >-10dBm

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3.2.3 Design Methodology
In cascade common source inductively degenerated, matching is adjusted through real part of input
impedance affected by pad capacitance. Resonance frequency and band width are adjusted by degeneration
and gate inductance (LS&LG) with pad capacitance and gate source capacitance (Cgs&Cpad). gain is
adjusted through transconductance (GM) and output parallel resistance of load inductor and added parallel
resistance at output. output frequency is adjusted through adding inductor resonates with total output
capacitance and input capacitance of mixer.
Adding inductor at output is very good than resistance as voltage across it is very small. but we must add
coupling capacitance at output to avoid VDD.

3.2.3.1 Design Equation

a. Input impedance
1 𝑔𝑚 𝐿𝑠
𝑍𝑖𝑛 = + 𝑆𝐿𝑠 +
𝑆𝐶𝑔𝑠 𝐶𝑔𝑠
𝑔𝑚 𝐿𝑠
Real part equal to 𝐶𝑔𝑠
Taking into account pad capacitance Cpad
Real part equal to
2
𝐶𝑔𝑠 𝑔𝑚 𝐿𝑠
𝑅𝑟𝑒𝑎𝑙 = ( ) ∗
𝐶𝑝𝑎𝑑 + 𝐶𝑔𝑠 𝐶𝑔𝑠
So, for implementing matching

𝐶𝑔𝑠 2 𝑔𝑚 𝐿𝑠
𝑅𝑆 = (𝐶𝑝𝑎𝑑+𝐶𝑔𝑠) ∗ eq(1)
𝐶𝑔𝑠

b. Resonance frequency in input

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𝜔𝑜 2 = (𝐶𝑝𝑎𝑑+𝐶𝑔𝑠)(𝐿𝐺+𝐿𝑠) eq(2)

c. Input quality factor

𝜔𝑜(𝑙𝑔+𝑙𝑠)
𝑄𝑖𝑛 = 𝑅𝑠
eq(3)

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d. Gain
𝜔𝑡∗𝑅𝑜𝑢𝑡 𝑅𝑜𝑢𝑡
𝐴𝑉 = 2𝜔𝑜∗𝑅𝑠
= 2𝐿𝑠∗𝜔 eq(4)

e. Noise factor
𝜔𝑜 2
𝑁𝑓 = 1 + 𝑔𝑚 𝑅𝑠ϒ ( 𝜔𝑡 ) eq(5)

3.2.3.2 Design Calculation

As we need full on chip so we need to choose gate inductor small and at another hand we need to get large
inductor for good quality factor. Degeneration inductor is taken as bond wire inductance. Channel length is
taken as minimum value of technology. Oxide capacitance is calculated from technology. pad capacitance
is assumed.

Parameters Value
Degeneration inductance (LS) 1nH
L_min 60nm
Cox 12Ff/um^2
Pad capacitance 100fF

a. Input pair width &transconductance

As this device is implemented full on chip and maximum spiral inductor value can be achieved is 4nH with
quality factor about 8.
From equation (2)
𝐶𝑔𝑠 + 𝐶𝑝𝑎𝑑 = 168𝑓𝐹
Then
𝐶𝑔𝑠 = 68𝑓𝐹
From
2
𝐶𝑔𝑠 = 𝐶𝑜𝑥 𝑊 𝐿
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Then
𝑊 = 140𝑢𝑚
𝑊 140𝑢𝑚
Input pair sizing 𝐿 = 60𝑛𝑚
From equation (1)
𝑔𝑚 = 20.75𝑚𝑠
b. Current calculation
Set up schematic as in figure .and sweep over range of current. And plot gm VS id and select current value.

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c. Cascode sizing
Cascade transistor should take the same sizing as input pair as if we:
1.increase sizing we will add noise at high frequency as degeneration impedance will decrease as parallel
capacitance to it will increase at high frequency.
2.decrease sizing cascade headroom voltage will increase.
𝑊 140𝑢𝑚
So cascade sizing is the same of input pair 𝐿 = 60𝑛𝑚

d. Load design
At load we need to add inductor to resonate with total capacitance at output. but we need to implement full
on chip LNA .so we assume value to load inductor and add additional capacitance .to get certain gain we
calculate total output resistance and add resistance parallel to inductor adjust gain.
Calculating Cadd
From tools >>result browser>>dcop
Cdd=28.6fF and Cdg=28.4Ff and Cjd=36Ff C,inmixer=50fF
C_out =143fF
Need to LD =6nH but spiral inductor achieve maximum inductance equals to 4nH and its parallel
capacitance about 20fF, so we need to add parallel capacitance its value calculated from equation (2).
C_add=70fF
Calculating Radd
Without adding Radd we get gain equals to 29dB but IIP,3 equals to -13dBm so we need to add parallel
resistance to reduce gain and increase IIP,3. Iterate over range of resistance to chose suitable value to IIP,3.
You must take into consideration that resistance consume area and increase noise figure.

𝑅𝑎𝑑𝑑 = 700𝑂ℎ𝑚𝑠

Parameter Value
W_input pair 140um
W_cascode 140um
ID 1mA
C_add 70fF
R_add 700 ohms

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3.2.4 Result
Gain
We had get high gain as we expect to get .we can control this gain by changing value of output resistance
as gain directly proportional to output resistance.
Gain calculation is achieved by using DC and ac analysis by setting AC amplitude of input port 1V and
calculating output voltage in dB. And show result as in fig.

S11
S11 represent reflection coefficient. It must be very low as this mean that circuit is well matched and
reflected power is very low.
S11 calculation is achieved by DC and PS analysis and selecting input port then from result select direct
plot then main form then PS then S11 as shown in fig.

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 Noise figure
It represents signal to noise ratio in input to signal to noise ratio in output and how much noise is added?
Noise figure calculation is done by noise analysis as shown in fig.

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 P,1Db Compression Point
It represents the input power at which gain is less than linear gain by 1dB. It must be high to avoid
saturation.
Calculation is done by using PSS analysis and sweep over range of input power as shown in fig.

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 IIP,3
It represent value of input power at which linear and third order output intersect .
Calculation using PSS and Pac analysis and enter center frequency and single point frequency which s near
to center frequency as shown in fig.

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Parameter Value
Gain 23dB
S11 -20dB
NF 2.5dB
P,1dB -15.4dBm
IIP,3 -4dBm
Power 1.1mW
Area 70891 um^2

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3.2.6 Enhancement
CMOS technology is a planar process, in which on different layers are laid on surface of the silicon chip.
Implementation of passive components particularly inductors is inconvenient. The performance is limited
by losses and parasitic. As inductance increases with increasing diameter and number of turns ,so we pay
large silicon area. So that needing to implement active inductors is very important it uses gyrator concept
which achieve inductance from certain input.

3.2.6.1 Active inductors

Active inductors are achieved by gyrators .gyrators are tow back to back trans conductors. When one port
connected to capacitor network called gyrator-c .as input and output are finite system called lossy.

3.2.6.2 resistive feedback active inductor

There different topologies to implement active inductor with different tradeoffs, here we will discuss
resistive feed back topology as it is simple and consume lower power. Resistance is a linear element and
leads to increasing parallel resistance which leads to increasing quality factor.
𝑅𝑝
𝑄=
𝜔𝐿

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 𝒈𝒎𝟒 𝒈𝒎𝟑(𝟏 + 𝑹𝒇 𝒈𝒅𝒔𝟒)
𝑸=√
(𝒈𝒅𝒔)^𝟐𝑪𝒈𝒔𝟒

𝑪𝒈𝒔𝟑(𝟏 + 𝑹𝒇𝒈𝒅𝒔𝟒)
𝑳=
𝒈𝒎𝟒 𝒈𝒎𝟑
𝒈𝒎𝟒 𝒈𝒎𝟑
𝒘=
𝑪𝒈𝒔𝟑𝑪𝒈𝒔𝟒(𝟏 + 𝑹𝒇𝒈𝒅𝒔𝟒)

References
1. Nguyen, Trung-Kien & Kim, Chung-Hwan & Ihm, Gook-Ju & Yang, Moon-Su & Lee, Sang-Gug.
(2004). CMOS Low-Noise Amplifier Design Optimization Techniques. Microwave Theory and
Techniques, IEEE Transactions on. 52. 1433 - 1442. 10.1109/TMTT.2004.827014.
2. Li, Xiaoyong. (2021). Low noise design techniques for radio frequency integrated circuits.
3. Idris, M. &
Yusop, Norbayah & Chachuli, Siti & Ismail, Mohd & Arith, Faiz & Shafie, N.. (2014). Design and analysis
of low noise amplifier using cadence. Journal of Theoretical and Applied Information Technology. 69.
151-160.
4. Kusuma ,
S.Shanthala and Cyril Prasanna Raj,(2018),Design Of Common Source Low Noise Amplifier With
Inductive Source Degeneration In Deep Submicron Cmos Process.

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