NCP13992

High Performance Current

Mode Resonant Controller
with Integrated High-
Voltage Drivers
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The NCP13992 is a high performance current mode controller for
half bridge resonant converters. This controller implements 600 V
gate drivers, simplifying layout and reducing external component
count. The built−in Brown−Out input function eases implementation 16
of the controller in all applications. In applications where a PFC front 1
stage is needed, the NCP13992 features a dedicated output to drive the SOIC−16 NB
PFC controller. This feature together with quiet skip mode technique (LESS PINS 2 AND 13)
further improves light load efficiency of the whole application. The D SUFFIX
NCP13992 provides a suite of protection features allowing safe CASE 751DU
operation in any application. This includes: overload protection,
over−current protection to prevent hard switching cycles, brown−out
MARKING DIAGRAM
detection, open optocoupler detection, automatic dead−time adjust,
over−voltage (OVP) and over−temperature (OTP) protections. 16
NCP13992xy
Features AWLYWWG
• High−Frequency Operation from 20 kHz up to 750 kHz
1
• Current Mode Control Scheme
NCP13992 = Specific Device Code
• Automatic Dead−time with Maximum Dead−time Clamp
x =A
• Dedicated Startup Sequence for Fast Resonant Tank Stabilization y = A, B, C, E
• Light Load Operation Mode for Improved Efficiency A = Assembly Location
WL = Wafer Lot
• Quiet Skip Operation Mode for Minimize Transformer Acoustic Noise Y = Year
• Latched or Auto−Recovery Overload Protection WW = Work Week
G = Pb−Free Package
• Latched or Auto−Recovery Output Short Circuit Protection
• Latched Input for Severe Fault Conditions, e.g. OVP or OTP
• Out of Resonance Switching Protection PIN CONNECTIONS
• Open Feedback Loop Protection
HV 1 16 VBOOT
• Precise Brown−out Protection
15 HB
• PFC Stage Operation Control According to Load Conditions
VBULK/PFCFB 3 14 MUPPER
• Startup Current Source with Extremely Low Leakage Current
SKIP 4
• Dynamic Self−Supply (DSS) Operation in Off−mode or Fault Modes
LLCFB 5 12 MLOWER
• Pin to Adjacent Pin / Open Pin Fail Safe
LLCCS 6 11 GND
• These are Pb−Free Devices
OVP/OTP 7 10 VCC
Typical Applications FBFREEZE 8 9 PFCMODE
• Adapters and Offline Battery Chargers
(Top View)
• Flat Panel Display Power Converters
• Computing Power Supplies
ORDERING INFORMATION
• Industrial and Medical Power Sources
See detailed ordering and shipping information on page 9 of
this data sheet.

© Semiconductor Components Industries, LLC, 2018 1 Publication Order Number:

March, 2019 − Rev. 3 NCP13992/D
 NCP13992

Figure 1. Typical Application Example without PFC Stage − WLLC Design

Figure 2. Typical Application Example with PFC Stage

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 NCP13992

PIN FUNCTION DESCRIPTION

Pin No. Pin Name Function Pin Description
1 HV High−voltage startup Connects to rectified AC line or to bulk capacitor to perform functions of Start−
current source input up Current Source and Dynamic Self−Supply

2 NC Not connected Increases the creepage distance

3 VBULK / Bulk voltage monitoring input Receives divided bulk voltage to perform Brown−out protection.
PFC FB

4 SKIP Skip threshold adjust Sets the skip in threshold via a resistor connected to ground
5 LLC FB LLC feedback input Defines operating frequency based on given load conditions. Activates skip
mode operation under light load conditions.

6 LLC CS LLC current sense input Senses divided resonant capacitor voltage to perform on−time modulation, out
of resonant switching protection, over−current protection and secondary side
short circuit protection.
7 OTP / OVP Over−temperature and Implements over−temperature and over−voltage protection on single pin.
over−voltage protection input

8 FB FREEZE Minimum internal FB level Adjusts minimum internal FB level that can be reached during light load oper-
ation.

9 PFC MODE PFC and external HV Provides supply voltage for PFC front stage controller and/or enables Vbulk
switch control output sensing network HV switch.

10 VCC Supplies the controller The controller accepts up to 20 V on VCC pin

11 GND Analog ground Common ground connection for adjust components, sensing networks and
DRV outputs.

12 MLOWER Low side driver output Drives the lower side MOSFET
13 NC Not connected Increases the creepage distance
14 MUPPER High side driver output Drives the higher side MOSFET
15 HB Half−bridge connection Connects to the half−bridge output.
16 VBOOT Bootstrap pin The floating VCC supply for the upper stage

Figure 3. Internal Circuit Architecture

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 NCP13992

MAXIMUM RATINGS
Rating Symbol Value Unit
HV Startup Current Source HV Pin Voltage (Pin 1) VHV −0.3 to 600 V
VBULK/PFC FB Pin Voltage (Pin3) VBULK/PFC FB −0.3 to 5.5 V
SKIP Pin Voltage (Pin 4) VSKIP −0.3 to 5.5 V
LLC FB Pin Voltage (Pin 5) VFB −0.3 to 5.5 V
LLC CS Pin Voltage (Pin 6) VCS −5 to 5 V
PFC MODE Pin Output Voltage (Pin 9) VPFC MODE −0.3 to VCC+0.3 V
VCC Pin Voltage (Pin 10) VCC −0.3 to 20 V
Low Side Driver Output Voltage (Pin 12) VDRV_MLOWER −0.3 to VCC + 0.3 V
High Side Driver Output Voltage (Pin 14) VDRV_MUPPER VHB – 0.3 to VBOOT + 0.3 V
High Side Offset Voltage (Pin 15) VHB VBoot −20 to VBoot +0.3 V
High Side Floating Supply Voltage (Pin 16) VBOOT −0.3 to 620 V
High Side Floating Supply Voltage (Pin 15 and 16) VBoot–VHB −0.3 to 20.0 V
Allowable Output Slew Rate on HB Pin (Pin 15) dV/dtmax 50 V/ns
OVP/OTP Pin Voltage (Pin 7) VOVP/OTP −0.3 to 5.5 V
FB FREEZE Pin Voltage (Pin 8) VP ON/OFF −0.3 to 5.5 V
Junction Temperature TJ −50 to 150 °C
Storage Temperature TSTG −55 to 150 °C
Thermal Resistance Junction−to−air RθJA 130 °C/W
Human Body Model ESD Capability per JEDEC JESD22−A114F − 4.5 kV
(except HV Pin – Pin 1)

Machine Model ESD Capability per JEDEC JESD22−A115C − 250 V

Charged−Device Model ESD Capability per JEDEC JESD22−C101E − 1 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78

ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
HV STARTUP CURRENT SOURCE
VHV_MIN1 Minimum voltage for current source operation 1 − − 60 V
(VCC = VCC_ON −0.5 V, ISTART2 drops to 95%)

VHV_MIN2 Minimum voltage for current source operation 1 − − 60 V

(VCC = VCC_ON −0.5 V, ISTART2 drops to 5 mA)

ISTART1 Current flowing out of VCC pin (VCC = 0 V) 1, 10 0.2 0.5 0.8 mA
ISTART2 Current flowing out of VCC pin (VCC = VCC_ON −0.5 V) 1, 10 6 9 13 mA
ISTART_OFF Off−state leakage current (VHV = 500 V, VCC = 15 V) 1 − − 10 mA
SUPPLY SECTION
VCC_ON Turn−on threshold level, VCC going up 10 V
(NCP13992AA, AC, AE) 15.3 15.8 16.3
(NCP13992AB) 11.5 11.9 12.3
VCC_OFF Minimum operating voltage after turn−on 10 9.0 9.5 10 V
VCC_RESET VCC level at which the internal logic gets reset 10 5.8 6.6 7.2 V
VCC_INHIBIT VCC level for ISTART1 to ISTART2 transition 10 0.40 0.80 1.25 V

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 NCP13992

ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
SUPPLY SECTION
ICC_SKIP−MODE Controller supply current in skip−mode, VCC = 15 V, 10, 11 mA
OVP/OTP block debiased during skip mode
(NCP13992AA, AE) 500 780 950
(NCP13992AB) 550 850 1100
(NCP13992AC) 600 850 1100
ICC_LATCH Controller supply current in latch−off mode, 10, 11 mA
VCC = VCC_ON − 0.2 V (NCP13992AA, AC, AE) 350 570 700
(NCP13992AB) − 670 1100
ICC_AUTOREC Controller supply current in auto−recovery mode, 10, 11 mA
VCC = VCC_ON − 0.2 V (NCP13992AA, AC, AE) 400 580 700
(NCP13992AB) − 670 1100
ICC_OPERATION Controller supply current in normal operation, 10, 11 4.0 5.4 7.0 mA
fsw = 100 kHz, Cload = 1 nF, VCC = 15 V

BOOTSTRAP SECTION
VBOOT_ON Startup voltage on the floating section (Note 3) 16, 15 7.5 9.0 10.0 V
VBOOT_OFF Cutoff voltage on the floating section 16, 15 7.0 8.2 9.1 V
IBOOT1 Upper driver consumption, no DRV pulses 16, 15 30 75 130 mA
IBOOT2 Upper driver consumption, Cload = 1 nF between Pins 13 & 16, 15 1.30 1.65 2.00 mA
15 fsw = 100 kHz, HB connected to GND

HB DISCHARGER
IDISCHARGE1 HB sink current capability VHB = 30 V 15 7 9.6 12 mA
IDISCHARGE2 HB sink current capability VHB = VHB_MIN 15 1 4.1 8 mA
VHB_MIN HB voltage @ IDISCHARGE changes from 2 to 0 mA 15 − − 10 V
DRIVER OUTPUTS
tr Output voltage rise−time @ CL = 1 nF, 10−90% of output 12, 14 20 45 80 ns
signal

tf Output voltage fall−time @ CL = 1 nF, 10−90% of output 12, 14 5 30 50 ns

signal

ROH Source resistance 12, 14 4 16 32 W

ROL Sink resistance 12, 14 1 5 11 W
IDRVSOURCE Output high short circuit pulsed current 12, 14 − 0.5 − A
VDRV = 0 V, PW v 10 ms
IDRVSINK Output high short circuit pulsed current 12, 14 − 1 − A
VDRV = VCC, PW v 10 ms
IHV_LEAK Leakage current on high voltage pins to GND 14, 15, 16 − − 5 mA
DEAD−TIME GENERATION
tDEAD_TIME_MAX Maximum Dead−time value if no dV/dt falling/rising edge is 12, 14 ns
received (NCP13992AA, AC, AE) 720 800 880
(NCP13992AB) 120 190 295
NDT_MAX Number of DT_MAX events to enters IC into fault 12, 14, 16 −
(NCP13992AC) − 16 −

dV/dt DETECTOR
PdV/dt_th_1 Positive slew rate on VBOOT pin above which is dV/dt_P 16 − 178 200 V/ms
sensor triggered, VHB rising from 0 to 100 V linearly (Note 2)

PdV/dt_th_2 Positive slew rate on VBOOT pin above which is dV/dt_P 16 − 226 250 V/ms
sensor triggered, VHB rising from 100 to 200 V linearly
(Note 2)

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 NCP13992

ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
dV/dt DETECTOR
PdV/dt_th_3 Positive slew rate on VBOOT pin above which is dV/dt_P 16 − 246 280 V/ms
sensor triggered, VHB rising from 200 to 400 V linearly
(Note 2)
NdV/dt_th_1 Negative slew rate on VBOOT pin above which is dV/dt_N 16 − 163 − V/ms
sensor triggered, VHB falling from 100 to 0 V linearly

NdV/dt_th_2 Negative slew rate on VBOOT pin above which is dV/dt_N 16 − 290 − V/ms
sensor triggered, VHB falling from 200 to 100 V linearly

NdV/dt_th_3 Negative slew rate on VBOOT pin above which is dV/dt_N 16 − 250 − V/ms
sensor triggered, VHB falling from 400 to 200 V linearly

PFC MODE OUTPUT AND P ON/OFF ADJUST

VPFC_M_OFF PFC MODE output voltage when application enters skip 9 − − 0.1 V
mode (inject 1 mA into the PFC MODE output)

VPFC_M_BO PFC MODE output voltage when VFB < VP ON/OFF 9 5.75 6.00 6.25 V
(sink 1 mA current from PFC MODE output)

VPFC_M_ON PFC MODE output voltage when VFB > VP ON/OFF 9 VCC − − − V
(sink 20 mA current from PFC MODE output) 0.4

IPFC_M_LIM PFC MODE output current limit (VPFC MODE < 2 V) 9 0.7 1.2 1.85 mA
OVP/OTP
VOVP OVP threshold voltage (VOVP/OTP going up) 7 2.35 2.50 2.65 V
VOTP OTP threshold voltage (VOVP/OTP going down) 7 0.76 0.80 0.84 V
IOTP OTP/OVP pin source current for external NTC – during 7 90 95 100 mA
normal operation

IOTP_BOOST OTP/OVP pin source current for external NTC – during 7 180 190 200 mA
startup

tOVP_FILTER Internal filter for OVP comparator 7 32 37 44 ms

tOTP_FILTER Internal filter for OTP comparator 7 200 330 500 ms
tBLANK_OTP Blanking time for OTP input during startup 7 14 16 18 ms
VCLAMP_OVP/OTP_1 OVP/OTP pin clamping voltage @ IOVP/OTP = 0 mA 7 1.0 1.2 1.4 V
VCLAMP_OVP/OTP_2 OVP/OTP pin clamping voltage @ IOVP/OTP = 1 mA 7 1.8 2.4 3.0 V
START−UP SEQUENCE PARAMETERS
t1st_MLOWER_TON Initial Mlower DRV on−time duration 12 4.7 4.9 5.4 ms
t1st_MUPPER_TON Initial Mupper DRV on−time duration 14 ms
(NCP13992AA, AC, AE) 0.72 0.79 0.88
(NCP13992AB) 0.15 0.20 0.25
tSS_INCREMENT On−time period increment during soft−start 12, 14 17 20 22 ns
KSS_INCREMENT Soft−Start increment division ratio (NCP13992AA) 12, 14 − 4 − −
(NCP13992AB, AC) − 8 −
(NCP13992AE) − 2 −
tWATCHDOG Time duration to restart IC if start−up phase is not finished 12, 14 ms
(NCP13992AA, AC, AE) 0.45 0.50 0.55
(NCP13992AB) 1.80 2.00 2.20
FEEDBACK SECTION
RFB Internal pull−up resistor on FB pin 5 15 18 25 kW
KFB VFB to internal current set point division ratio 5 1.92 2.00 2.08 −
VFB_REF Internal voltage reference on the FB pin 5 4.60 4.95 5.30 V
VFB_CLAMP Internal clamp on FB input of On−time comparator referred 5 4.4 4.6 4.8 V
to external FB pin voltage

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 NCP13992

ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
FEEDBACK SECTION
VFB_SKIP_HYST Skip comparator hysteresis (NCP13992AA, AC) 5 148 174 222 mV
(NCP13992AB) 295 350 410
(NCP13992AE) 1 25 45
VFB_LL_IN Feedback voltage thresholds to enter Light load mode 5 V
(NCP13992AA, AC) 0.468 0.508 0.548
(NCP13992AE) 0.658 0.713 0.768
VFB_LL_OUT Feedback voltage thresholds to exit Light load mode, 5 V
(NCP13992AA, AC) 0.595 0.635 0.675
(NCP13992AE) 1.045 1.100 1.155
t1st_MLOWER_SKIP On−time duration of 1st Mlower pulse when FB cross 5, 12 ms
VFB_SKIP_IN + VFB_SKIP_HYST threshold (NCP13992AA, AE) 0.95 1.05 1.15
(NCP13992AB) 1.08 1.20 1.32
(NCP13992AC) 1.7 1.9 2.1
V1st_MUPPER_SKIP Internal FB level reduction during 1st Mupper pulse when 5, 6, 14 mV
FB cross VFB_SKIP_IN + VFB_SKIP_HYST threshold (Note 2)
(NCP13992AA, AC, AE) − 150 −
(NCP13992AB) − 100 −
SKIP INPUT
ISKIP Internal Skip pin current source 4 48 50 52 mA
CSKIP_LOAD_MAX Maximum loading capacitance for skip pin voltage filtering 4 − − 10 nF
(Note 2)

QUIET−SKIP PARAMETERS (EXCEPT NCP13992AB)

tLAST_ML_PATTERN The portion of previous MU on−time that is place for last ML 12 − 50 − %
pulse in pattern

tLAST_ML_SKIP The portion of previous MU on−time that is place for last ML 12 − 50 − %

pulse before the LL or skip mode is activated

tGEAR_UP Skip burst off−time duration that is needed to increase num- 12, 14 − 5 − ms
ber of skipped valleys between following patterns

tGEAR_DOWN Skip burst on−time duration that is needed to decrease 12, 14 − 15 − ms

number of skipped valleys between following patterns

tVALLEY_WD Time duration to force valley count logic if valley is not de- 12, 14 4.5 5 5.5 ms
tected

tQS_timer Quiet Timer duration (NCP13992AA, AC) 12, 14 − 5 − ms

(NCP13992AE) − 0.125 −

NQS_1/4 Number of patterns adjustment when bust period is shorter 12, 14 − 2 − −

than ¼ of QS_timer duration
NQS_2/4 Number of patterns adjustment when bust period is longer 12, 14 − 1 − −
than ¼ and shorter than 2/4 of QS_timer duration
NQS_3/4 Number of patterns adjustment when bust period is longer 12, 14 − 0 − −
than 2/4 and shorter than 3/4 of QS_timer duration

NQS_4/4 Number of patterns adjustment when bust period is longer 12, 14 − 0 − −

than 3/4 and shorter than 4/4 of QS_timer duration

NQS_INF Number of patterns adjustment when bust period is longer 12, 14 −

than QS_timer duration (NCP13992AA, AC) − −1 −
(NCP13992AE) − −3 −
NPATTERN_INIT Initial number of patterns placed when LL or skip mode is 12, 14 − 1 − −
activated

NLL_blank Number of MU pulses during which FB_LL_IN cmp is 14 − 60 − −

blanked once VFB > VFB_LL_OUT

FB FREEZE INPUT
IFB_Freeze FB Freeze pin current source 4 18 20 22 mA

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 NCP13992

ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
FB FREEZE INPUT
CFB_Freeze_LOAD_MAX Maximum loading capacitance for FB Freeze pin voltage 4 − − 10 nF
filtering (Note 2)

CURRENT SENSE INPUT SECTION

tpd_CS On−time comparator delay to Mupper driver turn off 5, 6 − − 250 ns
VFB = 2.5 V, VCS goes up from –2.5 V to 2.5 V with rising
edge of 100 ns
ICS_LEAKAGE Current sense input leakage current for VCS = ± 3 V 6 − − ±1 mA
VCS_OFFSET Current sense input offset voltage (NCP13992AA, AC) 6 160 200 240 mV
(NCP13992AB) 110 150 190
(NCP13992AE) 60 100 140
tLEB Leading edge blanking time of the on−time comparator 5, 6, 14 360 440 540 ns
output

LFFGAIN Line Feed Forward current source transconductance 3, 6 mA/V

(VVBULK/PFC_FB > VBO) (NCP13992AA, AC, AE) − 0 −
(NCP13992AB) − 480 −
FAULTS AND AUTO−RECOVERY TIMER
tTON_MAX Maximum on−time clamp (NCP13992AA, AE) 12, 14 7.3 7.7 8.4 ms
(NCP13992AB) 2.5 2.7 2.9
(NCP13992AC) 10.4 11.1 11.9
NTON_MAX_COUNTER Number of TON_MAX events to confirm fault 12,14 − 1 − −
tFB_FAULT_TIMER FB fault timer duration (NCP13992AA, AE) − 160 200 240 ms
(NCP13992AB, AC) 80 100 120

VFB_FAULT FB voltage when FB fault is detected 5 4.5 4.7 4.9 V

NCS_FAULT_COUNTER Number of CS_fault cmp. pulses to confirm CS fault − − 5 − −
(except NCP13992AB)

VCS_FAULT CS voltage when CS fault is detected 6 2.5 2.7 2.9 V

(except NCP13992AB)

tA−REC_TIMER Auto−recovery duration (common timer for all fault condition) − 0.8 1 1.2 s
BROWN−OUT PROTECTION
VBO Brown−out turn−off threshold 3 0.965 1.000 1.035 V
IBO Brown−out hysteresis current, VVBULK/PFC_FB < VBO 3 4.1 5.0 5.7 mA
VBO_HYST Brown−Out comparator hysteresis 3 5 12 25 mV
IBO_BIAS Brown−Out input bias current 3 − − 0.05 mA
tBO_FILTR BO filter duration 3 10 20 30 ms
RAMP COMPENSATION
RCGAIN Ramp compensation gain − 58 82 108 mV/ms
tRC_SHIFT Ramp compensation time shift − − 0.4 − ms
TEMPERATURE SHUTDOWN PROTECTION
TTSD Temperature shutdown TJ going up (NCP13992AA, AB, AE) − − 124 − °C
(NCP13992AC) − 137 −

TTSD_HYST Temperature shutdown hysteresis − − 30 − °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design.
3. Minimal resistance connected in series with bootstrap diode is 3.3 W

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 NCP13992

IC OPTIONS
Cumulative OVP/OTP
FB fault FB fault timer/ bias during
Option FB fault source counter CS_FAULT TON_MAX OVP OTP skip
NCP13992AA Auto−recovery Timer NO Auto−recovery Auto−recovery Latch Auto−recovery OFF
NCP13992AB Auto−recovery Timer NO OFF OFF Auto−recovery Auto−recovery OFF
NCP13992AC Auto−recovery Timer NO Auto−recovery OFF Latch Latch OFF
NCP13992AE Auto−recovery Timer NO Auto−recovery Auto−recovery Latch Auto−recovery OFF

Dedicated
PFC_MODE Dead time Ramp comp Soft_start_-
Option skip status Skip mode control Dead time fault BO status status seq
NCP13992AA OFF Quiet Skip ZVS or DT_max OFF ON Without ramp ON
shift

NCP13992AB OFF Standard Skip ZVS or DT_max OFF ON Without ramp ON

shift

NCP13992AC ON Quiet Skip ZVS or DT_max Auto−recovery ON Without ramp ON

shift

NCP13992AE OFF Quiet Skip ZVS or DT_max OFF ON Without ramp ON

shift

ORDERING INFORMATION
Device Package Marking Package Shipping†
NCP13992AADR2G NCP13992AA
NCP13992ABDR2G NCP13992AB
SOIC−16, Less Pin 2 and 13 (Pb−free) 2500 / Tape & Reel
NCP13992ACDR2G NCP13992AC
NCP13992AEDR2G NCP13992AE
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 NCP13992

VCC Management with High−voltage Startup Current over−temperature protection to prevent IC damage for any
Source failure mode that may occur in the application. The HV
The NCP13992 controller features a HV startup current startup current source is primarily enabled or disabled based
source that allows fast startup time and extremely low on VCC level. The startup HV current source can be also
standby power consumption. Two startup current levels enabled by BO_OK rising edge, auto−recovery timer end
(Istart1 and Istart2) are provided by the system for safety in and TSD end event. The HV startup current source charges
case of short circuit between VCC and GND pins. In the VCC capacitor before IC start−up.
addition, the HV startup current source features a dedicated

Figure 4. Internal Connection of the VCC Management Block

The NCP13992 controller disables the HV startup current when the die temperature reaches 130°C. At this
source once the VCC pin voltage level reaches VCC_ON temperature, Istart2 will be progressively to prevent the die
threshold – refer to Figure 4. The application then starts temperature from rising above 130°C.
operation and the auxiliary winding maintains the voltage
bias for the controller during normal and skip−mode Brown−out Protection − VBULK/PFC FB Input
operating modes. The IC operates in so called Dynamic Self Resonant tank of an LLC converter is always designed to
Supply (DSS) mode when the bias from auxiliary winding operate within a specific bulk voltage range. Operation
is not sufficient to keep the VCC voltage above VCC_OFF below minimum bulk voltage level would result in current
threshold (i.e. VCC voltage is cycling between VCC_ON and and temperature overstress of the converter power stage.
VCC_OFF thresholds with no driver pulses on the output The NCP13992 controller features a VBULK/PFC FB input
during positive VCC ramp). Please refer to Figure 23 through in order to precisely adjust the bulk voltage turn−ON and
Figure 25 to find an illustration of the NCP13992 VCC turn−OFF levels. This Brown−Out protection (BO) greatly
management system under all operating conditions/modes. simplifies application level design.
The HV startup current source features an independent
over–temperature protection system to limit Istart2 current

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 NCP13992

Figure 5. Internal Connection of the Brown−out Protection Block

The internal circuitry shown in Figure 5 allows V bulk_OFF * V BO

monitoring the high−voltage input rail (Vbulk). A R upper + R lower @ (eq. 4)
V BO
high−impedance resistive divider made of Rupper and Rlower
resistors brings a portion of the Vbulk rail to the Note that the VBULK/PFC FB pin is pulled down by an
VBULK/PFC FB pin. The Current sink (IBO) is active below internal switch when the controller is in startup phase − i.e.
the bulk voltage turn−on level (Vbulk_ON). Therefore, the when the VCC voltage ramps up from VCC < VCC_RESET
bulk voltage turn−on level is higher than defined by the towards the VCC_ON level on the VCC pin. This feature
division ratio of the resistive divider. To the contrary, when assures that the VBULK/PFC FB pin voltage will not ramp
the internal BO_OK signal is high, i.e. the application is up before the IC operation starts. The IBO hysteresis current
running, the IBO sink is disabled. The bulk voltage turn−off sink is activated and BO discharge switch is disabled once
threshold (Vbulk_OFF) is then given by BO comparator the VCC voltage crosses VCC_ON threshold. The
reference voltage directly on the resistor divider. The VBULK/PFC FB pin voltage then ramps up naturally
advantage of this solution is that the Vbulk_OFF threshold according to the BO divider information. The BO
precision is not affected by IBO hysteresis current sink comparator then authorizes or disables the LLC stage
tolerance. operation based on the actual Vbulk level.
The Vbulk_ON and Vbulk_OFF levels can be calculated The low IBO hysteresis current of the NCP13992 brown
using equations below: out protection system allows increasing the bulk voltage
The IBO is ON: divider resistance and thus reduces the application power
(eq. 1)
consumption during light load operation. On the other hand,
V BO ) V BOhyst +
the high impedance divider can be noise sensitive due to
V bulk_ON @
R lower
R lower ) R upper
* I BO @ ǒ Ǔ
R lower @ R upper
R lower ) R upper
capacitive coupling to HV switching traces in the
application. This is why a filter (tBO_FILTR) is added after the
BO comparator in order to increase the system noise
The IBO is OFF: immunity. Despite the internal filtering, it is also
R lower recommended to keep a good layout for BO divider resistors
V BO + V bulk_OFF @ (eq. 2)
R lower ) R upper and use a small external filtering capacitor on the
VBULK/PFC pin if precise BO detection wants to be
One can extract Rlower term from equation 2 and use it in achieved.
equation 1 to get needed Rupper value: The bulk voltage HV divider can be also used by a PFC
Vbulk_ON@VBO front stage controller as a feedback sensing network (refer
* V BO * V BOhyst
V bulk_OFF again to Figure 5). The shared bulk voltage resistor divider
R lower + (eq. 3) between PFC and LLC stage offers a way how to further
ǒ
I BO @ 1 *
VBO
Vbulk_OFF
Ǔ reduce power losses during no−load operation. The
NCP13992 features a PFC MODE pin that disconnects bias

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 NCP13992

of the PFC stage during light load or fault mode operation. The controller is allowed to run when OVP/OTP input
This technique further reduces the no−load power voltage is within this working window. The controller stops
consumption down again since the power losses of voltage the operation, after filter time delay, when the OVP/OTP
divider are not affected by the bulk voltage at all. input voltage is out of the no−fault window. The controller
Please refer to Figure 23 through Figure 25 for an then either latches−off or or starts an auto−recovery timer −
illustration of NCP13992 Brown−out protection system in depending on the IC version − and triggered the protection
all operating conditions/modes. threshold (VOTP or VOVP).
The VBULK/PFC FB pin voltage is also used by Line The internal current source IOTP allows a simple OTP
Feed Forward block (LFF). Please refer to ON−time implementation by using a single negative temperature
modulation and feedback loop block description for more coefficient (NTC) thermistor. An active soft clamp
information about LFF function. composed from Vclamp and Rclamp components prevents the
OVP/OTP pin voltage from reaching the VOVP threshold
Over−voltage and Over−temperature Protection when the pin is pulled up by the IOTP current. An external
The OVP/OTP pin is a dedicated input to allow for a pull*up current, higher than the pull*down capability of
simple and cost effective implementation of two key the internal clamp (VCLAMP_OVP/OTP), has to be applied to
protection features that are needed in adapter applications: pull the OVP/OTP pin above VOVP threshold to activate the
over−voltage (OVP) and over−temperature (OTP) OVP protection. The tOVP_FILTER and tOTP_FILTER filters
protections. Both of these protections can be either latched are implemented in the system to avoid any false triggering
or auto−recovery– depending on the version of NCP13992. of the protections due to application noise and/or poor
The OVP/OTP pin has two voltage threshold levels of layout.
detection (VOVP and VOTP) that define a no−fault window.

Figure 6. Internal Connection of OVP/OTP Input

The OTP protection could be falsely triggered during • VCC falls below VCC_OFF threshold
controller startup due to the external filtering capacitor • BO OK signal goes to low state (i.e. Brown−out
charging current. Thus the tBLANK_OTP period has been condition occurs on the mains)
implemented in the system to overcome such behavior. The
• Fault signal is activated (Auto−recovery timer starts
OTP comparator output is ignored during tBLANK_OTP
counting or Latch fault is present)
period. In order to speed up the charging of the external
filtering capacitor COVP_OTP connected to OVP/OTP pin, • IC goes into the skip−mode operation (VFB_SKIP_IN
the IOTP current has been doubled to IOTP_BOOST. The threshold was reached)
maximum value of filtering capacitor is 100 nF. IC option that keeps OVP/OTP block working during skip
The OVP/OTP ON signal is set after the following events: mode is also available. The IC consumption is increased for
• the VCC voltage exceeds the VCC_ON threshold during this version by OVP/OTP block bias.
The latched OVP or OTP versions of NCP13992 enters
first start−up phase (after VCC pin voltage was below
latched protection mode when VCC voltage cycles between
VCC_RESET threshold)
VCC_ON and VCC_OFF thresholds and no pulses are provided
• BO OK signal is received from BO block by drivers. The controller VCC pin voltage has to be cycled
• Auto−recovery timer elapsed and a new restart occurs down below VCC_RESET threshold in order to restart
• IC returns to operation from skip−mode (VFB_SKIP_IN + operation. This would happen when the power supply is
VFB_SKIP_HYST threshold was reached) unplugged from the mains.
The IOTP current source is disabled when:

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 NCP13992

PFC MODE Output 1st to control the external small signal HV MOSFET switch
The NCP13992 has PFC MODE pin that can be used to that connects the bulk voltage divider to the VBULK/PFC
disable or enable PFC stage operation based on actual FB input
application operating state – please refer to Figure 7. The 2nd to control the PFC front stage controller operation via
PFC MODE output pin can be used for two purposes: PFC controller supply pin

Figure 7. Internal Connection of the PFC MODE Block

There are two possible states of the PFC MODE output ON−time Modulation and Feedback Loop Block
that can be placed by the controller based on the application Frequency modulation of today’s commercially available
operating conditions: resonant mode controllers is based on the output voltage
a) The PFC MODE output pin is pulled−down by an internal regulator feedback only. The feedback voltage (or current)
MOSFET switch before controller startup. This technique of output regulator drives voltage (or current) controlled
ensures minimum VCC pin current consumption in order to oscillator (VCO or CCO) in the controller. This method
ramp VCC voltage in a short time from the HV startup presents three main disadvantages:
current source. This approach speeds up the startup and 1st − The 2nd order pole is present in small signal gain−phase
restart time of an SMPS. The PFC MODE output pin is also characteristics => the lower cross over frequency and worse
pulled−down in protection mode during which the HV transient response is imposed by the system when voltage
startup current source is operated in DSS mode. Application mode control is used. There is no direct link to the actual
power consumption is reduced in both above cases. primary current – i.e. no line feed forward mechanism which
b) The pull−down switch is disabled and controller connects results in poor line transient response.
VCC pin voltage to PFC MODE output with minimum 2nd – Precise VCO (or CCO) is needed to assure frequency
dropout (VPFC_M_ON). modulation with good reproducibility, fmin and fmax clamps
The PFC MODE pin output current is limited when the need to be adjusted for each design => need for an
VCC to PFC MODE bypass switch is activated. The current adjustment pin(s).
limitation avoids bypass switch damage during PFC VCC 3rd – Dedicated overload protection system, requiring an
decoupling capacitor charging process or short circuit. A additional pin, is needed to assure application safety during
minimum value PFC VCC decoupling capacitance should overload and/or secondary short circuit events.
be used in order to speed up PFC stage startup after it is The NCP13992 resolves all disadvantages mentioned
enabled by the NCP13992 controller. above by implementing a current mode control scheme that
Please refer to Figure 23 through Figure 25 for an ensures best transient response performance and provides
illustration of NCP13992 PFC operation control. inherent cycle−by−cycle over−current protection feature in
the same time. The current mode control principle used in
this device can be seen in Figure 8.

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 NCP13992

Figure 8. Internal Connection of the NCP13992 Current Mode Control Scheme

The basic principle of current mode control scheme detection – please refer to chapter dedicated to short circuit
implementation lies in the use of an ON−time comparator protection.
that defines upper switch on−time by comparing voltage The second input signal for the on−time comparator is
ramp, derived from the current sense input voltage, to the derived from the FB pin voltage. This internal FB pin signal
divided feedback pin voltage. The upper switch on−time is is also used for the following purposes: skip mode operation
then re−used for low side switch conduction period. The detection, PFC MODE control and overload / open FB pin
switching frequency is thus defined by the actual primary fault detection. The detailed description of these functions
current and output load conditions. Digital processing with can be found in each dedicated chapters. The internal
10 ns minimum on−time resolution is implemented to pull−up resistor assures that the FB pin voltage increases
ensure high noise immunity. The ON−time comparator when the optocoupler LED becomes less biased – i.e. when
output is blanked by the leading edge blanking (tLEB) after output load is increased. The higher FB pin voltage implies
the Mupper switch is turned−on. The ON−time comparator a higher reference level for on−time comparator i.e. longer
LEB period helps to avoid false triggering of the on−time Mupper switch on−time and thus also higher output power.
modulation due to noise generated by the HB pin voltage The FB pin features a precise voltage clamp which limits the
transition. internal FB signal during overload and startup. The FB pin
The voltage signal for current sense input is prepared signal passes through the FB processing block before it is
externally via natural primary current integration by the brought to the ON−time comparator input. The FB
resonant tank capacitor Cs. The resonant capacitor voltage processing block scales the FB signal down by a KFB ratio
is divided down by capacitive divider (Ccs1, Ccs2, Rcs1, in order to limit the CS input dynamic voltage range. The
Rcs2) before it is provided to the CS input. The capacitive scaled FB signal is then further processed by subtraction of
divider division ratio, which is fully externally adjustable, a ramp compensation generator signal in order to ensure
defines the maximum primary current level that is reached stability of the current mode control scheme. The divided
in case of maximum feedback voltage – i.e. the capacitive internal FB signal is overridden by a Soft−start generator
divider division ration defines the maximum output power output voltage during device starts−up.
of the converter for given bulk voltage. The CS is a bipolar The actual operating frequency of the converter is defined
input pin which an input voltage swing is restricted to ±5 V. based on the CS pin and FB pin input signals. The maximum
A fixed voltage offset is internally added to the CS pin signal output power of the converter, under given input voltage, is
in order to assure enough voltage margin for operation the limited by maximum internal FB voltage clamp that is
feedback optocoupler − the FB optocoupler saturation reached when optocoupler provides no current. The
voltage is ~ 0.15 V (depending on type). However, the CS maximum output power limit is bulk voltage dependent due
pin useful signal for frequency modulation swings from 0 V, to changing ratio between magnetizing and load primary
so current mode regulation would not work under light load current components. Line Feed Forward (LFF) system is
conditions if no offset would be added to the CS pin before implemented in the controller to compensate for maximum
it is stabilized to the level of the on−time comparator input. output power clamp variation. The ILFF current that flows
The CS pin signal is also used for secondary side short circuit out from the Cs pin is BO/PFC FB pin voltage proportional

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 NCP13992

and creates voltage offset on the resistor connected to the Cs only when BO pin voltage exceeds BO_OK threshold
pin. The higher input voltage, the higher drop is created on voltage.
external resistor. The Mupper switch on−time is thus Please refer to Figure 9 and below description for better
reduced for given maximum internal FB voltage clamp understanding of the NCP13992 frequency modulation
when input voltage increases. The ILFF current is provided system.

Figure 9. NCP13992 On−time Modulation Principle

The Mupper switch is activated by the controller after Overload and Open FB Protections
dead−time (DT) period lapses in point A. The frequency The overload protection and open FB pin detection are
processing block increments the ON−time counter with implemented via FB pin voltage monitoring in this
10 ns resolution until the internal CS signal crosses the controller. The FB fault comparator is triggered once the FB
internal FB set point for the ON−time comparator in point B. pin voltage reaches its maximum level and the VFB_FAULT
A DT period is then introduced by the controller to avoid any threshold is exceeded. The fault timer or counter (depending
shoot−through current through the power stage switches. on IC option) is then enabled – refer to Figure 10. The time
The DT period ends in point C and the controller activates period to the FB fault event confirmation is defined by the
the Mlower switch. The ON−time processing block preselected tFB_FAULT_TIMER parameter when the fault
decrements the ON_time counter down until it reaches zero. timer option is used. The FB fault counter, once selected as
The Mlower switch is then turned−OFF at point D and the a FB fault confirmation period source, defines the fault
DT period is started. This approach results in perfect duty confirmation period via Mupper DRV pulses counting. The
cycle symmetry for Mlower and Mupper switches. The FB fault confirmation time is thus dependent on switching
Mupper switch on−time naturally increases and the frequency. The fault timer/counter is reset once the FB fault
operating frequency drops when the FB pin voltage is condition diminishes. A digital noise filter has been added
increased, i.e. when higher current is delivered by the after the FB fault comparator to overcome false triggering of
converter output – sequence E. the FB fault timer/counter due to possible noise on the FB
The resonant capacitor voltage and thus also CS pin input. The noise filter has a period of 2 ms for FB fault
voltage can be out of balance in some cases – this is the case timer/counter activation and 20 µs for reset/deactivation to
during transition from full load to no−load operation when assure high noise immunity. A cumulative timer/counter IC
skip mode is not used or adjusted correctly. The current option is also available on request. The FB fault
mode operation is not possible in such case because the timer/counter is not reset when the FB fault condition
ON−time comparator output stays active for several diminishes in this case. The FB fault timer/counter is
switching cycles. Thus a special logic has been implemented disabled and memorizes the fault period information. The
in NCP13992 in order to repeat the last valid on−time until cumulative FB fault timer/counter integrates all the FB fault
the current mode operation recovers – i.e. until the CS pin events over the IC operation time. The Fault timer/counter
signal balance is restored by the system. can be reset via skip mode or VCC UVLO event.

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 NCP13992

Figure 10. Internal FB Fault Management

The controller disables driver pulses and enters protection primary current is naturally limited by the NCP13992
mode once the FB fault event is confirmed by the FB fault on−time modulation principle in this case. But the primary
timer or counter. Latched or auto−recovery operation is then current increases when the output terminals are shorted. The
triggered – depends on selected IC option. The controller NCP13992 controller will maintain zero voltage switching
adds an auto−recovery off−time period (tA−REC_TIMER) and operation in such case, however high currents will flow
restarts the operation via soft start in case of auto−recovery through the power MOSFETS, transformer winding and
option. The application temperature runaway is thus secondary side rectification. The NCP13992 implements a
avoided in case of overload while the automatic restart is still dedicated secondary side short circuit protection system that
possible once the overload condition disappears. The IC will shut down the controller much faster than the regular FB
with latched FB fault option stays latched−off, supplied by fault event in order to limit the stress of the power stage
the HV startup current source working in DSS mode, until components. The CS pin signal is monitored by the
the VCC_RESET threshold is reached on the VCC pin – i.e. dedicated CS fault comparator − refer to Figure 8. The CS
until user re−connects power supply mains. fault counter is incremented each time the CS fault
Please refer to Figure 23 and Figure 24 for an illustration comparator is triggered. The controller enters
of the NCP13992 FB fault detection block. auto−recovery or latched protection mode (depending on IC
option) in case the CS fault counter overflows refer to
Secondary Short Circuit Detection Figure 11. The CS fault counter is then reset once the CS
The protection system described previously, implemented fault comparator is inactive for at least 50 Mupper upcoming
via FB pin voltage level detection, prevents continuous pulses. This digital filtering improves CS fault protection
overload operation and/or open FB pin conditions. The system noise immunity.

Figure 11. NCP13992 CS Fault Principle

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Dedicated Startup Sequence and Soft−Start 50% duty cycle symmetry – refer to Figure 12. This hard
Hard switching conditions can occur in a resonant SMPS switching appears because the resonant tank initial
application when the resonant tank operation is started with conditions are not optimal for the clean startup.

Figure 12. Hard Switching Cycle Appears in the LLC Application

when Resonant Tank is Excited by 50% Duty Cycle during Startup

The initial resonant capacitor voltage level can differ These facts show that a clean, hard switching free and
depending on how long delay was placed before application parasitic oscillation free, startup of an LLC converter is not
operation restart. The resonant capacitor voltage is close to an easy task, and cannot be achieved by duty cycle
zero level when application restarts after very long delay – imbalance and/or simple resonant capacitor pre−charge to
for example several seconds, when the resonant capacitor is Vbulk/2 level. These methods only work in specific startup
discharged by leakage to the power stage. However, the conditions.
resonant capacitor voltage value can be anywhere between This explains why the NCP13992 implements a
Vbulk and 0 V when the application restarts operation after proprietary startup sequence − see Figure 13 and Figure 14.
a short period of time – like during periodical SMPS The resonant capacitor is discharged down to 0 V before any
turn−on/off. Another factor that plays significant role during application restart − except when restarting from skip mode.
resonant power supply startup is the actual load impedance
seen by the power stage during the first pulses of startup
sequence. This impedance is not only defined by resonant
tank components but also by the output loading conditions
and actual output voltage level. The load impedance of
resonant tank is low when the output is loaded and/or the
output voltage is low enough to made secondary rectifies
conducting during first switching cycles of startup phase.
The resonant frequency of the resonant tank is given by the
resonant capacitor capacitance and resonant inductance
−note that the magnetizing inductance does not participate
in resonance in this case. However, if the application
starts−up when the output capacitors is charged and there is
no load connected to the output, the secondary rectification
diodes is not conducting during each switching cycle of
startup sequence and thus the resonant frequency of resonant Figure 13. Initial Resonant Capacitor Discharge
tank is affected also by the magnetizing inductance. In this before Dedicated Startup Sequence is Placed
case, the resonant frequency is much lower than in case of
startup into loaded/discharged output.

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 NCP13992

Figure 14. Dedicated Startup Sequence Detail

The resonant capacitor discharging process is simply The startup period then depends on the previous condition.
implemented by activating an internal current limited switch Another blank Mlower switch period is placed by the
connected between the HB pin and IC ground – refer to controller in case condition a) occurred. A normal Mlower
Figure 13. This technique assures that the resonant capacitor driver pulse, with DC of 50% to previous Mupper DRV
energy is dissipated in the controller without ringing or pulse, is placed in case condition b) is fulfilled.
oscillations that could swing the resonant capacitor voltage The dedicated startup sequence is placed after the
to a positive or negative level. The controller detects that the resonant capacitor is discharged (refer to Figure 13 and
discharge process is complete via HB pin voltage level Figure 14) in order to exclude any hard switching cycles
monitoring. The discharge switch is disabled once the HB during the startup sequence. The first Mupper switch cycle
pin voltage drops below the VHB_MIN threshold. in startup phase is always non−ZVS cycle because there is
The dedicated startup sequence continues by activation of no energy in the resonant tank to prepare ZVS condition.
the Mlower driver output for Tl1 period (refer to Figure 14). However, there is no energy in the resonant tank at this time,
This technique ensures that the bootstrap capacitor is fully there is also no possibility that the power stage MOSFET
charged before the first high−side driver pulse is introduced body diodes conducts any current. Thus the hard
by the controller. The first Mupper switch on−time Tup1 commutation of the body diode cannot occur in this case.
period is fixed and depends on the application parameters. The IC will not start and provide regular driver output
This period can be adjusted internally – various IC options pulses until it is placed into the target application, because
are available. The Mupper switch is released after Tup1 the startup sequence cannot be finished until HB pin signal
period and it is not followed by the Mlower switch is detected by the system. The IC features a startup watchdog
activation. The controller waits for a new ZVS condition for timer (tWATCHDOG) which activates a dedicated startup
Mupper switch instead and measures actual resonant tank sequence periodically in case the IC is powered without
conditions this way. The Mupper switch is then activated application (during bench testing) or in case the startup
again after the Mlower blank period is used for measurement sequence is not finished correctly. The IC will provide the
purposes. The second Mupper driver conduction period is first Mlower and first Mupper DRV pulses with a
then dependent on the previously measured conditions: tWATCHDOG off−time in−between startup attempts.
1. The Mupper switch is activated for 3/2 of previous
Mupper conduction period in case the measured Soft−start
time between previous Mupper turn−off event and The dedicated startup sequence is complete when
upper ZVS condition detection is twice higher than condition b) from previous chapter is fulfilled and the
the the previous Mupper pulse conduction period controller continues operation with the soft−start sequence.
2. The Mupper switch is activated for previous A fully digital non−linear soft−start sequence has been
Mupper conduction period in case the measured implemented in NCP13992 using a soft−start counter and
time between previous Mupper turn−off event and D/A converter that are gradually incremented by the Mlower
upper ZVS condition detection is twice lower than driver pulses. A block diagram of the NCP13992 soft−start
the previous Mupper pulse conduction period system is shown in Figure 15.

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 NCP13992

Figure 15. Soft−start Block Internal Implementation

The soft−start block subsystems and operation are 4. The Maximum ON−time comparator compares the
described below: actual ON−time counter value with the maximum on−time
1. The Soft−Start counter is a unidirectional counter that is value (tTON_MAX) and activates the latch (or auto−recovery)
loaded with the last Mupper on−time value that is reached at protection mode once IC detect requested number of
the dedicated startup sequence end (i.e. during condition b TON_MAX events. The minimum operating frequency of
occurrence explained in previous chapter). The on−time the controller is defined the same way. The Maximum
period used in the initial period of the soft−start sequence is ON−time comparator reference is loaded by the Soft−Start
affected by the first Mupper on−time period selection and counter value on each switching cycle during soft−start. The
the dedicated startup sequence processing. The Soft−Start Maximum ON−time fault signal is ignored during
counter counts up from this initial on time period to its Soft−Start operation. The converter Mupper switch on−time
maximum value which corresponds to the IC maximum (and thus operating frequency) is thus defined by the
on−time. The Soft−Start counter is incremented by the Soft−Start counter value indirectly – via Maximum
soft−start increment number (tSS_INCREMENT) during each ON−time comparator. The Mupper switch on−time is
Mlower switch on−time period. The soft−start start increased until the Soft−Start counter reaches tTON_MAX
increment, selectable via IC option, thus affects the period and Maximum on−time protection is activated, or
soft−start time duration. The Mlower clock signal for the until ON−time comparator takes action and overrides the
Soft−Start counter can be divided down by the SS clock Maximum ON−time comparator.
divider (KSS_INCREMENT) in case the soft−start period needs 5. The Soft−Start D/A converter generates a soft−start
to be prolonged further – this can be also done via IC option voltage ramp for ON−time comparator input synchronously
selection. The Soft−Start period is terminated (i.e. the with Soft−Start counter incrementing. The internal FB
counter is loaded to its maximum) when the FB pin voltage signal for ON−time comparator input is artificially
drops below VFB_SKIP_IN level. pulled−down and then ramped−up gradually when soft−start
2. The ON−time counter is a bidirectional counter that is period is placed by the system – refer to Figure 16. The FB
used as a main system counter for on−time modulation loop is supposed to take over at certain point when
during soft−start, normal operation or overload conditions. regulation loop is closed and output gets regulated so that
The ON−time counter counts−up during Mupper switch soft−start has no other effect on the on−time modulation.
conduction period and then counts down to zero – defining The Soft−Start counter continues counting−up until it
Mlower switch conduction period. This technique assures reaches its maximum value which corresponds to the IC
perfect 50% duty cycle symmetry for both power switches maximum on−time value – i.e. the IC minimum operating
as afore mentioned. The ON−time counter count−up mode frequency. The Soft−Start period is terminated (i.e. counter
can be switched to the count−down mode by either of two is loaded to its maximum) when the FB pin voltage drops
events: 1st when the ON−time counter value reaches the below VFB_SKIP_IN level. The D/A converter output evolve
maximum on−time value (tTON_MAX) or 2nd when the actual accordingly to the Soft−Start counter as it is loaded from its
Mupper on−time is terminated based on the current sense output data bus.
input information.

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Figure 16. Soft Start Behavior

The Controller Operation during Soft−start Sequence and saturates at its maximum possible value which
Evolves as Follows: corresponds to IC minimum operating frequency. The
The Soft−Start counter is loaded by last Mupper on−time maximum on−time fault detection system is enabled when
value at the end of the dedicated startup sequence. The Soft−Start counter value is equal to tTON_MAX value.
ON−time counter is released and starts count−up from zero The previous on−time repetition feature, described above
until the value that is equal to the actual Soft−Start counter in the ON−time modulation and feedback loop chapter, is
state. The Mupper switch is active during the time when disabled in the beginning of soft start period. This is because
ON−time counter counts−up. The Maximum ON−time the ON−time comparator output stays high for several cycles
comparator then changes counting mode of the ON−time of soft start period – until the current mode regulation takes
comparator from count−up to count−down. A dead−time is over. The previous on−time repetition feature is enabled
placed and the Mlower switch is activated till the ON−time once the current modulation starts to work fully, i.e. in the
counter reaches zero value. The Soft−Start counter is time when the ON−time comparator output periodically
incremented by selected increment during corresponding drops to low state within actual Mupper switch on−time
Mlower on−time period so that the following Mupper switch period. Typical startup waveform of the LLC application
on−time is prolonged automatically – the frequency thus driven by NCP13992 controller can be seen in Figure 17.
drops naturally. Because the operating frequency of the
controller drops and Mlower DRV signal is used as a clock
source for the Soft−start counter, the soft−start speed starts
to decrease on each (or on each N−th) Mlower driver pulse
(where N is defined by KSS_INCREMENT) of switching cycle.
So we have non−linear soft−start that helps to speed up
output charging in the beginning of the soft−start operation
and reduces the output voltage slope when the output is close
to the regulation level. The output bus of the Soft−Start
counter addresses the D/A converter that defines the
ON−time comparator reference voltage. This reference
voltage thus also increases non−linearly from initial zero
level until the level at which the current mode regulation
starts to work. The on−time of the Mupper and Mlower
switch is then defined by the ON−time comparator action
instead of the Maximum ON−time comparator. The Figure 17. Application Startup with NCP13992 −
soft−start then continues until the regulation loop is closed Primary Current − Green, Vout − Magenta
and the on−time is fully controlled by the secondary
regulator. The Soft−Start counter then continues in counting

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Skip Mode Operation preselected level. Zero voltage switching technique is still
Then NCP13992 implements proprietary light load and present for the power switches to achieve high light load
quiet skip mode operating techniques that improve light load efficiency. Quiet skip mode operation is initiated when load
efficiency, reduce no−load power consumption and drops further and FB voltage drops below another FB
significantly reduce acoustic noise. Controller uses 50% threshold that is user adjustable on the skip pin. The
duty cycle symmetry under full and medium load frequency of skip burst is regulated by internal digital
conditions. Normal current mode frequency modulation controller around preselected quiet skip frequency clamp in
takes place during this operating mode – refer to on−time order to reduce acoustic noise. The skip frequency then
processing section of this datasheet. The 50% duty cycle drops to very low values during no−load conditions. Refer
symmetry operating mode is replaced by continues to Figure 18, Figure 19 and Figure 20 for typical application
operation with minimum switching patterns repeated after waveforms during light load and quiet skip mode operating
controlled amount of off−time when load is decreased below modes.

Figure 18. No−load Operation

Figure 19. Quiet Skip Mode Operation

Figure 20. Light−load Operation

The High Voltage Half−bridge Driver resistor Rboot value is 3.3 W. Figure 21 shows the internal
The driver features a traditional bootstrap circuitry, architecture of the drivers section. The device incorporates
requiring an external high voltage diode with resistor in an upper UVLO circuitry that makes sure enough VGS is
series for the capacitor refueling path. Minimum series available for the upper side MOSFET.

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 NCP13992

HV
Vboot
Internal Mupper Pulse Level
Trigger Shifter
S Cboot
Q Mupper
Q
R
HB
dV/dt_P signal dV/dt
detector
dV/dt_N signal
UVLO
Rboot
HB
HB disch. activation discharger
Dboot
VCC
aux
VCC
Fault
Mlower
Internal Mlower Delay
+
GND

Figure 21. The NCP13992 Internal DRVs Structure

The internal dV/dt sensor, connected to the VBOOT pin,

detects the HB pin voltage transitions in order to setup the
optimum DT period – please refer to Dead−Time chapter.
The internal HV discharge switch is connected to the HB pin
and discharges resonant capacitor before application
startup. The current through the switch is regulated to
IDISCHARGE level until the VHB_MIN threshold voltage is
reached on the HB pin. The discharge system assures always
the same startup conditions for application – regardless of
previous operating state.
As stated in the maximum ratings section, the floating
portion can go up to 620 VDC on the BOOT pin. This
voltage range makes the IC perfectly suitable for offline
applications featuring a 400 V PFC front stage.

Automatic Dead−time Adjust

The dead−time period between the Mupper and Mlower
drivers is always needed in half bridge topologies to prevent
any cross conduction through the power stage MOSFETs Figure 22. Optimum Dead−time Period Adjust
that would result in excessive current, high EMI noise
generation or total destruction of the application. Fixed The MOSFET body diode conduction time is minimized
dead−time period is often used in the resonant converters when optimum dead−time period is used which results in
because this approach is simple to implement. However, this maximum efficiency of a resonant converter power stage.
method does not ensure optimum operating conditions in There are several methods to determine the optimum
resonant topologies because the magnetizing current is dead−time period or to approximate it (for example using
changing with line and load conditions. The optimum auxiliary winding on main transformer or modulating
dead−time, under a given operating conditions, is equal to dead−time period with operating frequency of the
the time that is needed for bridge voltage to transition converter). These approaches however require a dedicated
between upper and lower states and vice versa – refer to pin for nominal dead−time adjust or auxiliary winding
Figure 22.

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 NCP13992

voltage sensing. The NCP13992 uses a dedicated method 2. The controller is latched−off in case the ZSV
that senses the VBOOT pin voltage internally and adjusts the condition is not detected within selected
optimum dead−time period with respect to the actual tDEAD_TIME_MAX period
operating conditions of the converter. The high−voltage 3. The controller stops operation and restarts
dV/dt detector, connected to the VBOOT pin, delivers two operation after auto−recovery period in case the
internal digital signals that are indicating Mupper to Mlower ZSV condition has not been detected within the
and Mlower to Mupper transitions that occur on the HB and selected tDEAD_TIME_MAX period
VBOOT pins after the corresponding MOSFET switch is A DT fault counter option is available. Selected number
turned−off. The controller enables the opposite MOSFET in (NDT_MAX) or DT fault events have to occur in order to
the power stage once the corresponding dV/dt sensor output confirm DT fault in this case.
provides information about HB (or VBOOT) pin transition A fixed DT option is also available for this device. The
ends. internal dV/dt sensor signal is not used for this device option
The ZVS transition on the bridge pin (HB) could take a and the tDEAD_TIME_MAX period is used as a regular DT
longer time or even does not finish in some cases – for period instead. The DT fault detection is disabled in this
example with extremely low bulk voltage or when some case.
critical failure occurs. This situation should not occur
normally in correctly designed application because several Temperature Shutdown
other protections would prevent such a situation. The The NCP13992 includes a temperature shutdown
NCP13992 implements maximum DT period clamp that protection. The typical TSD hysteresis is 30°C. When the
limits driver’s off−time period to the tDEAD_TIME_MAX temperature rises above the upper threshold, the controller
value. The corresponding MOSFET driver is forced to stops switching instantaneously, and goes into the off−mode
turn−on by the internal logic regardless of missing dV/dt with extremely low power consumption. The VCC supply is
sensor signal. This situation does not occur during normal maintained (by operating the HV start−up in DSS mode) in
operation and will be considered a fault state by the device. order to memorize the TSD event information. When the
There are several possibilities on how the controller temperature falls below the lower threshold, the full restart
continues operation after this event occurrence – depending (including soft−start) is initiated by the controller. The HV
on the IC option: startup current source features an independent
1. The opposite MOSFET switch is forced to turn−on over−temperature protection which limits its output current
when tDEAD_TIME_MAX period elapses and no in case the DIE temperature exceeds TSD to avoid damage
fault is generated to the HV startup silicon structure.

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 NCP13992

APPLICATION INFORMATION

Controller Operation Sequencing of NCP13992 LLC for the feedback block. The VCC management controls the
Controller HV startup in DSS mode in order to keep enough VCC level
The paragraphs below describe controller operation to hold the latch−up state memorized while the application
sequencing under several typical cases as well as transitions remains plugged−in to the mains.
between them. The power supply is removed from the mains at point H
and the VCC voltage drops down below VCC_RESET level
1. Application start, Brown−out off and restart,
thus the low voltage controller is released from latch. A new
OVP/OTP latch and then restart – Figure 23
Application is connected to the mains at point A thus the application start occurs when the user plugs the application
HV input of the controller becomes biased. The HV startup the mains again.
current source starts charged VCC capacitor until VCC 2. Application start, Brown−out off and restart, output
reaches VCC_ON threshold. short fault with auto−recovery restart – Figure 24
The VCC pin voltage reached VCC_ON threshold in point Operating waveforms descriptions for this figure is
B. The BO, FB, OVP/OTP and PFC MODE blocks are similar to one for Figure 23 from point A till point G – with
enabled. The VBULK/PFC FB pin starts to receive divided one difference. The skip mode operation (FB <
bulk voltage as the external HV switch is activated by PFC VFB_SKIP_IN) blocks the IC startup after first VCC_ON event
MODE output. The VCC blank is activated during each instead of BO_fault.
VCC_ON event to ensure that the internal logic ignores all The LLC converter operation is stopped in point G
fault inputs until the internal blocks are fully biased and because the controller detects an overload condition (short
stabilized after a VCC_ON event. The IC DRVs were not circuit event in this case as the Vout drops abruptly). The
enabled after first VCC blank period in this case as the controller disables all blocks except for the FB block and the
voltage on VBULK/PFC FB is below VBO level. The IC fault logic. The HV startup DSS operation is initiated in
keeps all internal blocks biased and operates in the DSS order to keep enough VCC level for all internal blocks that
(Dynamic Self−Supply) mode as long as the fault conditions need to be biased. Internal auto−recovery timer counts down
is still present. the recovery delay period tA−REC_TIMER.
The BO_OK condition is received (voltage on The auto−recovery restart delay period lapses at point H.
VBULK/PFC FB reach VBO level) at point C. The IC The HV startup current source is activated to recharge VCC
activates the startup current source to refill VCC capacitor capacitor before a new restart.
in order to assure sufficient energy for a new startup. The The VCC_ON threshold is reached in point I and all the
VCC capacitor voltage reaches VCC_ON level again and the internal blocks are biased. The VCC blank and OVP/OTP
VCC blank period is started. The DRVs are enabled and the blank period are started at the same time. The LLC converter
application is started after VCC blank period lapses because operation is enabled, including a dedicated startup and
there is no faults condition at that time. soft−start period. The output short circuit is removed in
Line and also bulk voltage drops at point D so the BO_OK between thus the Vout ramped−up and the FB loop took over
signal become low (voltage on VBULK/PFC FB drops during the LLC converter soft−start period.
below VBO level). The LLC DRVs are disabled as well as
OVP/OTP block bias. The PFC MODE output stay high to 3. Startup, skip−mode operation, low line detection
keep the bulk voltage divider connected, so the BO block and restart into skip−mode – Figure 25
still monitors the bulk voltage. The controller activates the The application is plugged into the mains at point A thus
HV startup current source into DSS mode to keep enough the HV input of the controller becomes biased. The HV
VCC voltage for operation of all blocks that are active while startup current source starts charging the VCC capacitor
the IC is waiting for BO_OK condition. until VCC reaches the VCC_ON threshold.
The line voltage and thus also bulk voltage increase at The VCC pin voltage reaches the VCC_ON threshold at
point E so the Brown−out block provide the BO_OK signal point B. The BO, FB, OVP/OTP and PFC MODE blocks are
once the VBO level is reached. The startup current source is enabled. The VBULK/PFC FB pin begins to receive divided
activated after BO_OK signal is received to charge the VCC bulk voltage as the external HV switch is activated by the
capacitor for a new restart. PFC MODE output. The VCC blank period is activated
The VCC_ON level is reached in point F. The OVP/OTP during each VCC_ON events. This blank ensures that the
block is biased and the VCC blank period is started at the internal logic ignores all fault inputs until the internal blocks
same time. The controller restores operation via the regular are fully biased and stabilized after VCC_ON event. The IC
startup sequence and soft−start after VCC blank period DRVs are not enabled even after VCC blank period ends
lapses since there is no fault condition detected. because the OVP fault condition is present. The OVP fault
The application then operates normally until the condition disappears after some time so the HV startup
OVP/OTP input is pulled−up at point G. The controller then current source is enabled to prepare enough VCC for a new
enters latch−off mode in which all blocks are disabled except startup attempt. The new VCC blank and OTP blank periods

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 NCP13992

are placed after the VCC_ON event is detected. The controller VCC_OFF level during skip mode. The device would enters
authorizes DRVs at point C as there are no faults conditions into off−mode.
present after the VCC blank period elapses. The load current The line voltage drops in point F, but the bulk voltage is
is reduced thus the FB loop reduces the primary controller dropping slowly as there is nearly no consumption from the
FB pin voltage. bulk capacitor during skip mode – only some refilling bursts
The load diminished further and the FB skip threshold is are provided by the controller. The application thus
reached in point D. The controller turns−off all the blocks continues in skip mode operation for several skip burst
that are not essential for the controller operation during cycles.
skip−mode – i.e. all blocks except FB block and VCC The bulk voltage level less than VBO threshold is detected
management. This technique is used to minimize the device by the controller in point G during one of the skip burst
consumption when there are no driver pulses during pulses. The controller thus disabled DRVs and enters DSS
skip−mode operation. The output voltage then drops mode of operation in which the OVP/OTP block is disabled
naturally and the FB loop reflects this change into the and the controller is waiting for BO_OK event. The PFC
primary FB pin voltage that increases accordingly. The MODE provides the VPFC_M_ON voltage in this case to
auxiliary winding is refilling VCC capacitor during each allow the PFC stage to refill bulk capacitors.
skip burst thus the controller is supplied from the application The line voltage is increased at point H thus the controller
during the skip mode operation. receives the BO_OK signal. The BO_OK signal is received
The controller FB skip−out threshold is reached in point during the period in which the HV startup current source is
E; the controller enables all blocks and LLC DRVs to refill active and refills the VCC capacitor.
the output capacitor. The controller did not activate the HV This VCC_ON threshold is reached by the VCC pin at point
startup current source because there is enough voltage I. The VCC blank period and OVP/OTP blank period are
present on the VCC pin during skip mode. The OTP blank started at the same time. The full startup sequence is enabled
periods is activated at the beginning of the skip burst to mask at the end of the VCC blank period as no fault is detected. The
possible OTP faults. application then enters skip mode again as the load current
Note: The VCC capacitor needs to be chosen with a value is low.
high enough to ensure that VCC will not drop below the

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 NCP13992

Figure 23. Application Start, Brown−out Off and Restart, OVP/OTP Latch and then Restart

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 NCP13992

Figure 24. Application Start, Brown−out Off and Restart, Output Short Fault with Auto−recovery Restart

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 NCP13992

Figure 25. Startup, Skip−mode Operation, Low Line Detection and Restart into Skip

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 NCP13992

PACKAGE DIMENSIONS

SOIC−16 NB MISSING PINS 2 AND 13

CASE 751DU
ISSUE O

NOTE 5
D A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
16 9 2X 2. CONTROLLING DIMENSION: MILLIMETERS.
0.10 C D 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.10 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
F 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
E E1 NOTE 4
NOTE 6
PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS
OR GATE BURRS SHALL NOT EXCEED 0.25 mm PER SIDE.
A1 DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
L2 L PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
0.20 C 1 8
B 14X b DETAIL A C SEATING
PLANE MILLIMETERS
2X 4 TIPS NOTE 5 DIM MIN MAX
0.25 M C A-B D
TOP VIEW A 1.35 1.75
A1 0.10 0.25
2X b 0.35 0.49
0.10 C A-B DETAIL A c 0.17 0.25
D 9.80 10.00
D
0.10 C E 6.00 BSC
0.10 C E1 3.90 BSC
e 1.27 BSC
L 0.40 1.27
L2 0.203 BSC
A e END VIEW
C SEATING
PLANE
SIDE VIEW

RECOMMENDED
SOLDERING FOOTPRINT
14X
1.52

16 9

7.00

1 8

14X
1.27 0.60
PITCH
DIMENSIONS: MILLIMETERS

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