Scribd
Upload
1K views2 pages

VLSI Interview Experience Synopsys

The document contains an interview experience that included questions from various domains: 1) Digital electronics and digital IC design questions regarding flip-flops, latches, logic gates and finite state machines. 2) SystemVerilog questions on blocking/non-blocking assignments, sensitivity lists, data types, formal verification, and writing testbenches. 3) UVM questions about the standard UVM verification methodology and roles of different components. 4) AXI protocol questions regarding channels, outstanding transactions, reset behavior and transfer types. 5) Computer architecture questions on pipelining, memory hierarchy and the role of cache memory.

Uploaded by

Akash Katta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
1K views2 pages

VLSI Interview Experience Synopsys

The document contains an interview experience that included questions from various domains: 1) Digital electronics and digital IC design questions regarding flip-flops, latches, logic gates and finite state machines. 2) SystemVerilog questions on blocking/non-blocking assignments, sensitivity lists, data types, formal verification, and writing testbenches. 3) UVM questions about the standard UVM verification methodology and roles of different components. 4) AXI protocol questions regarding channels, outstanding transactions, reset behavior and transfer types. 5) Computer architecture questions on pipelining, memory hierarchy and the role of cache memory.

Uploaded by

Akash Katta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

VLSI Interview Experience

Ques1: Tell me About Yourself ?

Questions from Digital Electronics and Digital IC Design

1. Difference between X (Don’t care) and Z (High Impedance).


2. Difference between FLIP FLOP and LATCH
3. Flip flop using Latch
4. Optimized architecture to get 63X as output and whereas X is input.
5. OR Gate Using MUX
6. What is difference between Synchronous and Asynchronous FIFO.
7. Why CMOS Logic
8. FSM for Sequence Detector for sequence 1011. (Moore and Mealy both)
9. Set up, Hold time and clock skew

System Verilog:

1. Example to differentiate blocking and non blocking assignment


2. What do you means by sensitivity list and code snippet
3. Difference between Display & Monitor
4. Write code for Sequence detector (1011, Using FSM which u made)
5. Different types of Fork-Join and there uses
6. Difference between Queues and Arrays
7. various data types in system verilog
8. Do “bit” support all four Logic levels 0,1,X,Z and if not then which data type to use
9. What is Constraint Random Verification
10. Formal Verification
11. Always v/s initial
12. Reg v/s Wire in verilog (Procedural & continuous assignment in verilog)
13. Code JK, T flip and also write testbench to verify it.

UVM (Mentioned this as Basic Knowledge in Resume)

1. How UVM is used in Functional verification and why UVM is needed ?


2. Different phases of the UVM testbench
3. Draw architecture for standard UVM TB architecture
4. Role of Scoreboard, Agent in UVM TB
5. Role of UVM in constraint Randome verification
6. Difference between TLM and Analysis ports

AXI Related Question:

1. Rajveer, Since you are working on AXI protocol related Designs so assume I don’t know
about AXI protocol and Give me basic overview and Use cases of this protocol
2. How many Channels are there in AXI protocol
3. Why there is no READ response channel
4. What do you mean by Outstanding Transaction capability in AXI.
5. AXI IP was running and performing data transfer and sudden power cut. What will happen
when power resumes. Also what happens during reset
6. Difference between FIXED and INCR transfer
7. WRAP Boundary calculation
Computer Architecture:

1. Pipeline and its role in SoC Design


2. Memory hierarchy
3. Cache memory role in Processor

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy