gls vs rtl ?

SDF corners
what is inside sdf
what is zd? Zd vs sdf?
what is synchronizer?
explain metastability
How to debug setup and hold violation
draw 4:1 mux using gates
swap value with and without temp variable
why we use constraint ?
purpose of Randomization
pre and post randomization why we use them ?
can we write constraint outside class if yes then how we can write outside ?
What is multidriver and what are multidriver issues ?
What is race condition ?
what is clock skew?
What is isolation and retention cell ?
what is priority encoder?
what is NRF and how to intialize them?
How to turn off synchronizer Timing ?
rand vs randc?\

1.diff b/w soc and ip

2.what you verified in low power?
3.what is the test flow in low power?
4.how power up the ip ?
5. what are the states(modes) in low power?
6.how to convert sv to c?
7.what are the content in upf? Is there any memory info? Any memory subsystem
in ur soc?
8.when we need level shifters?
9.what is the booting process?
10.use of stack pointer?
11.how we can stop the simulation without using objections and $finish()
12.factory overriding methods? How to create the pkt ?
13.how we can count no.of raise objections and no.of drop objectons?
14.is there any another method to connect seq except start method?
15.virtual sequence? Virtual seqr? Sequence?
16.diff b/w m-seqr and p-seqr?
17.virtual interface?
18.what is the tlm fifo?
19.how to connect mon to sb?
20.what u developed in ethernet?
21.what is hresponse signal?
22.what is in-order and out-of-order axi?

ROUND 1:

1. Explain about your Project? Mostly asked about encoding techniques?

2. Explain Ethernet encoder and Manchester encoder?
3. What is the purpose of Manchester encoder? And its application?
4. Why you are using encoding techniques?
5. How you are developing your environment by using sv or uvm?
6. Explain your transmitter environment?
7. Asked about sequence?
8. Explain the difference between m-sequencer and p-sequencer?
9. Where you are using p-sequencer?
10. Write an assertion for signal A is high after that B should be high and after that c should be
asserted for infinite times, and after some delay d should be high?
11. And asked me to write a property based for same assertion? And for same assertion did some
modification.
12. What is the difference between new and create method?
13. What are the main blocks in your transmitter and receiver block and explain?
 14. One scenario based question like am giving huge memory and am writing randomly into that and
randomly reading from that memory ? then how can you compare that in the scoreboard?
15. How can you check the random test case? And how you are comparing in scoreboard for random
test case?

ROUND -2
16. What are the projects you worked on previously?
17. What is Ethernet frame generator? Why you are using that?
18. Explain Ethernet frame? What is Manchester encoder and its application?
19. What is main purpose of this Ethernet generator block?
20. What are the component you worked on? And explain about sanity test case?
21. Asked me to draw the ethrnetframe generator block where exactly you used that block in your
environment?
22. How you are verifying the register in your project, like writing and reading how you are
checking?
23. Asked me about APB Protocol, explain me about that with fsm diagram? Explained about those
signals?

Set 1:

Basic Digital Electronics

Flops latches hold time and Setup time. Mux, conversion of muxs into gates.
GLS basic
bugs in gls
how to set environment for gls.

Set 2:

1. Generate a 50Mhz clock with 60% duty cycle.

2. Write a constraint to generate 10 random elements and the order of the elements should be in
descending order.
3. Write an assertion to check the clk_period of 50Mhz.
4. a) Consider we have 1000 assertions. suppose one assertion is not asserted and how we will get to
know that the assertion has not asserted.
b) Clk_period assertion : If antecedent is not correct, how will you find that antecedent is incorrect.
Note: While asserting the property, we are not displaying any error message.
5. In which phases does the raise_objection and drop_objection will be written.
6. Once the sequence starts, what happens to the raise_objection in the background.
7. Out of 100 assertions, for one assertion the antecedent is not correct and the assertion is not
triggered
8. How do you start the sequence on to the sequencer without using the "start" method.
9. What happens if we didn't raise and drop the objections.
10. Some basic Coverage Questions.

Set 3:

1) Explain about your latest project?

2) What are the roles and responsibilities in your project?

3) What is virtual interface?

4) What is inline constraint?

5) Why we are writing c based test cases for soc project?

6) What are the responses in AHB?

7) Explain about retry and split response?

8) What are the channels and responses in AXI?

9) Explain about SLVERR and DECERR response?

10) Which simulation u have run in GLS?

11) What is setup time and hold time?

12) What is virtual class?

Set 4:

1)difference between code coverage and functional coverage?

2)If my code coverage is 100% and functional coverage is 90%.What are the things need to be done to
make functional coverage 100%
3)In which phase do we need to write functional coverage?
4)difference between verification plan ,coverage plan and test plan?
5)I am having DUT , w_addr[7:0] and w_data[15:0] are inputs
R_addr[7:0] and r_data[63:0] are outputs.Write the functional coverage ?
6)whenever I randomize the particular array,I should store 9 elements to that array without
repetition.
7)what is the use of soft constraint?Expalin?
8)Did you found any bugs in your latest project? If you found a bug how did you fix it?
9)Have you worked on power aware verification and GLS?
10) If my functional coverage is 100% and code coverage is 90%.What are the things need to be done to
make code coverage 100%
11)I am having two masters and three slaves.Think of different scenarios and write the test plan for the
given scenario?
12)different types of code coverage?
13)did you use any scripts for writing functional coverage?

Set 5:

1. Tell me about yourself?

2. What are projects you have worked on?
3. What is the need of AMBA3 Architecture?
4. If there is no AMBA protocols then which protocol we can use?
5. What is the difference between bit [7:0] and byte?
6. What is the difference between Dynamic Array and Associative Array?
7. Where we can use Dynamic Array and Associative Array in projects?
8. If there are two classes, One is parent and the other is Child? How can we override parent with
the child?
9. If they have same arguments with the same variable? If we pass two different values to the child
and parent? What is the output i.e either child will reflect or parent will?
10. If the data types of those two arguments are different then what will happen?
11. Write a SV code for clockdiv4?
12. If an input is 11001100? Write a code to get output as 11110000?
13. Write a C language code for a string which should be printed in reverse order?
14. There are 5 lanes on a race track. One needs to find out the 3 fastest horses among total of 25.
Find out the minimum number of races to be conducted in order to determine the fastest three.
15. There are 8 batteries, but only 4 of them work. You have to use them for a flashlight which needs
only 2 working batteries. To guarantee that the flashlight is turned on, what is the minimum
number of battery pairs you need to test?
16. What is the use of Interface?
17. Where do we instantiate interface?
18. How do we assign signals to the interface in any class?

1st round>> INTERVIEWER - Mihul pitwa

1] explain about your recent project ? asked if i have worked on soc level project
2] explain APB read transaction with waveform?
3] write a code for the fibonacci series in c?
4] For the given below dut , write a test scenario,full testbench?

5] For the above DUT ,how will you verify the output you are getting is same as the input you
provided?
6] difference between illegal and ignore bins ?
7] AXI write transaction with waveform ?
8] What are the critical RTL bugs found in the project ?
9] Sub questions are projects ?

2nd round>> INTERVIEWER - Vijay

1] asked about the project ?

2]More Sub questions of the project ?
3] say i have a dual port ram , which takes random addresses , how will you verify ,and write a
scoreboard code ?
4] write a coverage for 1kb memory , where i want to ignore some bins?
5] say there is a basket, it has 100 balls in it, there are red balls,green balls,black balls, blue
balls , but whenever i pick the ball, i want red ball frequently , write a code for it in sv ?
6] Difference between weighted distribution and non weighted distribution constraint ?

1.Introduce yourself?

2.What do you know about vlsi design and verification?

3.Why do you need verification and how do you start verification?

4.What kind of verification you have worked on?

5.Your project roles?

6.Understanding about UVM test bench flow?

7.How do Build phase execute?

8.UVM factory and its uses?

9.What are the different Data types in SV?

10.Difference between wire and reg?

11.System Verilog Events?

12.Different types of arrays in System Verilog?

13.Difference between Associative Array and Dynamic Array?

14.Difference between bounded and unbounded queue?

15.Difference between blocking and non blocking assignment statements?

16.Difference between fork join and fork join_any?

17.Difference between tasks and functions?

18.Different types of code coverage you have worked on?

19.Coverpoint,Covergroup,Bins ?

20.How do the below code appear on a waveform?

always@(posedge clk);

begin

A=5;

B<=1;

End

21.What is the value of (P-A)*(P-B)*.....(P-Z)?

1. Introduce yourself.
 2. What is isolation cell and retention cell.
3. How will u know that isolation cell is missing from one IP to another IP.
4. If LEVEL SHIFTERS are missing then what will happen & how will know that level shifters
are missing.
5. What is gls? how you verified? what u have verified?
6. Have u debugged or u have to report to someone or u have to debugged?
7. Do u know sv and uvm
8. What is clocking block? How race round will avoid by clock block/
9. What is interface , modport
10. What is virtual interface
11. Glass has full of water and u have no measurement thing& how will make half without
using any measurement

.Explain about projects what you done previously?

2.what is Isolation cells?

3. why we need Isolation cells?

4.what is the use of Isolation cell?

5.what are the types of Isolation cell?

6.How you enable isolation cell?

7.what are the contents present in upf?

8.what is level shifter? what is the use of it?

9.Explain about processor booting?

10.How interrupt will be served?

11.How cpu will knows which

12.And gate using Nand gate?

13.write a Verilog code for half adder?

14.diff b/w task and functions?

15.diff $display and $monitor?

16.diff macros and functions?

17.what is pointer in c?

18.How you identify source file and header file in c?

19.what are compile errors and runtime errors?

20.what is meant by assemble code?

1. Self intro
2. Write a 4:1 mux code using ternary operator
3. Implement XOR gate using 2:1 mux
4. Finite state machine for 1101 mealy non-overlapping
5. Explain what you did in your clock project
6. How will you verify that whether the required frequency is going to all
modules or not.
7. Do you write any checkers
8. What is virtual interface
9. Do you have any idea about system verilog tasks and function.
10. Why you use isolation cells
11. Which protocols do you used in your project
12. How many channels are present in AXI
13. Outstanding and out of order features in AXI
14. Master trying to write/read into particular Slave, but slave does not
response anything, what is the issue?
15. Explain objections in UVM
16. Did you done Processor based verification?
17. He given some scenario that take one pointer variable and configure
some address by using processor/CPU
18. Difference between INC and WRAP in AHB
19. Do you know ISR[Interrupt service Routine]
20. Write the code for isolation strategies how it is present in UPF file

2nd panel

1. What is the recent project you did

2. Explain the flow of clock controller
 3. He given some frequencies, then he asked to write assertion checkers for
how to find required frequency with the help of PLL LOCK
4. What is the need of GLS
5. Did you face any issues with zero delay loops
6. How you avoid the zero delay loops
7. How you verify the timing checks by using SDF simulation
8. Explain the flow of Fuse and Reset project
9. Is protected signals are present in AHB?
10. Explain HTRANS in AHB?
11. Explain isolation cells
12. Is there any power signal present in clock module
13. What are the corner cases you verified in clock controller
14. Explain retention strategies
15. How clock controller give Output frequency, whether it should be
constant or it will give different values
16. Do you know any register model
17. Did you work on SOC level verification
18. How you connect C and SV in your environment
19. How you connect tb to your environment

1.what u done in low power?

2.what is isolation cell?
3. types of isolation cells?
4.where u r going to place isolation cells?
5. whether u need to connect clamp0 or clamp 1 ? how u will know ?
6. how will u know whether isolation cells are inserted or not?
7.what is power domain?
8. within one power domain can we create one more power doamin?
9.along with the power domain can we do power down of module?
10.types of retention cells? name them?
11. how boolean latch will work?
12. he asked me about dv file?
13. he asked me about nlp coverage ?
14. what is power switche?
15. power nets and sets?
16.explain about processor booting?
17. what u verified in processor booting?
18. test case for retention cells ?
19. why we are using level shifters?
20. questions regarding ahb protocol? given some senarios answers htrans,hready,hwrite
21. what are the channels in ahb?
22. how many channels in axi?what are they?
23. in axi if the response not came based on which signal u will know?
24. based on which signal u will know the address is valid or not?
25. handshaking signals in axi?
26. asked about linux commands? command for difference between two directories?
27. gvim commands? command for select complete line?
28. in gvim command for replace a string?
29. verdi ? how will u search a signal?

1st Round: Manish

1) tell me about yourself?

2) what are the roles and responsibilities in your project?

3) diff between SoC verification and block level verification?

4) questions based on SoC level verification

5) questions based on Projects

6) More questions related to project

7) what are the functional testcases you have developed in your project?

8) explain about functional testcases and connectivity checks in your SoC project?

9) what are the connectivity checks you have done?

10) code: what is result for below code?

1) for(int i = 0; i < 5; i++) begin

fork

int j;

j = i;

thread(j);
 join_none

end

2)for(int i = 0; i < 5; i++) begin

automatic int j;

j = i;

fork

thread(j);

join_none

end

3)for(int i = 0; i < 5; i++) begin

fork

automatic int j;

j = i;

thread(j);

join_none

end

4)for(int i = 0; i < 5; i++) begin

automatic int j;

j = i;

fork

#1ns;

thread(j);

join_none

end

11) questions in system verilog

12) what is call back? where and why they are used in your testbench?

13) questions related to constraints

14) questions related to axi2ahb project

15) How AXI ID's are mapped to AHB? (In AHB there are no ID's, so to what signal will the AXI ID's are
mapped to AHB)?

16) why do we need AXI2AHB bridge?

2nd Round: Nagendra

17) Tell me about yourself

18) Questions related to my SoC project

19) Questions about AXI2AHB Bridge project

20) Questions on AXI Protocol

21) How to convert 64-bit data axi transaction to ahb transaction?

22) What is the use of DECERR and SLVerr?

23) Exclusive access in axi?

24) Explain the flow of axi protocol, like write and read happens with waveform?

25) Handshake mechanism in axi?

26) what are signals and their features?

27) Question related to UVM

28) what is uvm_component and why we need so many components, can’t we do in single component?

29) sequencer driver handshake mechanism?

30) testbench flow in UVM?

31) how the sequence knows on which sequencer it must start?

32) What we need phase objections in UVM?

33) Questions related to Constraints.

34) Did you work on coverage?

35) What is functional coverage?

36) What is Toggle coverage?

37) How to you implement coverage for 4kb address and 1kb address boundary in ahb?

38) Tell me about Connectivity check in my SoC project?

3rd Round: Manager: Daniel

39) Scenario based questions related to projects

40) Gave few Logics to implement?

41) Asked whether I worked on Core verification?

42) Asked whether I worked on C based testcases?

43) Asked whether I worked on GLS?

44) Asked whether I worked on power management? (PA)?

45) Puzzle:

There are 25 horses among which you need to find out the fastest 3 horses. You can conduct race among
at most 5 to find out their relative speed. At no point you can find out the actual speed of the horse in a
race. Find out the minimum no. of races which are required to get the top 3 horses.

● Brief about your recent project

● What type of test cases you wrote
● About ethernet and preamble use in ethernet
● What is the critical bug u fixed recently
● What is your contribution in functional coverage in the recent project
● Write a code to randomise the inputs and the output should be divisible by 3 and not
divisible by 4 and should be less than 100
● Assertion related code
● Top level test.bench of your last project
● Data link layer and transport layer means?
● What are the inputs and outputs of mac
● What is use of m and p sequencer
● Types of transfers in axi
● Some questions on ahb
● Write a assertion …we have two signals a and b , a should be high from the same clk
cycle after 5 r 6 clk cycles b should be high , need to repeat this for 5 times and then c
should be high , use sequence and property concept
●
project explation.
what is factory and factory overide
port export ,driver-sequencer
analysis port ,monitor scoreboard
uvm event pool
what is make file
i2c fram format,start and stop condition
till now what you debug (detailed explanation)
what is full duplex.how you verify full duplex in spi.
why we use functional coverage

1.write a constraint logic for source address and destination address for 4kB address space and
address should not repeat, source address should be always less than destination address?
2.Types of functional coverage and their differences?
3. write a functional coverage code with respect to first question?
4.why clocking block required in interface?
5. where and all assertions can be implemented?
6. Write Assertion for - Once Signal B" goes high "Signal "A" must not be asserted until Signal
"C" asserted high? Note: it can happen at any number of clocks.
7.what is uvm_factory?
8. What happens if class is not registered with factory? without factory registration will uvm
phases work?
9.if we are assigning child class handle to parent class , child and parent class having same
method name with same signature, also same constraint with different range. when we are
accessing through parent class handle which method and constraint will execute ?
10.what is uvm_config_db ? what is its usage in testbench?
11.Difference between associative array and dynamic array ? explain with their application?
12. write a constraint to dynamic array with value range 10 to 20 , 10 should get 80 tmes and 20
should get 20 times?
13.if you want to assign parent class handle to child class handle what need to be done and
why?
14.write output of the following code
module tb;
initial begin
$display("[%0t] Main Thread: Fork Join start going to start ",$time);
fork
fork
print(20,"Thread1_0");
print(30,"Thread1_1");
join
 print(10,"Thread1");
join
$display("[%0t] Main Thread: Fork Join start is finished",$time);
end

task automatic print(int time, string name);

$(time) $display("[%0t] %s",$time,name);
endtask
endmodule

Set 2:
1. How would you like to introduce yourself.
2.ethernet working flow and how ethernet packet is created and how data tranfer is happening
between blocks , also asked explain with real time example.
3.demorgans law: (a+b)' =a'.b', (a.b)'=a'+b'
4.what are the universal logic gates and why we called universal logic gates?
5. Draw a not gate using nand gate?
6.Draw a Flip flop using nand gates? How to convert SR flip flop to D flip flop?
7.write a D flip flop logic in verilog?
8. In the above d flip flop logic if reset is continuously toggling what will be output Q?
9.explain about raise time,fall time, setup time, hold time ? What happens if input varies before
hold time ?
10.Limitations of k map ?
11. Where and all grey codes will be used ,what purpose?
12. In Cross domain crossing ,how synchronisation happens between blocks?
13. What are the types of synchronizations we have?
14.why always block not used in program block?
15.difference between static and automatic methods?
16. Why static methods can't be used in pass by reference?
17. Explain polymorphism concept?
18.what are types of coverage?
19.where and all functional coverage and assertions will be implemented?
20. What are the test cases you worked on?
21.which test case you will use for verification configuration register sequences?

1) Introduce yourself?
2) what is your recently worked project. Can u elaborate it?
3) How you wrote the scripting? How did you do that process? Explain.
4) Did you implemented the TB architecture for your block? And the testcases are in which
files?
5) How you rate your in SV and UVM ?
6) How many phases are there in UVM? In which approach is in Start of simulation phase?
7) what is program block?
8) what is the difference between module and program block?
9)Do we have program blocks in UVM ?
10) what is assert keyboard you use, if signal c becomes high and a,b signals are in constant?