CD54HC373, CD74HC373

SCLS452C – FEBRUARY 2001 – REVISED MAY 2022

CDx4HC373 Octal Transparent D-Type Latches With 3-State Outputs

1 Features 2 Description
• 2-V to 6-V VCC operation The ’HC373 devices are octal transparent D-type
• Wide operating temperature range of latches designed for 2-V to 6-V VCC operation.
–55℃ to 125℃
When the latch-enable (LE) input is high, the Q
• Balanced propagation delays and transition times
outputs follow the data (D) inputs. When LE is low,
• Standard outputs drive up to 15 LS-TTL loads
the Q outputs are latched at the logic levels of the D
• Significant power reduction compared to LS-TTL
inputs.
Logic ICs
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
CD74HC373M SOIC (20) 12.80 mm × 7.50 mm
CD74HC373E PDIP (20) 25.40 mm × 6.35 mm
CD54HC373F CDIP (20) 26.92 mm × 6.92 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Logic Diagram (positive logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC373, CD74HC373
SCLS452C – FEBRUARY 2001 – REVISED MAY 2022 www.ti.com

Table of Contents
1 Features............................................................................1 7.1 Overview..................................................................... 8
2 Description.......................................................................1 7.2 Functional Block Diagram........................................... 8
3 Revision History.............................................................. 2 7.3 Device Functional Modes............................................8
4 Pin Configuration and Functions...................................3 8 Power Supply Recommendations..................................9
5 Specifications.................................................................. 4 9 Layout...............................................................................9
5.1 Absolute Maximum Ratings........................................ 4 9.1 Layout Guidelines....................................................... 9
5.2 Recommended Operating Conditions(1) .................... 4 10 Device and Documentation Support..........................10
5.3 Thermal Information....................................................4 10.1 Receiving Notification of Documentation Updates..10
5.4 Electrical Characteristics.............................................5 10.2 Support Resources................................................. 10
5.5 Timing Requirements ................................................. 5 10.3 Trademarks............................................................. 10
5.6 Switching Characteristics ...........................................6 10.4 Electrostatic Discharge Caution..............................10
5.7 Operating Characteristics........................................... 6 10.5 Glossary..................................................................10
6 Parameter Measurement Information............................ 7 11 Mechanical, Packaging, and Orderable
7 Detailed Description........................................................8 Information.................................................................... 10

3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2022) to Revision C (May 2022) Page
• Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, N was 69 is now 84.6.... 4

Changes from Revision A (April 2003) to Revision B (January 2022) Page

• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC373 CD74HC373

 CD54HC373, CD74HC373
www.ti.com SCLS452C – FEBRUARY 2001 – REVISED MAY 2022

4 Pin Configuration and Functions

OE 1 20 VCC
1Q 2 19 8Q
1D 3 18 8D
2D 4 17 7D
2Q 5 16 7Q
3Q 6 15 6Q
3D 7 14 6D
4D 8 13 5D
4Q 9 12 5Q
GND 10 11 LE

J, N, or DW package
20-Pin CDIP, PDIP, or SOIC
Top View

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: CD54HC373 CD74HC373
CD54HC373, CD74HC373
SCLS452C – FEBRUARY 2001 – REVISED MAY 2022 www.ti.com

5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ± 20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ± 20 mA
IO Continuous output drain current per output VO = 0 to VCC ± 35 mA
IO Continuous output source or sink current per output VO = 0 to VCC ± 25 mA
Continuous current through VCC or GND ± 50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 Recommended Operating Conditions(1)

MIN MAX UNIT
VCC Supply voltage 2 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
tt Input transition (rise and fall) time VCC = 4.5 V 500 ns
VCC = 6 V 400
TA Operating free-air temperature –55 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

5.3 Thermal Information

DW (SOIC) N (PDIP)
THERMAL METRIC 20 PINS 20 PINS UNIT
(1)
RθJA Junction-to-ambient thermal resistance 109.1 84.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 76 72.5 °C/W
RθJB Junction-to-board thermal resistance 77.6 65.3 °C/W
ψJT Junction-to-top characterization parameter 51.5 55.3 °C/W
ψJB Junction-to-top characterization parameter 77.1 65.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC373 CD74HC373

 CD54HC373, CD74HC373
www.ti.com SCLS452C – FEBRUARY 2001 – REVISED MAY 2022

5.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C TA = –55°C to 125°C TA = –40°C to 85°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN MAX MIN MAX MIN MAX
2V 1.9 1.9 1.9
IOH = –20 μA 4.5 V 4.4 4.4 4.4
VOH VI = VIH or VIL 6V 5.9 5.9 5.9 V
IOH = –6 mA 4.5 V 3.98 3.7 3.84
IOH = –7.8 mA 6V 5.48 5.2 5.34
2V 0.1 0.1 0.1
IOL = 20 μA 4.5 V 0.1 0.1 0.1
VOL VI = VIH or VIL 6V 0.1 0.1 0.1 V
IOL = 6 mA 4.5 V 0.26 0.4 0.33
IOL = 7.8 mA 6V 0.26 0.4 0.33
II VI = VCC or 0 6V ±0.1 ±1 ±1 μA
IOZ VO = VCC or 0 6V ±0.5 ±10 ±5 μA
ICC VI = VCC or 0 IO = 0 6V 8 160 80 μA
Ci 10 10 10 pF
Co 20 20 20 pF

5.5 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
TA = 25°C TA = –55°C to 125°C TA= –40°C to 85°C
VCC UNIT
MIN MAX MIN MAX MIN MAX
2V 80 120 100
tw Pulse duration, LE high 4.5 V 16 24 20 ns
6V 14 20 17
2V 50 75 65
tsu Setup time, data before LE↓ 4.5 V 10 15 13 ns
6V 9 13 11
2V 5 5 5
th Hold time, data after LE↓ 4.5 V 5 5 5 ns
6V 5 5 5

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: CD54HC373 CD74HC373
CD54HC373, CD74HC373
SCLS452C – FEBRUARY 2001 – REVISED MAY 2022 www.ti.com

5.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
FROM TO LOAD TA = 25°C TA = –55°C to 125°C TA = –40°C to 85°C
PARAMETER VCC UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN MAX MIN MAX MIN MAX
2V 150 225 190
D Q CL = 50 pF 4.5 V 30 45 38
6V 26 38 33
tpd ns
2V 175 265 220
LE Q CL = 50 pF 4.5 V 35 53 44
6V 30 45 37
2V 150 225 190
ten OE Q CL = 50 pF 4.5 V 30 45 38 ns
6V 26 38 33
2V 150 225 190
tdis OE Q CL = 50 pF 4.5 V 30 45 38 ns
6V 26 38 33
2V 60 90 75
tt Q CL = 50 pF 4.5 V 12 18 15 ns
6V 10 15 13

5.7 Operating Characteristics

VCC = 5 V, TA = 25℃
PARAMETER TYP UNIT
Cpd Power dissipation capacitance 51 pF

6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC373 CD74HC373

 CD54HC373, CD74HC373
www.ti.com SCLS452C – FEBRUARY 2001 – REVISED MAY 2022

6 Parameter Measurement Information

A. CL includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmaxis measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
I. All parameters and waveforms are not applicable to all devices.

Figure 6-1. Load Circuit and Voltage Waveforms

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: CD54HC373 CD74HC373
CD54HC373, CD74HC373
SCLS452C – FEBRUARY 2001 – REVISED MAY 2022 www.ti.com

7 Detailed Description
7.1 Overview
The ’HC373 devices are octal transparent D-type latches designed for 2-V to 6-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs
are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
7.2 Functional Block Diagram

7.3 Device Functional Modes

Table 7-1. Function Table(each latch)
INPUTS OUTPUT
OE LE D Q

L H H H
L H L L
L L X Q0
H X X Z

8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC373 CD74HC373

 CD54HC373, CD74HC373
www.ti.com SCLS452C – FEBRUARY 2001 – REVISED MAY 2022

8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: CD54HC373 CD74HC373
CD54HC373, CD74HC373
SCLS452C – FEBRUARY 2001 – REVISED MAY 2022 www.ti.com

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC373 CD74HC373

 PACKAGE OPTION ADDENDUM

www.ti.com 11-May-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CD54HC373F ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC373F Samples
& Green
CD54HC373F3A ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8407201RA Samples
& Green CD54HC373F3A
CD74HC373E ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC373E Samples

CD74HC373EE4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC373E Samples

CD74HC373M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC373M Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-May-2023

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC373, CD74HC373 :

• Catalog : CD74HC373
• Military : CD54HC373

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-May-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC373M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
CD74HC373M96 SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-May-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC373M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HC373M96 SOIC DW 20 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-May-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC373E N PDIP 20 20 506 13.97 11230 4.32
CD74HC373EE4 N PDIP 20 20 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated