CD 74 HC 374

CD54HC374, CD74HC374, CD54HCT374, CD74HCT374, CD54HC574, CD74HC574, CD54HCT574,
CD74HCT574
SCHS183E – NOVEMBER 1998 – REVISED OCTOBER 2022
CDx4HC374 High-Speed CMOS Logic Octal D-Type

Flip-Flop, 3-State Positive-Edge Triggered
1 Features 2 Description
• Buffered inputs The ’HC374, ’HCT374, ’HC574, and ’HCT574 are
• Common three-state output enable control octal D-type flip-flops with 3-state outputs and the
• Three-state outputs capability to drive 15 LSTTL loads. The eight edge-
• Bus line driving capability triggered flip-flops enter data into their registers on
• Typical propagation delay (clock to Q) = 15 ns at the LOW to HIGH transition of clock (CP). The
VCC = 5 V, CL = 15 pF, TA = 25℃ output enable (OE) controls the 3-state outputs and
• Fanout (over temperature range) is independent of the register operation. When OE is
– Standard outputs: 10 LSTTL loads HIGH, the outputs are in the high-impedance state.
– Bus driver outputs: 15 LSTTL loads The 374 and 574 are identical in function and differ
• Wide operating temperature range: –55℃ to 125℃ only in their pinout arrangements.
• Balanced propagation delay and transition times Device Information
• Significant power reduction compared to LSTTL (1)
PART NUMBER PACKAGE BODY SIZE (NOM)
Logic ICs
CD54HC374F3A CDIP (20) 26.92 mm × 6.92 mm
• HC types
CD54HC574F CDIP (20) 26.92 mm × 6.92 mm
– 2-V to 6-V operation
– High noise immunity: NIL = 30%, NIH = 30% of CD54HCT374F3A CDIP (20) 26.92 mm × 6.92 mm
VCC at VCC = 5 V CD54HCT574F CDIP (20) 26.92 mm × 6.92 mm
• HCT types CD74HC374M SOIC (20) 12.80 mm × 7.50 mm
– 4.5-V to 5.5-V Operation CD74HC574M SOIC (20) 12.80 mm × 7.50 mm
– Direct LSTTL input logic compatibility, CD74HCT374M SOIC (20) 12.80 mm × 7.50 mm
VIL = 0.8 V (max), VIH = 2 V (min)
CD74HCT574M SOIC (20) 12.80 mm × 7.50 mm
– CMOS input compatibility, II ≤ 1μA at VOL, VOH
CD74HC374E PDIP (20) 25.40 mm × 6.35 mm
CD74HC574E PDIP (20) 25.40 mm × 6.35 mm
CD74HCT374E PDIP (20) 25.40 mm × 6.35 mm
CD74HCT574E PDIP (20) 25.40 mm × 6.35 mm
CD74HCT574PWR TSSOP (20) 6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
Functional Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD74HCT574
SCHS183E – NOVEMBER 1998 – REVISED OCTOBER 2022 www.ti.com
Table of Contents
1 Features............................................................................1 7.2 Functional Block Diagram......................................... 10
2 Description.......................................................................1 7.3 Device Functional Modes..........................................10
3 Revision History.............................................................. 2 8 Power Supply Recommendations................................11
4 Pin Configuration and Functions...................................3 9 Layout............................................................................. 11
5 Specifications.................................................................. 4 9.1 Layout Guidelines..................................................... 11
5.1 Absolute Maximum Ratings........................................ 4 10 Device and Documentation Support..........................12
5.2 Recommended Operating Conditions.........................4 10.1 Receiving Notification of Documentation Updates..12
5.3 Thermal Information....................................................4 10.2 Support Resources................................................. 12
5.4 Electrical Characteristics.............................................5 10.3 Trademarks............................................................. 12
5.5 Prerequisite for Switching Characteristics.................. 6 10.4 Electrostatic Discharge Caution..............................12
5.6 Switching Characteristics ...........................................7 10.5 Glossary..................................................................12
6 Parameter Measurement Information............................ 8 11 Mechanical, Packaging, and Orderable
7 Detailed Description......................................................10 Information.................................................................... 12
7.1 Overview................................................................... 10
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2022) to Revision E (October 2022) Page
• Increased RθJA for packages: DW (58 to 109.1); N ( 69 to 84.6); PW (83 to 131.8)......................................... 4
Changes from Revision C (May 2004) to Revision D (January 2022) Page

• Updated the numbering, formatting, tables, figures, and cross-refrences throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC374 CD74HC374 CD54HCT374 CD74HCT374 CD54HC574 CD74HC574

CD54HCT574 CD74HCT574
CD74HCT574
www.ti.com SCHS183E – NOVEMBER 1998 – REVISED OCTOBER 2022
4 Pin Configuration and Functions
HC(T) 374 HC(T) 574

J, DW, or N package J, DW, N, or PW package
20-Pin CDIP, SOIC, or PDIP 20-Pin CDIP, SOIC, PDIP, or TSSOP
Top View Top View
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

CD74HCT574
5 Specifications
5.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage – 0.5 7 V
IIK Input diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA
IOK Output diode current For VO < –0.5 V or VO > VCC + 0.5 V ±20 mA
IO Drain current, per output For –0.5 V < VO < VCC + 0.5 V ±35 mA
IO Output source or sink current per output pin For VO > –0.5 V or VO < VCC + 0.5 V ±25 mA
Continuous current through VCC or ground current ±50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature range – 65 150 °C
Lead temperature (Soldering 10s) (SOIC - Lead Tips Only) 300 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 Recommended Operating Conditions

MIN MAX UNIT
HC types 2 6
VCC Supply voltage range V
HCT types 4.5 5.5
VI, VO DC input or output voltage 0 VCC V
2V 1000
Input rise and fall time 4.5 V 500 ns
6V 400
TA Temperature range –55 125 ℃
5.3 Thermal Information

DW (SOIC) N (PDIP) PW (TSSOP)
THERMAL METRIC 20 PINS 20 PINS 20 PINS UNIT
(1)
RθJA Junction-to-ambient thermal resistance 109.1 84.6 131.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 76 72.5 72.2 °C/W
RθJB Junction-to-board thermal resistance 77.6 65.3 82.8 °C/W
ψJT Junction-to-top characterization
51.5 55.3 21.5 °C/W
parameter
ψJB Junction-to-board characterization
77.1 65.2 82.4 °C/W
parameter
RθJC(bot) Junction-to-case (bottom) thermal
N/A N/A N/A °C/W
resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

CD74HCT574
5.4 Electrical Characteristics

TEST VCC 25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER (2) UNIT
CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 1.5 1.5 1.5
VIH High level input voltage 4.5 3.15 3.15 3.15 V
6 4.2 4.2 4.2
2 0.5 0.5 0.5
VIL Low level input voltage 4.5 1.35 1.35 1.35 V
6 1.8 1.8 1.8
High level output IOH = – 20 μA 2 1.9 1.9 1.9
voltage IOH = – 20 μA 4.5 4.4 4.4 4.4 V
CMOS loads IOH = – 20 μA 6 5.9 5.9 5.9
VOH
High level output IOH = – 6 mA 4.5 3.98 3.84 3.7
voltage V
IOH = –7.8 mA 6 5.48 5.34 5.2
TTL loads
Low level output IOL = 20 μA 2 0.1 0.1 0.1

voltage IOL = 20 μA 4.5 0.1 0.1 0.1 V
CMOS loads IOL = 20 μA 6 0.1 0.1 0.1
VOL
Low level output IOL = 6 mA 4.5 0.26 0.33 0.4
voltage V
IOL = 7.8 mA 6 0.26 0.33 0.4
TTL loads
II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 μA
Quiescent device
ICC VI = VCC or GND 6 8 80 160 μA
current
VIL or Three-state leakage
VO = VCCor GND 6 ±0.5 ±5.0 ±10 μA
VIH current
HCT TYPES
4.5 to
VIH High level input voltage 2 2 2 V
5.5
4.5 to
VIL Low level input voltage 0.8 0.8 0.8 V
5.5
High level output
voltage IOH = – 20 μA 4.5 4.4 4.4 4.4
CMOS loads
VOH V
High level output
voltage IOH = – 6 mA 4.5 3.98 3.84 3.7
TTL loads
Low level output

voltage IOL = 20 μA 4.5 0.1 0.1 0.1
CMOS loads
VOL V
Low level output
voltage IOL = 6 mA 4.5 0.26 0.33 0.4
TTL loads
II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA
Quiescent device
ICC VI = VCC or GND 5.5 8 80 160 μA
current
VIL or Three-state leakage
VO = VCCor GND 6 ±0.5 ±5.0 ±10 μA
VIH current

CD74HCT574
5.4 Electrical Characteristics (continued)

TEST VCC 25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER (2) UNIT
CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX
D0 - D7 inputs held 4.5 to
100 108 135 147 μA
at VCC – 2.1 5.5
HCT374
Additional quiescent CP input held at 4.5 to
100 324 405 441 μA
device current per VCC – 2.1 5.5
input pin
OE input held at 4.5 to
100 468 585 637 μA
VCC – 2.1 5.5
ΔICC (1)
D0 - D7 inputs held 4.5 to
100 144 180 196 μA
at VCC – 2.1 5.5
HCT574
Additional quiescent CP input held at 4.5 to
100 270 337.5 367.5 μA
device current per VCC – 2.1 5.5
input pin
OE input held at 4.5 to
100 216 270 294 μA
VCC – 2.1 5.5
(1) For dual-supply systems, theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specificationis 1.8mA.
(2) VI = VIH or VIL, unless otherwise noted.
5.5 Prerequisite for Switching Characteristics

25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER VCC (V) UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
HC TYPES
2 6 5 4
fMAX Maximum clock frequency 4.5 30 25 20 MHz
6 35 29 23
2 80 100 120
tW Clock pulse width 4.5 16 20 24 ns
6 14 17 20
2 60 75 90
tSU Setup time data to clock 4.5 12 15 18 ns
6 10 13 15
2 5 5 5
tH Hold time data to clock 4.5 5 5 5 ns
6 5 5 5
HCT TYPES
fMAX Maximum clock frequency 4.5 30 25 20 MHz
tW Clock pulse width 4.5 16 20 24 ns
tSU Setup time data to clock 4.5 12 15 18 ns
tH Hold time data to clock 4.5 5 5 5 ns

CD74HCT574
5.6 Switching Characteristics

CL = 50 pF, Input tr, tf = 6 ns
TEST 25℃ –40℃ to 85℃ –55℃ to 125℃
PARAMETER VCC (V) UNIT
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
HC TYPES
2 165 205 250
CL = 50 pF ns
tPLH, Propagation delay 4.5 33 41 50
tPHL Clock to output CL = 15 pF 5 15
ns
CL = 50 pF 6 28 35 43
2 135 170 205
CL = 50 pF ns
tPLZ, 4.5 27 34 41
Output disable to Q
tPHZ CL = 15 pF 5 11
ns
CL = 50 pF 6 23 29 35
2 150 190 225
CL = 50 pF ns
tPZL, 4.5 30 38 45
Output enable to Q
tPZH CL = 15 pF 5 12
ns
CL = 50 pF 6 26 33 38
fMAX Maximum clock frequency CL = 15 pF 5 60 MHz
2 60 75 90
tTHL,
Output transition time CL = 50 pF 4.5 12 15 18 ns
tTLH
6 10 13 15
CI Input capacitance CL = 50 pF 10 10 10 10 pF
CO Three-state output capacitance 20 20 20 20 pF
CPD Power dissipation capacitance(1) (2) CL = 15 pF 5 39 pF
HCT TYPES
tPHL, Propagation delay CL = 50 pF 4.5 33 41 50

ns
tPLH Clock to output CL = 15 pF 5 15
tPLZ, CL = 50pF 4.5 28 35 42

Output disable to Q ns
tPHZ CL = 15 pF 5 11
tPZL, CL = 50 pF 4.5 30 38 45
Output enable to Q ns
tPZH CL = 15 pF 5 12
fMAX Maximum clock frequency CL = 15 pF 5 60 MHz
tTLH,
Output transition time CL = 50 pF 4.5 12 15 18 ns
tTHL
CI Input capacitance CL = 50 pF 10 10 10 10 pF
CO Three-state output capacitance 20 20 20 20 pF
CPD Power dissipation capacitance(1) (2) CL = 15 pF 5 47 pF
(1) CPD is used to determine the dynamic power consumption, per package.
(2) PD = CPD VCC 2 fi + Σ VCC 2 fO CL where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply voltage.

CD74HCT574
6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test VCC Test

Point Point
S1
RL From Output
From Output
Under Test Under Test
CL(1) S2 CL(1)
(1) CL includes probe and test-fixture capacitance. (1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for 3-State Outputs Figure 6-2. Load Circuit for Push-Pull Outputs
VCC VCC
Output
Input 50% 50% 50% 50%
Control
0V 0V
tPLH(1) tPHL(1) tPZL(3) tPLZ(4)
VOH § 9CC
Output
Output 50% 50% Waveform 1 50%
S1 at VLOAD(1) 10%
VOL VOL
(1) (1) (3) (4)
tPHL tPLH tPZH tPHZ
VOH VOH
Output 90%
Output 50% 50% Waveform 2 50%
S1 at GND(2)
VOL §0V
(1) The greater between tPLH and tPHL is the same as tpd. (1) S1 = CLOSED; S2 = OPEN.
Figure 6-3. Voltage Waveforms, Propagation (2) S1 = OPEN; s2 = CLOSED.
Delays for Standard CMOS Inputs (3) tPLZ and tPHZ are the same as tdis.
(4) tPZL and tPZH are the same as ten.
Figure 6-4. Voltage Waveforms, Standard CMOS
Inputs Propagation Delays
VCC
90% 90%
Input
10% 10%
0V
tr(1) tf(1)
VOH
90% 90%
Output
10% 10%
VOL
tr(1) tf(1)
(1) The greater between tr and tf is the same as tt.
Figure 6-5. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs

CD74HCT574
3V 3V
Input 1.3V 1.3V Input 1.3V 1.3V
0V 0V
tPLH(1) tPHL(1) tPZL(1) tPLZ(2)
VOH Output VCC
Output Waveform 1
50% 50% 50%
Waveform 1 S1 CLOSED, 10%
VOL S2 OPEN VOL
tPHL(1) tPLH(1) tPZH(1) tPHZ(2)
VOH Output VOH
Output Waveform 2 90%
50% 50% 50%
Waveform 2 S1 OPEN,
VOL S2 CLOSED 0V
(1) The greater between tPLH and tPHL is the same as tpd. (1) tPLZ and tPHZ are the same as tdis.
Figure 6-6. Voltage Waveforms, Propagation (2) tPZL and tPZH are the same as ten.
Delays for TTL-Compatible Inputs Figure 6-7. Voltage Waveforms, TTL-Compatible
CMOS Inputs Propagation Delays

CD74HCT574
7 Detailed Description
7.1 Overview
The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-type flip-flops with 3-state outputs and the capability
to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the LOW to HIGH
transition of clock (CP). The output enable (OE) controls the 3-state outputs and is independent of the register
operation. When OE is HIGH, the outputs are in the high-impedance state. The 374 and 574 are identical in
function and differ only in their pinout arrangements.
7.2 Functional Block Diagram
7.3 Device Functional Modes

Table 7-1. Truth Table(1)
INPUTS OUTPUT
OE CP Dn Qn
L ↑ H H
L ↑ L L
L L X Q0
H X X Z
(1) H = high level (steady state), L = low level (steady state), X =

don’t care, ↑ = transition from low to high level, Q0 = the level
of Q before the indicated steady-state input conditions were
established, Z= high impedance state

CD74HCT574
8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

CD74HCT574
10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 8-Sep-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
5962-8974201RA ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8974201RA Samples
& Green CD54HCT574F3A
CD54HC374F3A ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8407101RA Samples
& Green CD54HC374F3A
CD54HC574F ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC574F Samples
& Green
CD54HC574F3A ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC574F3A Samples
& Green
CD54HCT374F3A ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8550701RA Samples
CD54HCT574F ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HCT574F Samples
& Green
CD54HCT574F3A ACTIVE CDIP J 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8974201RA Samples
CD74HC374E ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC374E Samples
CD74HC374M LIFEBUY SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC374M
CD74HC374M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC374M Samples
CD74HC374M96E4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC374M Samples
CD74HC574E ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC574E Samples
CD74HC574M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC574M Samples
CD74HCT374E ACTIVE PDIP N 20 20 RoHS & NIPDAU N / A for Pkg Type -55 to 125 CD74HCT374E Samples
Non-Green
CD74HCT374EE4 ACTIVE PDIP N 20 20 RoHS & NIPDAU N / A for Pkg Type -55 to 125 CD74HCT374E Samples
Non-Green
CD74HCT374M LIFEBUY SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT374M
CD74HCT374M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT374M Samples
CD74HCT574E ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT574E Samples
CD74HCT574M LIFEBUY SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT574M
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
CD74HCT574M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT574M Samples
CD74HCT574ME4 LIFEBUY SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT574M
CD74HCT574PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK574 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF CD54HC374, CD54HC574, CD54HCT374, CD54HCT574, CD74HC374, CD74HC574, CD74HCT374, CD74HCT574 :
• Catalog : CD74HC374, CD74HC574, CD74HCT374, CD74HCT574

• Automotive : CD74HCT574-Q1, CD74HCT574-Q1
• Enhanced Product : CD74HCT574-EP, CD74HCT574-EP
• Military : CD54HC374, CD54HC574, CD54HCT374, CD54HCT574
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 12-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC374M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
CD74HC574M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
CD74HC574M96 SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
CD74HCT374M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
CD74HCT574M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
CD74HCT574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
CD74HCT574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC374M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HC574M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HC574M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HCT374M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HCT574M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HCT574PWR TSSOP PW 20 2000 356.0 356.0 35.0
CD74HCT574PWR TSSOP PW 20 2000 356.0 356.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC374E N PDIP 20 20 506 13.97 11230 4.32
CD74HC374M DW SOIC 20 25 507 12.83 5080 6.6
CD74HC574E N PDIP 20 20 506 13.97 11230 4.32
CD74HCT374E N PDIP 20 20 506 13.97 11230 4.32
CD74HCT374EE4 N PDIP 20 20 506 13.97 11230 4.32
CD74HCT374M DW SOIC 20 25 507 12.83 5080 6.6
CD74HCT574E N PDIP 20 20 506 13.97 11230 4.32
CD74HCT574M DW SOIC 20 25 507 12.83 5080 6.6
CD74HCT574ME4 DW SOIC 20 25 507 12.83 5080 6.6
PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
6.6 5.85
6.4
NOTE 3
10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE 0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20
SYMM
18X (0.65)
10 11
(5.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20
SYMM
18X (0.65)
10 11
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC
10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1
13.0 2X
12.6 11.43
NOTE 3
10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4
0.33
TYP
0.10
0.25
SEE DETAIL A GAGE PLANE
1.27 0.3
0 -8 0.40 0.1
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC
20X (2) SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10 11
(9.3)
LAND PATTERN EXAMPLE

SCALE:6X
SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10 11
(9.3)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

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CD54HC374, CD74HC374, CD54HCT374, CD74HCT374, CD54HC574, CD74HC574, CD54HCT574,

CDx4HC374 High-Speed CMOS Logic Octal D-Type

(1) For all available packages, see the orderable addendum at

Changes from Revision C (May 2004) to Revision D (January 2022) Page

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC374 CD74HC374 CD54HCT374 CD74HCT374 CD54HC574 CD74HC574

4 Pin Configuration and Functions

HC(T) 374 HC(T) 574

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

5.2 Recommended Operating Conditions

5.3 Thermal Information

4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC374 CD74HC374 CD54HCT374 CD74HCT374 CD54HC574 CD74HC574

5.4 Electrical Characteristics

Low level output IOL = 20 μA 2 0.1 0.1 0.1

Low level output

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5

5.4 Electrical Characteristics (continued)

5.5 Prerequisite for Switching Characteristics

6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC374 CD74HC374 CD54HCT374 CD74HCT374 CD54HC574 CD74HC574

5.6 Switching Characteristics

tPHL, Propagation delay CL = 50 pF 4.5 33 41 50

tPLZ, CL = 50pF 4.5 28 35 42

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7

6 Parameter Measurement Information

Test VCC Test

8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC374 CD74HC374 CD54HCT374 CD74HCT374 CD54HC574 CD74HC574

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9

7.3 Device Functional Modes

(1) H = high level (steady state), L = low level (steady state), X =

10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC374 CD74HC374 CD54HCT374 CD74HCT374 CD54HC574 CD74HC574

8 Power Supply Recommendations

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11

10 Device and Documentation Support

11 Mechanical, Packaging, and Orderable Information

12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: CD54HC374 CD74HC374 CD54HCT374 CD74HCT374 CD54HC574 CD74HC574

• Catalog : CD74HC374, CD74HC574, CD74HCT374, CD74HCT574

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

Reel Width (W1)

Q3 Q4 Q3 Q4 User Direction of Feed

*All dimensions are nominal

TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

B - Alignment groove width

*All dimensions are nominal

20X (1.5) SYMM

LAND PATTERN EXAMPLE

SOLDER MASK METAL UNDER SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

NON-SOLDER MASK SOLDER MASK

6. Publication IPC-7351 may have alternate designs.