FIRST TERM

EXAMINATION
SIXTH SEMESTER [FEB. 2016]
(B.TECH]
MICROPROCESSOR AND
Time: 14 hrs.
MICROcONTROLLER (ETEE-310]
Note: Attempt Q. No. 1 1which is M.M.:30
91 Attempt any five. compulsory and any two more questions
from remaining.
Q.1Attempt any five:
Q.1. (a) State the priority of execution of (5x2)
signals. HOLD, RESET and INTERRUPT
Ans. Priority of execution are:
1 HOLD
2. INTERRUPT
3. RESET
Q.1. 6) Write a set of instructions to transfer
8085 microprocessor. logic 1 from the SOD line of
Ans. MVI A, OCOH
SIM
HLT
Q.1. (c) How much time is taken by the
microprocesser 8085 to
conditional CALL Instruction of 8085
microprocessor if condition is execute
Assume Microprocessor is running at 2MHZ? not true?
Ans. CALL instruction-9/18 T states

Ifcondition is not true 9 T states is used otherwise, 18 will be used

Given frequency-2MHz

T-1/P-05microsee
Time is taken by the microprocessor 8085=0.5*9 => 4.5 microsec
Q1. (d) State the function of TEST and LOCK signals of the 8086
microprocessor.
Ans.1 (d) Refer Q.9. (c) of End Term Exam 2016.(Page No. 48-2016)
Q1 e) Exrplain the LOOP instruction of microporcessor 8086 with suitable
ezamples.
Ans.
LOOP label Decrease CK. jump to label if CX not zero
Algorithm:
CX-CX-1
ifCX-Othen
junp
 else
nojump, continue LP
Example:
University-(B Tech)-AB Publisher 2016-3
9.2.(e) Write and explain a soflware
delay routine for 8085. (4)
include 'emu8086.inc Ans. To know how many T-States an
a T-State is one clock instruetion requires, and keeping in mind that
#make_COM# cycle long, we can caleulate the time
using the following formula:
Delay No. of T-States / Frequeney
ORG 100h
Example: If the speed of your microprocessor is 2 MHa then
MOV CX, 5 uses 7 T-States. Therefore the for a "MVIT instruction
instruction would require 3.5 u Seconds
label1: Now we can use a loop to produce a to complete
certain amount of tima delay
PRINTN T0op! See an example of a delay loop: in aprogram
LOOP labell MVI C, FFH 7 T-States
RET LOOP: DCRC 4 T-States
Q1. What are Logical and JNZ LOOP 10 T-States
Physical addresses? lHow the physical
are generated?
addrese
esses Here the first instruction
see
initializes the loop counter and is
Ans. Logical address is
contained in the 16 bit IP, BP, SP, BX, SI or requiring only 7 T-States. executed only once
known as the offset address or DI. It is als.
the effective address. also The following two instructions which is
The base inaide a loop that requires 14
segment address is contained in one of the 16 bit execute and is repeated 255 times until C becomes 0 T-States to
registers cS, DS, ES, SS. contents of the
segmentat We need to keep in mind though that in the last rotation of the
The physical address or the real address instruction will not loop, JNZ
jump to the address and so it requires only 7 TStates
the
base is formed by combining the offset
segment addresses. This address is 20 bit and rather than
the memory. is primarily used for the and the 10.
accessing of .Therefore, we must deduet 3 T-States from the total delay
get an
Physical Address Base delay calculation.
to
accurate
Q1. (g)Which among the Address *10OH + Logical Address.
To calculate the delay, we use the following formula:
and why?
MOVAX, [1000H] and following two instructions will be
Ans. Both instruction will MOVAX, [1001H]. executed faster TaiayTo.T
take
9.2. (a) Write a program for equal
time for Taeiaytotal delay: To= delay outside the loop; T= delay of the loop
8085 to generate
execution.
Ans. MVID, fibonacci series. Now using these formulas, we can caleulate the time delay for the above mention
COUNT; (4)
MVI B, 00; Initialize Initialize counter
example:
variable to store To-7TStates Delay ofthe MVI instruction
MVI C, 01; Initialize
variable to store
previous number
T=(14 x 255)-3 = 3567 TStates (14 TStates for the 2 instructions repeated
MOVA, B;: [Add two numbers] current number 255 times)
BACK: ADD C ; [Add two Now your microprocessor speed is 2 MHz. So we know
numbers]
MOVB, C; Current
number
MOV C, A; Save result
is now
previous number T (time for one T state) = VF
as a new current = h x 10 sec
DCRD;Decrement count number
= 5psec
JNZ
BACK;if count 0 go to BACK So now we have 3567 T-state so we will get 3567 x 5 p sec = 1.7835m sec of delay
HLT; Stop.
Q.3. (a) Explain the Align and DUP assembler directives. (2)
9.2 6) Write an intra
y15 address location5. segment direct JUMP instruetion tojump Ans. EVEN directive: This directive is used to Align the word boundary to

Ans. JMP SHORT Label

backward
(2)
next even address for faster access. Suppose we have a data segment named as

ds_segment, then:
JMP NEAR Label
DSsegment SEGMENT:
Shortjump rangel-127 <de 128) Numl db 05h
Long jump range(-32767<de+32768 Word1 dw 1234h
 Microcontroller
4-2016 Sixth Semester, Microprocessor and
I.P. University-(B.Tech)-AB Publisher 2016-5
Char db x; Location counter will point to 0004 when assembler reads no
statement.
next 1ORC, IOWC are /O read command and I/O write command signals respectively
These signals enable an 10 interface to read or write the data from or to the addressed
Prices DB5 DUP(?): An array of 5 bytes, after executing this LC will point to 0qu
h port. The MRDC, MWTC are memory read command and memory write command
which is an odd address.
EVEN: increment location counter to 000AH i.e. an even address signals respectively and may be used as memory read and write signals. All these
command signals instruct the memory to accept or send data from or to the bus. For
MyData DW 50 DUP(0): Array of 50 words will start from an even address. both of these write command signals, the advanced signals namely AIOWC and AMWTC
are available. They also serve the same purpose, but are activated one clock cycle
DS-segment ENDS:
earlier than the IOWC and MWTC signals, respectively
DB Defined Byte: DB declares a variable of type byte and reserves one locationin
memory for the variable of type byte. Q.3. (c) Design a microprocesser 8086 system having two 4K x 8 EPROM
and four 8K x 8 RAM. Avoid any foldback address. (4)
Example: num1 DB 15h, Char1 db A'
Ans. A system requires 16kb EPROM and 16kb RAM. Also the system has
numbers db 100 dup(0); Reserve an array of 50 words of memory and initialize All
one number of 8279, one number of 8251 and one number of 8254.
bytes with 00. 2 numbers of 8255,

Array is named as numbers. (8255 Programmable peripheral interface; 8279-Keyboard/display controller,

8251-USART and 8254
-

Timer). Draw the Interface diagram. Allocate addresses to

DUP stands for
duplicate mapped.
all the devices. The peripheral IC should be I/0
Q.3. (6)Drawthe timing diagram of memory wrile cycle in maximum mode The I/O devices in the system should be mapped by standard I/O mapping. Hence
configuration of 8086. (4)
decoders can be used to generate
separate chip select signals for memory IC and
Ans. The maximum mode system timing diagrams are also divided in two portions peripheral IC's.
as read (input) and write (output) timing diagrams. The
address/data and address/ 8) EPROM.
status timings are similar to the minimum mode. ALE is asserted in T1, just like .For 16kb EPROM, we can provide 2 numbers of 27G4(8k x
minimum mode. The only difference lies in the status signals used and the available 8) RAM.
control and advanced command signals. The fig. shows the same for the write operation. .For 16kb RAM we can provide 2 numbers of 6264 (8k x

The 8kb memories require 13 address lines. Hence the address lines A0-A12 are
T TI T T used for selecting the memorylocations,
decoder 74LS138
CLK UUUUL The unused address lines A13, A14 and Al5
are used as input to

decoder are tied to 10/

The logic low enables of this
One bus cycle (3-to-8-decoder) of memory IC. The
decoder is enabled for memory read/write operation.
Mlow) of 8085, so that this
ALE tied to appropriate logic levels permanently. The 4-
other enable pins of decoder
are
4 are kept for
select memory 1¬'s and the remaining
,-50 outputs of the decoder are used to
Active Inactve
Float future expansion.
ADD/STATUS XBHE S-S, The EPROM is mapped in the beginning of memory
space from
0000H to 3FFE

to FEFFFH.
space from C000
ADD/DATA
A-AXDataout D-D The RAM is mapped at the end ofmemory
ADS AD interfaced to the system. The chip-select
There are five peripheral IC's to be
AMWCor
AlOWcor
signals for these IC's are given through
another 3-to-8 decoder
74LS138 (/O decoder).

A13
decoder is A11, A12 and
The input to this
MWICor
Towcor and A15 are logically ORed and applied
to low enable
The address lines A13,A14
High of /O decoder.
DT/R
decoder is tied to
10/Mlow) signal of 8085, so that
DEN The logic high enable of I/O
read/write operation.
enabled for I/O
this decoder is

Memory Write Timing in Maximum Mode

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 8-2016 Sixth Semester, Microprocessor and
Microcontroller
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Resel Cik RDY
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As
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8086
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Fig. Maximum Mode 8086
The
significance of the
System.
pin. If IOB is MCE/PDEN* output depends
it acts as grounded, it acts as
master cascade enable to upon the status of the IOB
peripheral data enable used in the
used to issue two
control cascaded 8259A; else
multiple
interrupt acknowledge pulses to the bus
configurations.
INT pin is
interrupting device. interrupt controller or to an
 EIRST TE
FIRST TERM EXAMINATION (FEB. 2017]
eg SIXTH SEMESTER [B.TECH]
as MICROP CROPROCESSOR AND MICROCONTROLLER
to
ETEE-310]
Hrs.
M.M.130
ime:
1;
mto
m to No I is compulsory. Attempt anytwo from the remaing
Q.1.AttemptAny five.
1 Dy L)What istransparent latch and why is it necessary to use a lateh with
ernal such as LEDs? (2)
f bittpuAns.devices
wtput Atransparent latch is a storage element. It has an input, an output, and an
is active, the output transparently follows the
When the enable
e
lenes nabl or gate pin.
When the enable becomes inactive, the output freezes.
s o m e small del
delay).
(with
asaput result will
latch is necessary for output devices to return the result otherwise the
m
0.1.(6) The memory address of the last location of a 1K byte memory/chip is
tosappear

(2)
as FBFFH. Specify the starting address.
last location of 1Kbyte = FBFFH
mt Ans. As given
Number of register= 1K= 1*1024
Starting Address =FBFFH-03FFH=> F800H.
RET instruction is requires 4T states to
Q.1.c) Explain why unconditional 6T states for fetch. (2)
by bitch whereas conditional RET instruction requires
from Subroutine Unconditionally
Ans. RET: Return
subroutine to the calling program
Wit The program sequence is transferred from the
described below. The two bytes from the top of
othesed on the specified flag of the PSW as
program execution begins at the
new
usee stack are copied into the program counter, and
dress. RNZ
RET conditionally: RC, RNC, RP, RM, RPE, RPO, RZ,
is transferred to a
Example RC:-(Return if Carryis set) The program sequence
articular level or a 16-bit address if C=1 (or carry is 1)
Unconditional RET requires 4T states to fetch the calling address of the program.
doesn't require to check any condition. address of the
Whereas conditional RET requires 6T states to fetch the calling
fulfill. If condition is not true, it
grain, as it has to be wait till the conditionT-isstates.
ntinuesthe and thus requires fewer
sequence
directives used in 8086.
Q.1.d) Explain ASSUME and OFFSET assembler
(2)
to tell the assembler
Ans. ASSUME Directive The ASSUME directive is used
used for a specified segment. The 8086
at the name of the logical segment should bea Code
segment, a data segment, a stack
rks directly with only 4 physical segments:
ment, and an extra segment.
CS:coDE This tells the assembler that
the logical segment
Example: ASUME
the and should be treated
ed CODE contains the instruction statements for program
a code segment.
instruction which refers to
ASUME DS:DATA : This tells the assembler that for any
segment DATA.
d1n the data segment, data will found in the logical
 0 Available
1=Marked

I
 M i e r o c o n t r o l l e r

LP. University
Mieroprocessor
and
The
sity-[B.Tech. -AB Publisher 2017-5
MOD 111
instruction.
Semester,
Sixth (BXI, DL (4)
4-2017 code for
the MOV CS:
RM W 0 W-1 RM
Effeetive Address Caleulation
Construct
the binary
AL AX
MOD =00 MOD = 001
MOD 10
9.2.0b) MOV is
100010 000 O00 CBX+(5D
opcode
for
001 CL CX 001 (BX0+(DD (BX0+(SID D, (BXD+(6D+D16
Ans.
Converting Assembly Language 010 DL DX 010 (BP+(SI) BX+DD+D (BX0+(DID+Dis
Code
011 BL BX 011 (BP (DID (BP)+(SID+D, CBP)+(SD-D
Instructionsto Machine 100 AH SP 100 (SI
(BP)+(D) +D, (BP)+{DD+ Ds
REORM
OPCODE OW MOD 101 CH BP 101 (D1)
(SI) D (SD)+D16
110 DH SI 110 Direct Address
(DI)+D (DD D16
1 to 6 bytes 111 BH DI (BP) +
D, (BP)+ D 16
be coded with 111 (BX)
An
instruction can

three k i n d s ofinformation:
such as add,
subtract,
or
move
BX)+D (BX)+ D16
Byte 1
contains
operation Segment override prefix
specifies the Byte 1 Byte 2
field (6 bits) operand code format
Opcode destination
-

D i r e c t i o n Bit (D bit)
2 is
source
or
1
Opcode MOD REG RM
-
Register REG field in byte
operand in 100010DW
Tells the
register

to the REG field from

R/M 0 1
100010 0 0 00 0 1 0 11 1
1: Data flow to the R/M CS Register
the REG field
-

0: Data flow from 8-bit or

16-bit
data Opeode From DL Byte Reg DL BX]
Data Size Bit (W bit)
will be
performed
on
Memory No Disp
Machine Code = 2E8817H
-

operation
Specified whether the
0:8 bits
Q.2.(c) Explain the difference between LEA and
Ans. The MOV instruction
MOV instruction (2)
1:16 bits
two fields The MOV instruction is the most
Byte 2 has(MOD) - 2 bits important command in the 8086 because it moves
data from one location to another. It also has the widest
- Mode field (REG)-3 bits assembler programmer can use MOV vartety of parameters; so it the
Register field field) - 2
bits operand
understand. effectively, the rest of the. commands are easier to
field (R/M the f i r s t
-
Register/memory
the register for format:
is u s e d to
identify W 1
R E G field
W AX MOV destination,source
REG
AL CX MOV copies the data in the source to the
000 or a word. Sometimes
destination. The data can be either a byte
CL DX this has to be
determine from the operands whether a explicitly
001 stated when the assembler cannot
DL BX byte or word is being referenced.
010 BL The MOV instruction has a few
011 SP limitations:
AH An immediate value
100 BP
ds, 10)
cannot be moved into a segment register directly
(i.e. mov
CH SI
101
DH Segment registers cannot be copied directly Gi.e.
110
BH
DI A memory location cannot be
mov
es, ds)
the second operand copied into another memory location
111 field together specify aNumber, aDigit) i.e. mov
and 3-bit R/M
2-bit MOD field
Explanation CS cannot be copied to (i.e. mov cs,ax)
Code These limitations can be overcome
no displacement follows. using
purpose register as illustrated in the generalindirect
data
Memory mode, movement through a general
format given above.
00 Memory mode-8 bit Each of the possible values for the destination and
01 source is called a n address.
displacement follows The LEA instruction
Memory Mode., 16-bit format:
10 LEA register,.memory
displacement follows
Load Effective Address loads the
Register Mode no displacement specified register with the offset of a
memory
location.
R/M= 110, then 16-bit displacement follows The following two lines of code are identical:
Except when
 and
Microcontroller
L.P. University-{B.Tech.-AB Publisher
Microprocessor
2017-7
Sixth Semester, Mnemonics
6-2017
MVI D, 03H T-States
OFFSET aMessage
mov ax,
OFFSET is an
assemble Loop2:
LXI B, FFFFH
lea ax,aMessage indexed
because
DCXB 10
cannot be Loop1:
instruction
MOV to say 6
However, the would be impossible MOVA, C
directive, not an
instruction. It
hand, it is ORAB
aMessage+[BX]
On the other
mov ax,OFFSET is done at
assembly-time. JNZ Loop1
offset
calculation
10/7
since the DCRD
command
possible to issue the JNZ
leaax,aMessage[BX] Loop2 10/7

example:
Time delay given by Loopl (td1) =0.314568 second
lea dx,aMessage Approx. Total time delay (td)=3° tdl- 1 second
0.3.(c) Describe the effects on the Flags when the
Before each instruction, assuming all Flagsfollowing instructions
mov ah,09h
a rxecuted.
screen
a string to the e 0 (reset) and register
ofthe
=
int 21h outputting are:A DAH; B=
is the s a m e
standard
method of
situations,
making
ofisetting
contents
=
06H; C=9CH
that this in such MOV B,A
Notice to use the
LEA i n s t r u c t i o n (4)
lt is preferred
future.
DCR C
easier in
string
indicate
the status of various ADD B
which i n the following
Flags variables in the
CPU
among
others, IN 22
a set of used,
The flagsand
are
of the CPU.
Flags are
components
RAL
calculations

Ans. MOV B, A; B-DAH

contexts:
t o indicate errors DCR C; C=9BH
calculation

t o indicate
the sign ofthe last operations
ADD B;A=B4H&CF=1
t o enable a carry
during arithmetic IN 22; A=XX, as we don't know the content
of input port address 22 data.
state of th.
e RAL; A-01H&CF-0
for debugging certain tasks based
on the current
instructions perform Q4.(a) At a particular instant, the data in certain registers of the 8086 are as
A number of C237. Displacement
=
below: (2)
flags.Determine the effeetive SI 2A9B,
address (if applicable) resulting from the.
(3
=
=
637D, AX=1234H; BX = 3456H; CX= 10 H; SI =5678 H; DI=ABEFH; BP=CDEFH; Cs
Q.3.(a)
Given that: BX e
9087H;
mode: DS=9035 H; ES = 6798H; SS-909THL Ifnow the instruction MOVSBis executed
the addressing
registers and (2) Direct
by the processor state clearly what happens in the memory. Also indicate what
(1) I m m e d i a t e (4) Based Indexed
data are left in the above registers.
BX
(3) Register using Assume D flag is set
address is used
Ans. () No effective instruction itself Ans. MOVSB:copies contentsof byte givenby DS:SI into ES: DI
effective address
is given in the
i )Direct Direction Flag = 0; Forward processing Lot R)
used
(ii)No effective address is DF-1; Backward processing ( Rto L
Giv)BX+SI = 8E18H

produce a delay of 1 second. Consider the 808 Physical Address of source DS:SI =959C8H
ALP to Physical Address of destination ES: DI = 7256FH
9.3.b) Write an
clocked at 5 MHz. Here DF = 1 & CX = 10, That means 10 bytes of data are moved from 959C8H to
cannot be used to generate 1 sectime delay,So wee 7256FH
Ans.In8085 singleregister
a loop within loop
a technique:
to use time delay using and every time DF =1
Given time delay= 1
second Q4.b) Design a microprocessor 8086 based microcomputer system having
8085= 5MHz 4 chips of 4k RAM. 2 chip of 2Kram, 1 input device, and 1 output device. The I0
Frequency af
Time period of 8085= 0.2usec
devices are interfaced in memory mapped 10. The memory map notshould
have any fold back addresses. Give the complete memory map of this
LPto genérate 1 sec delay (6)
mierocomputer system.
 Microprocessor
and Microcontroller
Sixth Semester,
8-2017

Ans.
RAM 16 K RAM
Four chips of 4K
=

KRAMM
Two chips of 2K RAM=4
lines: 2 x 210 =Ap-A3
16 K RAM address
lines: 24 x 210 =Ag-Au
4K RAM address
Table Memory MapP
Ap A As A As As A A A
A A Ap As A Au Au Au| A 1 11 t
Address
1 1 11 1 1 1 1 1 111
FFFFF 1 1 1 0 0 016 0 00 0 0 0 0 0 0
POO00 K RAM 1

FBFFF
FB000

A-As CS2
CS,
Odd
16K x 8
Even
16K x 8

Do-D

CS,CS, =AzAg Ar4

A-A
CS3
5CS o0 Even
16K x 8
Odd
16K x 8

CSCS, =0 1 1 D,-D

A-A1

Even Odd
4Kx 8 4K x 8

D-D

Q4.(c) Consider the Instruction

2010H JUMP Disp
What is the value of Disp to go to the memory location 2005H.
ns. 2010H JMP 2005H
 FIRST TERM EXAMINATION (FEB. 2018]
SIXTH SEMESTER [B.TECH)]
MICROPROCESSOR AND MICROCONTROLLER
Time: 1hrs.
[ETEE-3110]
M.M.:30
Note: Q.No.I which is compulsory. Attempt any two questions from the rest.
Q.1. (a) Write the instructions to move value 5FHin memory location 3000H
using indirect addressing mode in 8085 microprocessor: (2)
Ans. LXIH, 3000H
MVI A, 5FFH
MOV M, A
HLT
Q. 1. (b) Explain the concept of
Ans. Memory segmented memory in 8086? (2)
Segmentation in 8086
Segmentation is the process in which theMicroprocessor
main of the computer is divided
into different segments and each segment has its ownmemory
base address. It is basically used
to enhance the speed of execution of the
fetch and execute the data from the
computer system, so that
processor is able to
memory easily and fast.
The Bus Interface Unit (BIU)
contains
(mentioned below) called as Segment Registers.four 16 bit special purpose registers
Code segment register (CS): is used for
segment of the memory, where the executable addressing memory location in the code
is stored.
Data segment register (DS): program
the data is stored.
points to the data segment of the memory where
Extra Segment Register (ES): also refers to
another data segment in the memory.
a segment in the memory which is
Stack Segment Register (SS): is used for
memory. The stack segment is that segment of
addressing stack segment of the
memory which is used to store stack
data.
Q.1. (c) Explain the function of ALEpin of 8085. (2)
Ans. ALE-Addres latch enable signal. This is used to demultiplex (latch) the (LSB)
address and data when it goes high.
Q.1. (d) What is wrong with MOV 1000H, BX instruction?
(1)
Ans. In this example destination is a data value, which can't
be possible.
Correct answer: MOV [1000], BX
or

MOV 1000, [BX]

Q1. (e) Explain SCASB instruction with example. (2)
Ans. The SCAS instruction is used for searching a particular character or set of
characters in a string. The data item to be searched should be in AL (for SCASB), AX
forSCASW) or EAX (for SCASD) registers. The string to be searched should be in memory
and pointed by the ES:DI
(or EDI) register.
1 . Explain the function of READY pin in 8085. (1)
Ans. Ready-This signal is used to delay the microprocessor Read or write cycle
Lll a
slow responding peripheral is ready to send or accept data.
2. (a) Draw and explain the timing diagram of MVIA, 32H instruetion. (5)
hs. iming Diagrams for MVIA, 32H. As shown in Fig, the instruction needs two
Deriodcles. The first machine cycle is OpCode fetch. It takes 4 T-states (4 clock
periods). The second machine cycle is a memory read which takes 3 T-states. The
ction cycle takes 7 T-states.
 M, (Memory read) LP.
M,(Opcodefetch)
GSUME Directive-The
ASS
of the logical
natly with
University-[B.Tech -Akash
ASSUME directive is Books
segment should
only 4 physical be used used to tell 2018-3
CLK an extra segment
segments: Code for
specified the assembler that
a
Example: ASUME CS:
aamed CODE contains
a
segment, a data segment. The 8086 works
segment, a stack
the
the ins CODE; This tells the
20H UnspecilieX 20H
High-order
memgnyaddresss
as code
a
segment.
ASUME DS:
instruction statements assembler that segment,
DATA; This tells the for the the logical
program and should besegment
to a data in
Low-Order the data
Low-Order
ono0H 01H --- (32H|data EQU
Each time Directive:
segment, data willassembler that for any treated
3EH Opcode the The EQU found in the instruction
with the value assembler finds thedirective logical whieh refers
given names intothegive namesegment
Memory addres Memory address is used
or a DATA.
MET another Equate symbol. The value
declared
to
some value or
The BYTE anywhere
can be in
the program, it will replace symbol.
THISfollowing operators can also
above or below.range 0 through 65535 the mame
and it can
Opcode iOIM = Ss s,-tatus line THIS WORD be used to be
Status ibM - 0 SS, Tetca declare an Equate:
satus ine THIS DWORD

nservedvariable-declared
A

address withit
at that
or Space reserved for it infor inDB,
a
DW, or DD
RD the .COM fle. directive-has
the .COM But an
Equate doesaddress
Example: an
file. and
until the instruction MV not have anhas space
in the system bus A-Byte EQU THIS address
Here is description of what happens
will explain a generic microprocessor
rather than 8085): DB 10 BYTE
32H is executed (again I address 2000H into the addresSbu
loads the memory A_vword EQU THIS WORD
TheProgram Counter DW 1000
machine cycle.
during Tl of the Op. Code the memory location 2000p
locates and identifies A_ dword EQU THIS
The address decoding system the MEMR-signal (Read) whichlas DD 4294967295 DWORD
Control unit produces
A t T2, the Timing and time the memory places the Opcode 3EH Buffer Size EQU 1024
this window of
during T2 and T3. Duringdata bus. Buffer DB 1024 DUP (0)
location 2000H into the Register then into od
the Opcode in the Iastruction
the Opcode it feede ptr EQU $
system places
The operating
Instruction Decoder.
When the Instruction
Decoder
and Control Unit.
decodes
The fetch operation is completed Q.3.1(a) Explain all;actually
the points to the
addressing next byte after the
decoded signal into the Timing Addressing i1smodes: 1lhe modes of 8086 with suitable
ith
1024th byte in buffer.
T3. method by which address of
instruction called as addressing example.
incremented to 2001H.
Tmmediate source of data is (5)
T h e Program Counter is secondbyte which contai mode of
and Control unit
finds out that a ntam nstruction addressing
is given alongw mode (LAMD: If
gwith instruction, then8/16
source. given
During T4, the Timing address 2001H). the bit data required
the data needs to be read
(i.e. Example: 1. MOV AL, 75H it is for
called immediate executing the
T h e second machine cycle
is Memory Read cycle.
Counter loads the address20018
2. MOV BX,
7506 H; mode. addressing
A t the T1 of
cycle the Program
the 2nd machine o
Direct 7506 H-BH BL
addressing mode (DAM):
into the address bus. the memory location 2001H bitB.A. of
PAof
location teAMD:
memory location
this memory 1s
If8/16 hit data is
If 8/16 bit
locates and identifies mode instructions.5en given alongwith the present in memory
the i 1present alongwith instruction,
a
and 16
The address decoding system MBEMR lasts duringn addressing8
signal which then it is called direct
and control unit produces Example: MOVAL, (9106H]
A t T2 the Timing
the data 32H is placed
into the data bus thenint
and T3. During this window of time 3. Register direct
addressing
the aveeutine (RDAM): If 8/16 bit dats
instruction, mode
the MPU.
the data 32H is stored
into the accumulator. the instruction
the instruction,
is
esent
alongwith in register and f8/16
the name of
data
present register required for
During the rest of T3, directives with
assembler
examplelongwith then it is called RDAM instruetion. register is given
DB, ASSUME and EQU Example: MOV CX, BX
Q2. (b) Explain: 4. Register indirect
BYTE-2-BYTE variable -ABYT and the E.A. is addressing mode (RIAM):
Ans. DB-The DB
directive is used to declare
a
present in a register, then it is called If the data is present in memory
RIAM instruction.
is made up of 8 bits. BA=[BX)/SI) ADI)
Declaration examples: Example: MOV CX, BX
Bytel DB 10h 5. Register relative addressing mode
max. possible for a
BYTE cation and the EA = (RRAM): Data is present in
Byte2 DB 265; OFFh, the
Return, terminator BYTE
[BXVBPVSIVDIJ+
Example: MOV CX, 97H (BPI 8/6 bit displacement. memory
CRLF DB ODh, 0Ah, 24h; Carriage
 Sixth Semester, Microprocessor And Microcontroller
4-2018
L.P.
6. Base index addressing mode (BIAM): Data is present in meme
ory location
University-(B.Tech J-Akash Books 2018-5
the EA = [BXVBP] + [SI/DI] The 8085 has fivehardware interrupts
Example: MOV CX, IBX) (SI] d) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (6) INTR
7. Relative base index addressing mode (RBIAM): EA, = [BX/BD
. +8/16 bit displacement Interrupt Vector address
Example: MOV AH, 1907H [BXIDI RST 7.5
MOV DX, 8AH[BPI[SI] is used the relative base, index addressing mode 03CH
8. Implicit addressing mode (IPAM): Ifaddress of source of data as well a RST6.5 0034H
fixed then operand is given alongwith the instd RST5.5 002CH
truction
no
of destination of result, are

Example: CLD, DAA, STD TRAP 0024H

and their vectored loo.
Q.3. (b) Explain different interrupts of 8085 TRAP:
What is a non-maskable interrupt? oeati This interrupt is a non-maskable
interrupt. It is unaffected by any mask or
Ans. Interrupt Structure in 8085. interrupt enable.
device to the processor, to requ TRAP has the highest priority and vectored interrupt
Interrupt is signals send by an external quest
processor to perform a particular
task or work. *TRAP interrupt is edge and level triggered.
Eered. ThisThis means TRAP must go
that the TRAP
means that
used for high and remain high until it is ace go
in the microprocessor based system the interrupts
are
Mainly In sudden power failure, it
transfer between the peripheral and the microprocessor. executes a ISR
and send the data from main memory
The processor will check the interrupts always at the
2nd T-state of last ma to bacp memory.
The
signal, which overrides the
TRAP, is HOLD S1gnal.
cycle. nceives HOLD and TRAP at the
at
time fthen HOLDsignal.
same time
the same If the processon
G.e., If
is recognized first processon
A
send the INTA (activeu reP is reeooniga
I f there is any interrupt it accept the interrupt and and then
signal to the peripheral. .There are two ways to clear TRAP
The vectored address of particular interrupt
is stored in program counter 1, By resetting interrupt.
microprocessor (External
executes an interrupt service
routine (ISR) addressed in pro signal)
The 9. By giving a high TRAP
counter
processor
ACKNOWLEDGE Internal signal)
RST 7.5: The RST T.5 interrupt is a maskable
I t returned to main program by RET instruction. .It has the second highest interrupt.
It two types of interrupts. priority.
Types of Interrupts: supports Software
.It is edge sensitive. 1e.
Input goes to high and no need to
Hardware i t recognized.
maintain high state until
Software interrupts: instructions. These instructions areeins.
inse
Maskable interrupt. It is disabled by,
are program 1DI instruction, 2.
The software interrupts
in a program. Enabled
System or processor reset; 3.
by EI instruction. After reorganization of interrupt;
locations
at desired from RSTO to RST 7. The vector ad
The 8085 has eight software interrupts RST 6.5 and 5.5:
for these interrupts can be
calculated as follows. ae RST 6.5 and RST 5.5 both are level
Interrupt number *8
= vector address
high until it recognized. triggered..ie. Input goes to high and stay
For RST 5, 5 * 8 = 40 28H Maskable interrupt. It is disabled by,
RST 5 is 0028H DI. SIM instruction; 2. System or processor
Vector address forinterrupt reset;
The Table shows the
vectoraddresses of all interrupts. .Enabled by EI instruction. 3.After reorganization of interrupt.
Interrupt Vector address The RST 6.5 has the third priority whereas RST 5.5
0000H
INTR: has the fourth priority.
RSTO .INTR is a maskable interrupt. It is disabled by,
RST 1 0008H DI. SIM instruction, 2. System or
RST 2 0010H interrupt.
processor reset. ;3. After reorganization of
0018H Enabled by EI instruction.
RST 3
RST4 0020H Non-vectored interrupt. After receiving INTA (active low) signal, it has to supply
0028H
the address of ISR.
RST5 I t has lowest priority.
0030H It is a level sensitive
RST 6 interrupts. i.e.
maintain high state until it recognized. Input goes to high and it is
necessary to
RST 7 0038H
The following sequence of events
occurs when INTR
1. The 8085 checks the status of signal goes high.
INTR signal during execution
Hardware interrupts: and placinganapprop of each instruction.
initiates the hardware interrupts 2.If INTR signal is high, then 8085
An external device active low interrupt complete its current instruction
and sends
signal at the interrupt pin
of the processor.
aninterrupt servicen
acknowledge signal, if the interrupt enabled.
is
is accepted then the processor executes
I f the interrupt
 Microcontroller

And
Microprocessor

I.P University-(B.Tech-Akash Books

logic places an
instru
Semester,
Sixth
additional e
external
6-2018 signal,
to the
acknowledge instruction,

the addition Tnterrupttype Trigger 2018-7

3. In response bus. In
the case of multibyte
by the
8085 to
transfer

bytes Priority MaskableVector address

OPCODE on
the data generated
TRAP
Edge and level
cycles a r e RST 7.5 No
Edge
structionon
of next instructio
machine
acknowledge
the
address
RST 6.5 2nd 0024H
into the microprocessor
the 8085
save
Level Yes 003CH
the
instruction,
RST 5.5 3rd Yes
4. On receiving instruction.
Level 4th 0034H
received INTE Level Yes
stack and execute
6.5 and RST 5th 002CH
RST 7.5, RST Yes
SIM and RIM
for interrupts:
additional
masking facility for prioity Edge/Level
T h e 8085 provide instruction.
RIM 2 ST
using SIM instruction.
be read by
executing a Vector iocation
can interrupts can 7.5
T h e status ofthese
interrupts

of
6.5 and RST
5.5
RST 7.5, RSTand then executing IM instruction RST
7.5 internupt Reset CLR O O03CH

T h e masking
or unmasking
8-bit data to
accumulator
3 RST recognizedhoco
moving a n S.5 O038H
performed by below. O034H
data is shown
T h e format ofthe 8-bit Do And

D D D D,
D, DD R7sMSEM7.5|M6
RST
Oa30H
soD/SDEX 5/M5.5 002CH
RST 5.5 mask Mask
RST6.5 mask E 1- TRA O024H
O028H

Serial output data RST 7.5 mask

Reset Q
Serial data enable
If, SDE 1, D,
= bit
Don't
care
Mask set enable
If, MSE =0, Do. D,
5 INTR reeiseORR Interupt Get RST
0020H
line enable FA O018H
send to SOD Code
is and D2 are ignored if. 0010H
ifSDE =
0, bit D, is From ext O008H
MSE. 1, mask is set. 0.4.
uptorst
(a)Write an
assembly HW
ten 8085language program to generate oO0OH
ignored Reset RST 7.5 f terms using
If R 7.5 = 1:RST 7. Ans. MVI D, OUNT; instructions.
Initialize Fibonacci series
is not allowed.
MVI B, 00, Initialize counter (5)
If R 7.5 =0: RST 7. variable store previous number
T C. 01; Initialize variable to
is allowed. to store
MOVA, B;[Add two numbers current number
BACK: ADD C; [Add two numbers]
acCumulator
accumulator
in
loaded in
Format of 8-bitdata to be
sim
instruction
MOV B, C; Current number is now
Fig. before executing
accumulator after exeetr previous number
MOV C, A; Save result as a new current
can be read from number
pending interrupts DCR D ; Decrement cóunt
The status of whiach
in accumulator, JNZ BACK; if count0 go to BACK
data is loaded
RIM instruction. executed an 8-bit
instruction is
When RIM HLT; Stop.
as shown
in fig. O 4(b Write an
can be interpreted
DA
D
D3 D D assembly
stored at location 2000of language program to find
D
D D data
segment. Also store thesquare of 16-bit
result at location
a

IE M7.5|M65 M55 3000H.

Ans.
siD 175 18s 155 Mask status of
LXI
LXI D,
H, 2200H: Initialize lookup table pointer
2000H : Initialize source memory
(5)

RST 5.5 LXI B,

pointer
3000H: Initialize destination memory
Serial Input Data
Mask status of BACK: LDAX D: Get the number pointer
RST 6.5 MOV L, A : A point to the square
Mask status of
Interrupt pending
status ofRST 7.5 RST 7.5 MOV A, M: Get the square
J-O
STAX B: Store the result at
Interrupt pending Interrupt 1 interruptsare enab
Enable Flag 0 = Interrupts are disa INX D: Increment source
destination
memory location
status of RST6.5 memory pointer
INX B: Increment destination
Interruptpending memory pointer
status of RST 5.5 MOVA, C CPI 05H: Check for last number
JNZ BACK: If not
repeat
HLT: Terminate program execution
 FIRST TERM EXAMINATION [FEB. 20191
SIXTH SEMESTER [B.TECH
MICROPROCESSORS AND MICRO
CONTROLLERS (ETEE-3101
Time: 1 hrs. MM:S
Note: Attempt all questions. Internal choice has been indicated
for thefollowing instraetions
Q.1. (a) Identify the types of addressing modes 23
of 8085.
(i) MOVA, M Cii) LXI H, 16 bit add.
Gi) ADI 06H iv) CMA
iE) Immediate addiressing n
Ans. i) Register Indirect addressing mode
(iii) Immediate addressing mode iv) Implicit addressing mode
(23
Q.1. (b) Discuss the functions of following signals of 8086.
INTR, NMI, TEST AND BHE
Ans.INTR: It is available at pin 18. It is an interrupt request signal, wme is
sampled during the last clock cycle of each instruction to determine it the processor

considered this as an interrupt or not.

17. Itis anedge
NMI: It stands for non-maskable interrupt and is available at pin
triggered input, which causes an interrupt request to the microprocessOr
TEST: This signal is like wait state and is available at pin 23. When this s a i
ishigh, then the processor has to wait for IDLE state, else the execution contimus
BHE: BHE stands for Bus High Enable, it is available at pin 34 anduseditoinieate
the transfer of data using data bus D8-D15. Thi_ signal is low during the irst ftoede
cycle, thereafter it is active.
(2
Q.1. (c) Explain the flag registers or PSW of intel 8086.
Ans. Flag Registers: It consists of 5 flip flop which changesits status aecomingto
the result stored in an accumulator. It is also known as status registers.IEiS ennnerte
to the ALU.
There are five flip-flops in the flag register are as follows:
L. Sign (S) 2.Zero (z) 3.Auxilliary carry (AC)
4. Parity (P) 5. Carry (C)
The bit position of the filp-flop in flag register is:

D DD DD D D D
S Z X AC X PXCY
All of the three flip flop set and reset according to the stored resultin the acmumuiator
1.Auxilliary carry AC)-If any carry goes from D3 to D4 inthe output then itis sef
otherwise it is reset.
2. Carry (C) - If the result stored in an accumulator generates a carryinits fnal
output then it is set otherwise it is reset.
3. Parity Flag (PF): This flag is used to indicate the parity ofresult. Flower arder
number of 1's, the Parity Flagis set to ane and for add
8-bits of the result contains even reset i.e. zero.
is
number of 1's, the Parity Flag
4.Zero Flag (ZF): It is set to one; if the result of arithmeticor logical operationis
Zero else it is reset. ofnumber is indieated by
5. Sign Flag (SF): sign magnitude format the sign
In
is set to ane
sign flag
MSB bit. If the result of operation negative,
is
 and Microcontrollers
2-2019 Sixth Semester,
Microprocessors
I.P.University-(B.Tech -Akash Books 2019-3
and flagStatus
ag Status as
1 . (d) Identify the contents
instructutions are excecuted.
of accumulator following(3) Timing Diagrams for MVIB, 05H. As shown in Fig, the instruction needs tow machine
wcles. The first machine cycle is Opcode fetch. It takes 4 T-states (4 clock
MVIA, 7FH The periods).
ORA A sCond machine cycle is a memory read which takes 3 T-States. Teih instruction
cycle
takes 7-T states.
CPIA2 H
Ans. MVIA, 7FH; A=7FH Here is description of what
A=FEH
happens in the system bus until the instruction
ORA A; MVI B, 05His executed (again I will explain a
CPI A2H; A=5CH
The Program
generic microprocessor rather than 8085):
5CH & Flag status CF=0, AC=0, P=1, S=0 and Z= Counter loads the memory address 2000H into the address bus
Content of Accumulator
=

ALP to find the smallest

number from the given series 9F, during T1 of the Opcode machine cycle.
Q.2.(a) Write an
5D and 6E. The address
Ans.
6)
2000H.
decoding system locates and identifies the memory location

Label Instruction Comments At T2, the Timing and Control unit produces the
MVIA, 9FH; Loads Accumulator with 9FH
during T2 and T3. During this window of time the MEMR-signal (Read) which lasts
MVI B,5DH; Loads register B with 5DH location 2000H into the data bus. memory places the Opcode 3EH from
Loads register C with 6EH
MVI C, 6EH; The operating system places the
CMP B; Compares B with A the Instruction Decoder.
When the Opcode in the Instruction Register then into
JCjump1:; On no carry jumps tojumpl: the decoded signal into the Instruction Decoder decodes the
MOVA, B Moves content of B to A in T3. Timing and Control Unit. The fetch Opcode
it feeds

Compares C with A The Program

i1soperation completed
During'T4, theCounter
Jumpl: CMP C; is incremented to 2001H.
JCjump2: On no carry jumps to jump2: Timing and
Moves content of C to A the data needs to be Control unit finds
MOVA, C; The second machine address 2001H). out that a second byte which contains
read (i.e.
jump2: STA 4200H Stores content of A to memory location 4200H cycle is
HLT Terminatesthe program
At the Tl of
the 2nd machine Memory
into the address bus.
Read cycle.
cycle the Program
9.2. b) Explain the various hardware interrupts of intel 8085 microprocessor Counter loads the
.The address
decoding address 2001H
Ans. Refer to Q.3.0h),
4) 2001H. system
locates and identifies the
First Term Examination 2018. (Page No. 4-2018) At T2 the Timing and control unit memory location
OR
Q.2. (a) Draw and explain the timing diagram of MVIB, 05H. an aT3.During this window of produces MEMR signal
(5) time data 32H is
the which
theMPU
placed into the datalasts
Ans.
.During the rest of"T3, the data
during T2
bus then into
M, (Opcode fetch) M, (Memory read)
o (b)If after 32H is stored
executing the into the
CLK theaccumulat then RIM
instruction 69H accumulator.
indicate, the status data is
Ans. of
different signals. transferred into
RIM Instruction (2)

DLow-Order 20H TUnspecifie 20H High-order

memoy address D,
DD,D, D D
Low-Order
SID 17.5 16s |155| 1E D
O0OH -06HOpcode .--01H 05Hdata
AD
AT
Memory addres Memory address M7.sM6.sMs.s
SeralInput Data

laterrupt pending Mask status of

Status 1/M status of R$T
7RST 5.S
= 0.
S& S, fetchOM = So& S,= status line 75 Mask status of
satus ine Interrupt pending
S2atus of R$T 6.5 RST6S
Mask statas of
RD lnterrupt pending RST 15
S2us of RST 5.5 atesrup
Enable nternupta ate enab
Flag0inservupts
ae disa
 Microeontrol
Semester,
Microprocessors
and
LP.University-1B.Tech-Akash Boeks 2019-5
4-2019 Sixth

RIM-69H =01101001 IE=1dnterruns. AX

I6.5=1Pending),15.5=0, Cs
SID-0, 175-1(Pending),
(unmasked),
and M5.5=1 (masked)
enatle), CX
75=0(urmasked),
M6.5-0
each of One and-Three Byte
Byte, Two Byte and SS DX
92. (e) Give two examples
DS BX No DISPLACEMENT
Instructions. (3) ES 18-BIT DISPLACEMENT
Ans. FS BP
instructions of S085 according to length GS SI
Grouping of

Ex: MOV AX, ISI-08H]

ADD DX, IDI+1006H)

TwoByte Three Byte Based-indexed Addressing Mode

One Byte instruction
instruction
(threeword)
instruction
(Oneword)
(Twoword)
Opcode is 1 byte
Displacedaa (Constant)
DisplacementPoints to first address of
Opcode is 1 byte operand is 2rd & 3 Base Regster Contains Matrx column
Opcode & operand is 2nd Number

operand both bytelgenerally 8-bit bytelgenerally 16-

in 1 byte bit address or
data) index Regster Contains Matri Row
data) Number (Variable)
Eg: MOV A.B Eg: LXI HC588H Regardess df using Si or Di
Eg ADI 88H when Base Register is BX
ADD M STA D5FCH
SUI FCH
DS BX +
(Sl
PA or Di)+ Displacement
3.(a) Explain Based, Indexed, Based-Indexed addressing modes ofR0ge
4)
When Base Register is BP
Microprocessor with suitable
examples. PA SS BR+(SI or Di)+ Displacement
Ans. Base Resister Addressing Mode
mode, contents of base register is added
toaddres Trese are
detaut segments and
addressing
In base registerobtain ceament-Overmide Prefir Changes them
effective address.
part ofinstruction to
modeenceptthe register now iscalled as
It is similar to theíndexed addressing
Ex: MOV AX, [BX+SI+08H]
base instead of indez address.
ADD DX, BP-DI+1006H]
thebeginning base Connect 128K
The base register hold 03. (b)
word =
(128K 16) RAM with
The address part of instruction
holds the offset. ocessor, ssume suitable address. system lines of 8086
the base changes Ans. Memory capacity = 128 K word = 256K Byte (6)
Offset remains same, numberisthe memory
When the offset is added tothe base register theresultant 128 Kbyte for even Memory Bank
will be placed.
location where the operand 128 Kbyte for Odd Memory Bank.
Ex:MOVAX, BX+08H Address Decoding Table
contents is added to a
ADD DX, [BP-1006H
cal Total Even Binary Address
Mode: An INDEX register's
Index addressing
EAX, TABLE[ESI)
offset Example:ADD address address
AAy A AAAA A A A, A A, A AA, A, A, AA
DISPLACEMENT to form theoperands presentin memory location 6K00000 000000 0,0 0 0 0 0 0
toexecute aninstruction is 0000 oo00 o0
00
The 8/1632 bit data required obtained by addingthree
contents:
andeffective address of
that memory location is 2AMFFFF 3FFFE0 0i1 1 1 1 111 1111 11111 10
of base register.
L The bit content
content of Index Register Decoded
2. The 32 bit A, to A address pin of memory
3. Displacemment for X
 IP University-[B.Tech-Akash Books
and Mieroeontrollers
and Micro
i e r o p r o c e s s o r s

microprocessor.
Semester,
diagram of8086
shows the internal block the bus interface
Sixth
6-019 Following figure funetional parts,
is divided into two independent
The 8086 CPU
or EU.
or BIU,
and the execution unit addresses on the
buses for the
unit all data and reads
BIU handles
Interface Unit: The instructions from
memory,
The Bus addresses, fetches
as it sends out
unit such
execution
as writes data
to ports and memory.
and as well instructions
data from ports memory to fetch
RAM unit (EU) tells the BIU where
Unit: The execution
A-A 128 Kx8 The Execution instructions
executes
ODD
or data from,
decodes instructions, and o r system, instruction
evEN micraproceSsor BANK execution unit are control cireuitry
NA The functional parts of the
unit (ALU). decoder in the EU
decoder, and Arithmetic logic operations. A
various internal o r external
circuitry to perform different internal
Control from memory to generate which
translates instructions fetched EU has a 16-bit ALU,
fo- control signals that required performing
the operation. The
subtract etc. and logical
operations
D-D senerate CSE
(chip selectlogic forevenbank) and Xi can perform arithmetic
operations such as add,
with A, to such a s AND, OR, XOR, increnment, decrement ete.
seleet logie for odd bank) 4)
Fisdennded
CSO (chip (b)
Q.3. Compare Procedures and macros using a suitable example
togenerate
decoded with BH5 OR Ans.
diagram explain
the two modesodes of operation Procedure Vs Macros
) W i t h the help of block Procedures
3 Macros
Architecture: The Intel
Microprocessor
ofIntel 8ISS 8086 is a Accessed by CALL and RET mechanism Accessed by name given to macro when
Microprocessor Internal microcomputer
Ans The S086intended to be used as the CPU n a The term 16 during program execution. defined during assembly.
bit microprocessor unit, internal regist Machine code for instructions only put in
b e m e a n s that
its arithmetic logicwords. It has 16-bit databus and 20-hit
uctin memory once
Machine code generated for instructions
binary
16-bit each time called.
are desigmed
to work
locations. If the first hu-yte of a Parameters are passed in registers,
stored in two consecutivememory word ord in one operation. wor Parameters passed as part of statement
Words will be read the entire memory locations or stack
which calls macro.
the 8086 c a n onthefi
i sat a n even address,
address,the 8086 will read
the first byte in Procedures uses stack
Macro does not utilize stack
odd
byteofthe word is atinananother operation
On A procedure can be defined anywhere in
and the second byte program using the directives PROC and
Amacro can be defined anywhere in
program using the directives MACROD
ENDP and ENDM.
Procedures take huge memory for
CALL3 bytes each time CALL is used) Length of code is very huge if macro's are
BU called for more number of tinmes.
Instruction instruction.
Stream
Byte
Queue
B-BUS

Control
system

EU

Anthmatic
logic unit

8086 Internal Block Diagram