Logic Design and Computing Systems

Chapter 4
Combinational Logic

ECEG-3121 1
Outline
 Combinational Circuits
 Design and analysis procedures
 Adders, Subtractors and Multipliers
 Comparators
 Encoders and decoders
 Multiplexers

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Introduction
 Logic circuits can be sequential or combinational.
• Combinational circuit consists of logic gates whose outputs at any
time are determined from only the present combination of inputs.
• Sequential circuits consists of logic gates (and storage elements)
whose outputs are a function of the inputs and the state of the
storage elements.

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 Combinational Circuits
• Combinational logic gates react to Note: There are no feedback
the values of the signals at their circuit in Combinational circuits.
inputs & produce the value of
output signal.
• n input variables = 2n combinations
of possible binary inputs.
• Therefore, combinational circuit
can be specified with a truth table
that lists the output values for each The combinational logic circuit can be
combination of input variables. described by m Boolean functions and each
output can be expressed in terms of n input
variables.
ECEG-3121 4
Analysis & Design
Analysis
• The analysis of a combinational circuit requires that we determine
the function that the circuit implements.
• This task starts with a given logic diagram and ends with a set of
Boolean functions, a truth table, or, an explanation of the circuit
operation.
Note: combinational circuits don’t have feedback circuits
• A feedback path is a connection from the output of one gate to the input of a
second gate whose output forms part of the input to the first gate.

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Analysis & Design
Analysis procedure: (to get Boolean function/truth table)
1. Label all gate outputs that are a function of input variables with
arbitrary symbols—but with meaningful names. Determine the Boolean
functions for each gate output.
2. Label the gates that are a function of input variables and previously
labeled gates with other arbitrary symbols. Find the Boolean functions
for these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are
obtained.
4. By repeated substitution of previously defined functions, obtain the
output Boolean functions in terms of input variables.

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Analysis Procedure
Boolean Expression Approach
A
B
F1
C T2=ABC
A T1=A+B+C
B T3=AB'C'+A'BC'+A'B'C
C
A
B F’2=(A’+B’)(A’+C’)(B’+C’)

A
F2
C
F2=AB+AC+BC
B
C
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
ECEG-3121 7
Analysis Procedure
A B C F1 F2
A=0 0 0 0 0 0 0
B=0 0
F1
C= 0
=0
A 0
=0 0
B
=0
C
1
A=0 0
B=0

A=0 0 0
F2
C= 0

B=0 0
C= 0

Truth Table Approach

ECEG-3121 8
Analysis Procedure
A B C F1 F2
A =0 0 0 0 0 0 0
1
B =0 0 0 1 1 0
F1
C =1
=0
A 1
B =0 1
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1

Truth Table Approach

ECEG-3121 9
Analysis Procedure
A B C F1 F2
A =0 0
0 0 0 0 0
B =1 1
F1 0 0 1 1 0
C =0
0 1 0 1 0
A =0 1
B =1 1
C =0
1
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0

Truth Table Approach

ECEG-3121 10
Analysis Procedure
A B C F1 F2
A =0 0 0 0 0 0 0
B =1 0
F1 0 0 1 1 0
C =1
=0 0 1 0 1 0
A 1
B =1 0 0 1 1 0 1
C =1
0
A =0 0
B =1

A =0 0 1
F2
C =1

B =1 1
C =1

Truth Table Approach

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Analysis Procedure
A B C F1 F2
A=1 0 0 0 0 0
0 1
B=0 0 0 1 1 0
F1
C=0
=1 0 1 0 1 0
A
=0 1 1 0 1 1 0 1
B
=0
C 1 0 0 1 0
1
A=1 0
B=0

A=1 0 0
F2
C=0

B=0 0
C=0

Truth Table Approach

ECEG-3121 12
Analysis Procedure
A B C F1 F2
A =1 0 0 0 0 0 0
B =0 0
0 0 1 1 0
F1
C =1
=1 0 1 0 1 0
A =0 1
B 0 0 1 1 0 1
=1
C 1 0 0 1 0
0
A =1 0
1 0 1 0 1
B =0

A =1 1 1
F2
C =1

B =0 0
C =1

Truth Table Approach

ECEG-3121 13
Analysis Procedure
A B C F1 F2
A =1 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =0
=1 0 1 0 1 0
A 1
B =1 0 0 1 1 0 1
C =0 0 1 0 0 1 0
A =1 1 1 0 1 0 1
B =1
1 1 0 0 1
A =1 0 1
F2
C =0

B =1 0
C =0

Truth Table Approach

ECEG-3121 14
Analysis Procedure
Truth Table Approach A B C F1 F2
A=1 0 0 0 0 0
B=1 1 1
F1 0 0 1 1 0
C= 1
A=1
0 1 0 1 0
B=1 1 0 0 1 1 0 1
C= 1 1 0 0 1 0
0
A=1 1 1 0 1 0 1
B=1
1 1 0 0 1
A=1 1 1
C
F2 1 1 1 1 1
=1
B
C= 1 1
=1 B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
ECEG-3121 15
Design Procedure
Design
 Given a problem statement:
o Determine the number of inputs and outputs
o Derive the truth table
o Simplify the Boolean expression for each output
o Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3” code

 4-bits  4-bits
 0-9 values ?  Value+3

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Design Procedure Eg: BCD-to-Excess 3 Converter
C C
A B C D w x y z
1 1 1
0 0 0 0 0 0 1 1
1 1 1 1
0 0 0 1 0 1 0 0 x x x x
B x x x x
B
0 0 1 0 0 1 0 1 A 1 1 x x
A 1 x x
0 0 1 1 0 1 1 0 D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
x x x x
B x x x x
B
1 0 1 0 x x x x
A 1 x x
A 1 x x
1 0 1 1 x x x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
y = C’D’+CD z = D’
1 1 1 0 x x x x
1 1 1 1 x x x x ECEG-3121 17
Design Procedure
BCD-to-Excess 3 Converter
A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x ECEG-3121 18
Analysis & Design
• A practical design must consider such constraints:
• number of gates
• number of inputs
• propagation time of the signal through the gates,
• number of interconnections
• ...

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Binary Adders
Arithmetic operation is one of the main operations performed by
digital computers.
The simple addition consists of four possible combination of inputs:
0+0=0; 0+1=1;1+0=1;
1+1=10 ….Carry bit is on higher bit
• A combinational circuit that performs the addition of two bits is
called a half adder.
• A circuit that performs the addition of three bits (two significant bits
and a previous carry) is a full adder

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Binary adders
Half-adder
 Two input variables: the addend & augend
 Two output variables: the sum & carry

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Binary Adder
Full Adder
• Adds 1-bit (addend) plus 1-bit (augend) plus 1-bit (carry)
• Produces Sum and Carry x
x S
+ y y
z
FA
y + z C
x y z C S
0 1 0 1 ───
0 0 0 0 0
x 1 0 1 0 C S
0 0 1 0 1
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1 0 0 1 0
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1 C = xy + xz + yz
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Binary Adder
Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z

ECEG-3121 23
Binary Adder
Full Adder
x HA S
y HA

z C

x
S

y
C

ECEG-3121 24
 Connecting n full adders in cascade produces a binary
Binary Adder adder for two n-bit numbers. 1 half adder and n-1 full adders)
x3 x2 x1 x0 y3 y2 y1 y0 c3 c2 c1 .
+ x3 x2 x1 x0
+ y3 y2 y1 y0
Cy Binary Adder C0 ────────
Cy S3 S2 S1 S0

S3 S2 S1 S0
x3 x2 x1 x0
y3 y2 y1 y0
0
Carry propagation
time limits the speed
of the addition.
FA FA FA FA

C4 C3 C2 C1
S3 S2 ECEG-3121
S1 S0 25
 Binary Subtractor
• Can be done by means of
complements.
A - B = A + (-B), where 2’s
complement can be used.
• 2’s = 1’s complement + 1 to
the LSB.
• 1’s complement can be
implemented with inverters

If V = 1, overflow: the result contains n+1 bits.

(the n+1 bit is actual sign bit but out of position) M = 0 Full adder
if V = 0, no overflow: the n bit result is correct M = 1 Subtractor

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Binary Subtractor
A-B : For unsigned numbers, the subtractor gives:
A-B if A ≥ B or
2’s complement of B-A if A<B
For signed numbers, the subtractor gives:
A-B if there is no overflow.
When two numbers with n digits are added and the sum is a number occupying
n+1 digits, it is called overflow.
Note: 1. Binary numbers in the signed-complement system are added and
subtracted by the same basic addition and subtraction rules as unsigned numbers.
2. The programmer must interpret the results depending on the numbers
(signed or unsigned).

ECEG-3121 27
 Overflow
Overflow on Signed & Unsigned
 When two unsigned numbers are added, An overflow can’t occur after an addition if one
an overflow is detected from the end carry number is positive and the other is negative.
out of the MSB position. An overflow may occur if the two numbers
 When two signed numbers are added, the added are both positive or both negative.
sign bit is treated as part of the number
and the end carry does not indicate an
overflow.

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 Binary Multiplier
 Done the same way as the decimal multiplication
 The multiplicand is multiplied by each bit of the
multiplier, starting from the least significant bit.
 Each such multiplication forms a partial product.
 Successive partial products are shifted one position
to the left.
 The final product is obtained from the sum
of the partial products.

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Binary multiplier

AND

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 Binary Multiplier
• For J multiplier bits and K multiplicand
bits we need (J x K) AND gates and (J − 1)
K-bit adders to produce a product of J+K
bits.

• K=4 and J=3, we need 12 AND gates and

two 4-bit adders.

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Comparator
• Compare 4-bit number to 4-bit number
• 3 Outputs: < , = , >
• Expandable to more number of bits

x3  A3 B3  A3 B3 A 3 A 2 A1 A0 B 3 B 2 B 1 B 0

x2  A2 B2  A2 B2
x1  A1 B1  A1 B1 Magnitude Comparator

x0  A0 B0  A0 B0
A<B A=B A>B
( A  B)  x3 x2 x1 x0
( A  B)  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
( A  B)  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
ECEG-3121 32
Comparator
A3
x3

B3

A2
x2

B2

A1 (A<B)
x1

B1

A0
x0 (A>B)

B0
(A=B)
ECEG-3121 33
Decoders
• A binary code of n bits can represent up to 2n binary codes.
• A decoder is a combinational circuit that converts a binary
information from n input lines to a maximum of 2n unique output
lines.
• But a decoder may have fewer than 2n outputs lines.
• 2n minterms.
• The output with value is equal to 1 represents the minterm
equivalent of the binary number currently available in the input
lines.

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Decoders
• Extract “Information ” from the code
• Binary Decoder
Example: 2-bit Binary Number

1
x1 0
Binary 0
x0 0 Decoder 0
0

35
Decoders
2-to-4 Line Decoder
Y3

Y2

I1 I0 Y3 Y2 Y1 Y0 Y1

0 0 0 0 0 1 Y0
0 1 0 0 1 0
1 0 0 1 0 0
I1
1 1 1 0 0 0 I0

Y3  I1 I 0 Y2  I1 I 0
Y1  I1 I 0 Y0  I1 I 0
36
Decoders Y7  I 2 I1 I 0

Y6  I 2 I1 I 0
3-to-8 Line Decoder
Y5  I 2 I1 I 0

Y4  I 2 I1 I 0

Y7
Y3  I 2 I1 I 0
Y6
Y5 Y2  I 2 I1 I 0
Decoder

I2 Y4
Binary

Y1  I 2 I1 I 0
I1 Y3
I0 Y2 Y0  I 2 I1 I 0
Y1
Y0 I2
I1
I0
37
 Decoders
“Enable” Control Y3

Y3 Y2
Decoder
I1 Y2
Binary

I0 Y1 Y1
E Y0
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0 38
Decoders I2 I1 I0
Expansion

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y3 Y7
I0 Y2 Y6

Decoder
0 0 0 0 0 0 0 0 0 0 1

Binary
I1 Y1 Y5
0 0 1 0 0 0 0 0 0 1 0
E Y0 Y4
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0 Y3 Y3
I0 Y2 Y2

Decoder
1 0 1 0 0 1 0 0 0 0 0

Binary
1 1 0 0 1 0 0 0 0 0 0 I1 Y1 Y1
1 1 1 1 0 0 0 0 0 0 0 E Y0 Y0

39
Decoders
Active-High / Active-Low
I1 I0 Y 3 Y 2 Y 1 Y 0 I1 I0 Y 3 Y 2 Y 1 Y 0 Y3

0 0 0 0 0 1 0 0 1 1 1 0 Y2
0 1 0 0 1 0 0 1 1 1 0 1
Y1
1 0 0 1 0 0 1 0 1 0 1 1
1 1 1 0 0 0 1 1 0 1 1 1 Y0

Y3 Y3
Decoder

Decoder
I1 I1 I1
Binary

Binary
Y2 Y2 I0
Y1 Y1
I0 Y0 I0 Y0

40
Decoders
• A decoder with enable input can be used as a demultiplexer, directing
an input to 2n possible output lines.
Y3
• There will be selection lines/bits
Y2
Decoder-demultiplexer
E I1 I0 Y3 Y2 Y1 Y0
Y1
0 x x 0 0 0 0
1 0 0 0 0 0 1 Y0

1 0 1 0 0 1 0
1 1 0 0 1 0 0 I1
I0
1 1 1 1 0 0 0 E

ECEG-3121 41
 Decoders
Full adder implementation
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 ECEG-3121 42
Decoders
Binary Binary
Decoder Decoder
Y7 Y7
Y6 Y6
Y5 Y5
x I2 Y4 x I2 Y4
y I1 Y3 y I1 Y3
z I0 Y2 z I0 Y2
Y1 Y1
Y0 Y0

S C S C 43
 Encoders
• It performs the inverse of decoders
• 2n or fewer input lines and n output lines.
• The output lines generate the binary code corresponding to the input
value.
x1
x3 x2 x1 y1 y0
Eg: 3-to-2 Binary
Encoder y1 0 0 0 0 0
x2 Binary
0 0 1 0 1
Encoder
y0 0 1 0 1 0
x3
1 0 0 1 1

ECEG-3121 44
Encoders
• Octal-to-Binary Encoder (8-to-3)
I7 I6 I5 I4 I3 I2 I 1 I0 Y2 Y1 Y0 I7
0 0 0 0 0 0 0 1 0 0 0 I6 Y2
0 0 0 0 0 0 1 0 0 0 1 I5
0 0 0 0 0 1 0 0 0 1 0 I4
0 0 0 0 1 0 0 0 0 1 1 I3 Y1
0 0 0 1 0 0 0 0 1 0 0 I2
0 0 1 0 0 0 0 0 1 0 1 I1
0 1 0 0 0 0 0 0 1 1 0 I0 Y0
1 0 0 0 0 0 0 0 1 1 1
Y2  I 7  I 6  I 5  I 4
Y1  I 7  I 6  I 3  I 2
Y0  I 7  I 5  I 3  I1 45
Priority Encoders
• 4-Input Priority Encoder

46
Encoders
4-Input Priority Encoder

ECEG-3121 47
Multiplexers
• A multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single
output line.
• The selection of a particular input line is controlled by a set of
selection lines.
• Normally, there are 2n input lines and n selection lines whose bit
combinations determine which input is selected.

ECEG-3121 48
Multiplexers

2-to-1-line
Multiplexer
Logic diagram Block diagram

ECEG-3121 49
Multiplexers
Multiplexer is also called data selector

Function table

4-to-1-line
Multiplexer ECEG-3121 50
Multiplexers
Quad 2-to-1 MUX A3
Y3
x3 I0 A2
y3 MUX Y Y2
I1
S A1
Y1
A0
x2 I0 Y0
MUX Y
y2 I1 B3
S A3
A2
B2 A1
x1 I0
MUX Y A0
Y3
y1 I1 B1 Y2
S MUX Y
1
B3 Y0
B0
B2
x0 I0
MUX Y B1
y0 I1
S
B0
S E
S E
S
51
Implementation Using Multiplexers
Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0
z I0
F
F=z z I1
MUX Y
0 0 1 1 0 I2
0 1 0 1 1 I3
F=z S1 S0
0 1 1 0
1 0 0 0 x y
F=0
1 0 1 0
1 1 0 1
1 1 1 1 F=1
52
Implementation Using Multiplexers
• Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0 D I0
0 0 0 1 1 F=D D I1
0 0 1 0 0
F=D D I2
0 0 1 1 1
0 1 0 0 1 0 I3
F=D MUX Y F
0 1 0 1 0 0 I4
0 1 1 0 0
0 1 1 1 0 F=0 D I5
1 0 0 0 0 1 I6
1 0 0 1 0 F=0
1 I7
1 0 1 0 0
1 0 1 1 1
F=D S2 S1 S0
1 1 0 0 1
F=1
1 1 0 1 1
A B C
1 1 1 0 1 F=1
1 1 1 1 1 53