Faculty of

Engineering

Digital Logic Design

Combinational Logic

Dr. Ahmed M. Abdeltawab

 Faculty of
Combinational Circuits Engineering

 Output is function of input only

i.e. no feedback

Combinational
n inputs • • m outputs
• Circuits •
• •


When input changes, output may change (after a delay)

ECE 203 Combinational Logic Ch4-1

 Faculty of
Combinational Circuits Engineering

 Analysis
● Given a circuit, find out its function
A
B
C
A
F1
?
B
C
A
B

?
● Function may be expressed as:
A
F2
C

B
C

♦ Boolean function
♦ Truth table

 Design
● Given a desired function, determine its circuit
● Function may be expressed as:
♦ Boolean function
?
♦ Truth table

ECE 203 Combinational Logic Ch4-2

 Faculty of
Analysis Procedure Engineering

Boolean Expression Approach

A
B
F1
C T2=ABC
A T1=A+B+C
B T3=AB'C'+A'BC'+A'B'C
C
A
B F’2=(A’+B’)(A’+C’)(B’+C’)

A
F2
C
F2=AB+AC+BC
B
C
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
ECE 203 Combinational Logic Ch4-3
 Faculty of
Analysis Procedure Engineering

Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 0
B =0
F1
C =0
A =0 0
B =0 0
C =0
1
A =0 0
B =0

A =0 0 0
F2
C =0

B =0 0
C =0

ECE 203 Combinational Logic Ch4-4

 Faculty of
Analysis Procedure Engineering

Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =1
A =0 1
B =0 1
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1

ECE 203 Combinational Logic Ch4-5

 Faculty of
Analysis Procedure Engineering

Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 1
B =1 0 0 1 1 0
F1
C =0
0 1 0 1 0
A =0 1
B =1 1
C =0
1
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0

ECE 203 Combinational Logic Ch4-6

 Faculty of
Analysis Procedure Engineering

Truth Table Approach A B C F1 F2

A =0 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =1
A =0
0 1 0 1 0
1 0 0 1
B =1 0 1 1
C =1
0
A =0 0
B =1

A =0 0 1
F2
C =1

B =1 1
C =1

ECE 203 Combinational Logic Ch4-7

 Faculty of
Analysis Procedure Engineering

Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 1
B =0 0 1 1 0 1
C =0 1 0 0 1 0
1
A =1 0
B =0

A =1 0 0
F2
C =0

B =0 0
C =0

ECE 203 Combinational Logic Ch4-8

 Faculty of
Analysis Procedure Engineering

Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 0
B =0 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =0 0 1 1 0 1
C =1 1 0 0 1 0
0
A =1 0 0 1
B =0
1 0 1

A =1 1 1
F2
C =1

B =0 0
C =1

ECE 203 Combinational Logic Ch4-9

 Faculty of
Analysis Procedure Engineering

Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =0 1 0 0 1 0
0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 0 1
F2
C =0

B =1 0
C =0

ECE 203 Combinational Logic Ch4-10

 Faculty of
Analysis Procedure Engineering

Truth Table Approach A B C F1 F2

A =1 0 0 0 0 0
1 1
B =1 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1 1 0 0 1 0
0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 1 1
C =1
F2 1 1 1 1 1
B =1 1
C =1 B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
ECE 203 Combinational Logic Ch4-11
 Faculty of
Design Procedure Engineering

 Given a problem statement:

● Determine the number of inputs and outputs
● Derive the truth table
● Simplify the Boolean expression for each output
● Produce the required circuit

Example:
Design a circuit to convert a “BCD” code to “Excess 3” code

➢ 4-bits ➢ 4-bits
➢ 0-9 values
? ➢ Value+3

ECE 203 Combinational Logic Ch4-12

 Faculty of
Design Procedure Engineering

BCD-to-Excess 3 Converter
C C
A B C D w x y z
1 1 1
0 0 0 0 0 0 1 1
1 1 1 1
0 0 0 1 0 1 0 0 B B
x x x x x x x x
0 0 1 0 0 1 0 1 A A
1 1 x x 1 x x
0 0 1 1 0 1 1 0
D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x
B x x x x
B
A 1 x x
A 1 x x
1 0 1 1 x x x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x
ECE 203 Combinational Logic Ch4-13
 Faculty of
Design Procedure Engineering

BCD-to-Excess 3 Converter
A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x
ECE 203 Combinational Logic Ch4-14
 Faculty of
Seven-Segment Decoder Engineering

a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
ECE 203 Combinational Logic Ch4-15
 Faculty of
Binary Adder Engineering

Half Adder x S
y HA
C
● Adds 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
───
x y C S C S
0 0 0 0
0 1 0 1 x S
1 0 0 1
1 1 1 0
y C

ECE 203 Combinational Logic Ch4-16

 Faculty of
Binary Adder Engineering

Full Adder x S
y FA
z C
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
y + z
x y z C S ───
0 1 0 1
0 0 0 0 0 C S
0 0 1 0 1 x 1 0 1 0
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
0 0 1 0
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1 C = xy + xz + yz
ECE 203 Combinational Logic Ch4-17
 Faculty of
Binary Adder Engineering

Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z

x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z

ECE 203 Combinational Logic Ch4-18

 Faculty of
Binary Adder Engineering

Full Adder
x S
y HA HA

z C

x
S

y
C

ECE 203 Combinational Logic Ch4-19

 Faculty of
Binary Adder Engineering

x3x2x1x0 y3y2y1y0
c3 c2 c1 .
+ x3 x2 x1 x0
Carry + y3 y2 y1 y0
Cy Binary Adder C0 Propagate ────────
Addition Cy S3 S2 S1 S0
S3S2S1S0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0
ECE 203 Combinational Logic Ch4-20
 Faculty of
Binary Adder Engineering

Carry Propagate Adder

x7 x6 x5 x4 x3 x2 x 1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0

Cy CPA C0 Cy CPA C0 0

S3 S2 S1 S0 S3 S2 S1 S0

S7 S6 S5 S4 S3 S2 S 1 S0

ECE 203 Combinational Logic Ch4-21

 Faculty of
Engineering

 Carry propagation
● When the correct outputs are available
● The critical path counts (the worst case)
● (A1, B1, C1) → C2 → C3 → C4 → (C5, S4)
● When 4-bits full-adder → 8 gate levels (n-bits: 2n gate
levels)

Figure 4.10 Full Adder with P and G Shown

ECE 203 Combinational Logic Ch4-22
 Faculty of
Parallel Adders Engineering

 Reduce the carry propagation delay

● Employ faster gates
● Look-ahead carry (more complex mechanism, yet faster)
● Carry propagate: Pi = AiBi
● Carry generate: Gi = AiBi
● Sum: Si = PiCi
● Carry: Ci+1 = Gi+PiCi
● C0 = Input carry
● C1 = G0+P0C0
● C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0
● C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

ECE 203 Combinational Logic Ch4-23

 Faculty of
Carry Look-ahead Adder (1/2) Engineering

 Logic diagram

Fig. 4.11 Logic Diagram of Carry Look-ahead Generator

ECE 203 Combinational Logic Ch4-24
 Faculty of
Carry Look-ahead Adder (2/2) Engineering

 4-bit carry-look
ahead adder
● Propagation delay
of C3, C2 and C1 are
equal.

Fig. 4.12 4-Bit Adder with Carry Look-ahead

ECE 203 Combinational Logic Ch4-25

 Faculty of
BCD Adder Engineering

4-bits plus 4-bits + x3 x2 x1 x0

+ y3 y2 y1 y0
 Operands and Result: 0 to 9 ────────
Cy S3 S2 S1 S0
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0
0+0 0 0 0 0 0 0 0 0 =0 0 0 0 0 0
0+1 0 0 0 0 0 0 0 1 =1 0 0 0 0 1
0+2 0 0 0 0 0 0 1 0 =2 0 0 0 1 0

0+9 0 0 0 0 1 0 0 1 =9 0 1 0 0 1
1+0 0 0 0 1 0 0 0 0 =1 0 0 0 0 1
1+1 0 0 0 1 0 0 0 1 =2 0 0 0 1 0

1+8 0 0 0 1 1 0 0 0 =9 0 1 0 0 1
1+9 0 0 0 1 1 0 0 1 =A 0 1 0 1 0 Invalid Code
2+0 0 0 1 0 0 0 0 0 =2 0 0 0 1 0

9+9 1 0 0 1 1 0 0 1 = 12 1 0 0 1 0 Wrong BCD Value

ECE 203
0001 1000 Combinational Logic Ch4-26
 Faculty of
BCD Adder Engineering

X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value

9+0 1 0 0 1 0 0 0 0 =9 0 1 0 0 1 0 0 0 0 1 0 0 1 =9
9+1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16 
9+2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17 
9+3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18 
9+4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19 
9+5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20 
9+6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21 
9+7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22 
9+8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23 
9+9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24 

+6

ECE 203 Combinational Logic Ch4-27

 Faculty of
BCD Adder Engineering

Correct Binary Adder’s Output (+6)

● If the result is between ‘A’ and ‘F’
● If Cy = 1

S3 S2 S1 S0 Err
S1
0 0 0 0 0

1 0 0 0 0 1 1 1 1
S2
1 0 0 1 0 S3 1 1
1 0 1 0 1 S0
1 0 1 1 1
1 1 0 0 1
Err = S3 S2 + S3 S1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

ECE 203 Combinational Logic Ch4-28

 Faculty of
BCD Adder Engineering

x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

Err

0 0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

Cy S3 S2 S1 S0
ECE 203 Combinational Logic Ch4-29
 Faculty of
Binary Subtractor Engineering

Use 2’s complement with binary adder

● x – y = x + (-y) = x + y’ + 1

x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0

ECE 203 Combinational Logic Ch4-30

 Faculty of
Binary Adder/Subtractor Engineering

M: Control Signal (Mode)

● M=0 ➔ F = x + y x3 x2 x1 x0 y3 y2 y1 y0 M
● M=1 ➔ F = x – y

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0

F3 F2 F1 F0

ECE 203 Combinational Logic Ch4-31

 Faculty of
Overflow Engineering

Unsigned Binary Numbers

x x2 x1 x0
3
y3 y2 y1 y0
0

FA FA FA FA

Carry C4 C3 C2 C1
S3 S2 S1 S0
2’s Complement Numbers
x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

Overflow C4 C3 C2 C1
S3 S2 S1 S0

ECE 203 Combinational Logic Ch4-32

 Faculty of
Magnitude Comparator Engineering

Compare 4-bit number to 4-bit number

● 3 Outputs: < , = , >
● Expandable to more number of bits

x3 = A3 B3 + A3 B3 A3A2A1A0 B3B2B1B0

x2 = A2 B2 + A2 B2
Magnitude
x1 = A1 B1 + A1 B1 Comparator
x0 = A0 B0 + A0 B0
A<B A=B A>B
( A = B) = x3 x2 x1 x0
( A  B) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
( A  B) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
ECE 203 Combinational Logic Ch4-33
 Faculty of
Magnitude Comparator Engineering

A3
x3

B3

A2
x2

B2

A1 (A<B)
x1

B1

A0
x0 (A>B)

B0
(A=B)

ECE 203 Combinational Logic Ch4-34

 Faculty of
Magnitude Comparator Engineering

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
0 I(A>B) I(A>B)
1
Magnitude Magnitude
I(A=B) I(A=B)
I(A<B)
Comparator I(A<B)
Comparator
0
A<B A=B A>B A<B A=B A>B

A<B A=B A>B

ECE 203 Combinational Logic Ch4-35

 Faculty of
ADDERS IN VERILOG Engineering

 half adder in 3 modeling styles

(dataflow/structural/behavioral).

ECE 203 Combinational Logic Ch4-36

 Faculty of
ADDERS IN VERILOG Engineering

ECE 203 Combinational Logic Ch4-37

 Faculty of
ADDERS IN VERILOG Engineering

ECE 203 Combinational Logic Ch4-38

 Faculty of
Decoders Engineering

Extract “Information” from the code Only one

lamp will
 Binary Decoder turn on
● Example: 2-bit Binary Number

0 1 2 3

0 1
x1 0
Binary
x0 0 Decoder 0
0

ECE 203 Combinational Logic Ch4-39

 Faculty of
Decoders Engineering

2-to-4 Line Decoder

Y3

y3 Y2

Decoder
I1 Binary
y2
y1 Y1
I0 y0
Y0

I1 I0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 = I1 I 0 Y2 = I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 = I1 I 0 Y0 = I1 I 0
ECE 203 Combinational Logic Ch4-40
 Faculty of
Decoders Engineering

3-to-8 Line Decoder Y7 = I 2 I1 I 0

Y6 = I 2 I1 I 0
Y7 Y5 = I 2 I1 I 0
Y6
Y5 Y4 = I 2 I1 I 0
Decoder
Binary

I2 Y4 Y3 = I 2 I1 I 0
I1 Y3
I0 Y2 Y2 = I 2 I1 I 0
Y1 Y1 = I 2 I1 I 0
Y0
Y0 = I 2 I1 I 0

I2
I1
I0
ECE 203 Combinational Logic Ch4-41
 Faculty of
Decoders Engineering

“Enable” Control Y3

Y3

Decoder
I1 Y2
Binary Y2
I0 Y1
E Y1
Y0
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
ECE 203 Combinational Logic Ch4-42
 Faculty of
Decoders Engineering

Expansion I2 I1 I0

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 Y3 Y7

Decoder
I0

Binary
0 1 0 0 0 0 0 0 1 0 0 Y2 Y6
I1 Y1 Y5
0 1 1 0 0 0 0 1 0 0 0 E
1 0 0 0 0 0 1 0 0 0 0 Y0 Y4
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 Y3 Y3

Decoder
I0

Binary
1 1 1 1 0 0 0 0 0 0 0 Y2 Y2
I1 Y1 Y1
E Y0 Y0

ECE 203 Combinational Logic Ch4-43

 Faculty of
Decoders Engineering

Active-High / Active-Low
I1 I0 Y 3 Y 2 Y 1 Y 0 I1 I0 Y 3 Y 2 Y 1 Y 0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2

Y1
Y3 Y3
Decoder

I1 I1 Decoder
Binary

Binary
Y2 Y2 Y0

Y1 Y1
I0 Y0 I0 Y0 I1
I0

ECE 203 Combinational Logic Ch4-44

 Faculty of
Implementation Using Decoders Engineering

 Each output is a minterm Binary

Decoder
 All minterms are produced
Y7
 Sum the required minterms Y6
Y5
x I2 Y4
y I1 Y3
Example: Full Adder
z I0 Y2
S(x, y, z) = ∑(1, 2, 4, 7) Y1
Y0
C(x, y, z) = ∑(3, 5, 6, 7)

ECE 203
S C
Combinational Logic Ch4-45
 Faculty of
Implementation Using Decoders Engineering

Binary Binary
Decoder Decoder

Y7 Y7
Y6 Y6
Y5 Y5
x I2 Y4 x I2 Y4
y I1 Y3 y I1 Y3
z I0 Y2 z I0 Y2
Y1 Y1
Y0 Y0

S C
S C
ECE 203 Combinational Logic Ch4-46
 Faculty of
Encoders Engineering

Put “Information” into code Only one

switch
 Binary Encoder should be
● Example: 4-to-2 Binary Encoder activated
at a time

1 x1
x3 x2 x1 y1 y0
y1 0 0 0 0 0
2
x2 Binary
Encoder 0 0 1 0 1
y0 0 1 0 1 0
3
x3
1 0 0 1 1

ECE 203 Combinational Logic Ch4-47

 Faculty of
Encoders Engineering

Octal-to-Binary Encoder (8-to-3)

I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
I5

Encoder
0 0 0 0 0 0 0 1 0 0 0 Y2

Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0 I7
1 0 0 0 0 0 0 0 1 1 1 I6 Y2
I5
Y2 = I 7 + I 6 + I 5 + I 4 I4
I3 Y1
Y1 = I 7 + I 6 + I 3 + I 2 I2
I1
Y0 = I 7 + I 5 + I 3 + I1 I0 Y0
ECE 203 Combinational Logic Ch4-48
 Faculty of
Priority Encoders Engineering

4-Input Priority Encoder

I3

Encoder
V

Priority
I3 I2 I1 I0 Y1 Y0 V I2 Y1
0 0 0 0 0 0 0 I1 Y0
0 0 0 1 0 0 1 I0
0 0 1 x 0 1 1
0 1 x x 1 0 1
I3 Y0
1 x x x 1 1 1
I2
Y1 I1 I1
Y1 = I 3 + I 2 Y1
1 1 1 1
1 1 1 1
I2 Y0 = I 3 + I 2 I1
I3 I0 V
1 1 1 1
I0
V = I 3 + I 2 + I1 + I 0

ECE 203 Combinational Logic Ch4-49

 Faculty of
Encoder / Decoder Pairs Engineering

Binary Binary
Encoder Decoder

7 I7 Y7
7
6 I6 Y6
6
5 I5 Y5
5
4
Y2 I2
4 I4 Y4
3
Y1 I1
3 I3 Y3
2
Y0 I0
2 I2 Y2

1 I1 Y1
1
0 I0 Y0
0

ECE 203 Combinational Logic Ch4-50

 Faculty of
Multiplexers Engineering

S1 S0 Y I0
0 0 I0 I1
MUX Y
0 1 I1 I2
1 0 I2 I3
S1 S0
1 1 I3
ECE 203 Combinational Logic Ch4-51
 Faculty of
Multiplexers Engineering

2-to-1 MUX
I0
I0 Y
MUX Y
I1 I1
S
S
I0
4-to-1 MUX I1
Y
I0 I2

I1 I3
MUX Y
I2
I3
S1 S0
S1 S0
ECE 203 Combinational Logic Ch4-52
 Faculty of
Multiplexers Engineering

Quad 2-to-1 MUX A 3

Y3
A2
x3 I0 Y2
y3 MUX Y A1
I1 Y1
S
A0
Y0
x2 I0 B3
y2 MUX Y
I1
S B2
A3
B1 A2
x1 I0 A1
Y3
y1 MUX Y B0 A0
I1 Y
MUX 2
S Y1
B3 Y0
B2
x0 I0
MUX Y
S E
B1
y0 I1 B0
S S E

S
ECE 203 Combinational Logic Ch4-53
 Faculty of
Multiplexers Engineering

Quad 2-to-1 MUX

A3
Y3 A3
A2
Y2 A2
A1 A1
Y1 Y3
A0
Y0
A0 Y2
MUX
B3 Y1
B3
B2 Y0
B2
B1 B1
B0 B0
S E
Extra
Buffers
S E
ECE 203 Combinational Logic Ch4-54
 Faculty of
Implementation Using Multiplexers Engineering

Example
F(x, y) = ∑(0, 1, 3)

x y F I0
1
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3
S1 S0
1 1 1
x y

ECE 203 Combinational Logic Ch4-55

 Faculty of
Implementation Using Multiplexers Engineering

Example
F(x, y, z) = ∑(1, 2, 6, 7)
0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
Y F
0 1 0 1 0 I4 MUX
0 1 1 0 0 I5
1 I6
1 0 0 0
1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z

ECE 203 Combinational Logic Ch4-56

 Faculty of
Implementation Using Multiplexers Engineering

Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
F=z z I1 F
0 0 1 1
MUX Y
0 1 0 1 0 I2
F=z 1 I3
0 1 1 0 S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
ECE 203 Combinational Logic Ch4-57
 Faculty of
Implementation Using Multiplexers Engineering

Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0
D I1
F=D
0 0 1 1 1 D I2
0 1 0 0 1
0 1 0 1 0
F=D 0 I3
0 MUX Y F
0 1 1 0 0
F=0 I4
0 1 1 1 0 D
1 0 0 0 0
I5
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
1 0 1 1 1
F=D 1 I7
1 1 0 0 1 S2 S1 S0
F=1
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1 A B C
ECE 203 Combinational Logic Ch4-58
 Faculty of
Multiplexer Expansion Engineering

8-to-1 MUX using Dual 4-to-1 MUX

I0 I0
I1 I1
MUX Y
I2 I2
I3 I3
S1 S0 I0
MUX Y Y
I1
I0 S
I4
I5 I1
MUX Y
I6 I2
I7 I3
S1 S0

1 0 0
ECE 203
S2 S1 S0 Combinational Logic Ch4-59
 Faculty of
DeMultiplexers Engineering

Y3
Y2
I DeMUX Y
1

S S Y0
1 0

Y3

Y2 S1 S0 Y3 Y 2 Y1 Y0
I
Y1 0 0 0 0 0 I
Y0
0 1 0 0 I 0
1 0 0 I 0 0
S1 1 1 I 0 0 0
S0
ECE 203 Combinational Logic Ch4-60
 Faculty of
Multiplexer / DeMultiplexer Pairs Engineering

MUX DeMUX

7 I7 Y7
7
6 I6 Y6
6
5 I5 Y5
5
4 I4 Y4
4
3 I3
Y I Y3
3
2 I2 Y2
2
1 I1 Y1
1
0 I0 Y0
0
S2 S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y1 y0
ECE 203 Combinational Logic Ch4-61
 Faculty of
DeMultiplexers / Decoders Engineering

Y3 Y3

Decoder
I1

Binary
Y2 Y2
I DeMUX Y I0 Y1
1
E Y0
S S Y0
1 0

E I1 I0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0

ECE 203 Combinational Logic Ch4-62

 Faculty of
Three-State Gates Engineering

 Tri-State Buffer
C A Y

A Y 0 x Hi-Z
1 0 0
1 1 1
C
A Y
 Tri-State Inverter
C

ECE 203 Combinational Logic Ch4-63

 Faculty of
Three-State Gates Engineering

A C D Y
0 0 Hi-Z
Y 0 1 B
C
1 0 A
B 1 1 ?

Not Allowed
D
A
C A if C = 1
Y=
B if C = 0
B
ECE 203 Combinational Logic Ch4-64
 Faculty of
Three-State Gates Engineering

I3

I2
Y
I1

I0
Y3
Decoder

S1 I1
Binary

Y2
I0 Y1
E Y0
ECE 203 Combinational Logic Ch4-65