ELEC 3300

Introduction to Embedded Systems

Topic 10
Memory, Interfacing to Memory, Memory Timing,
and Applications
Prof. Tim Woo

ELEC 3300 : Spring 17/18 Tim Woo 1

 Course Overview
Assembler

Instruction Set Architecture

Memory I/O System

Datapath & Control

Introduction to Basic Computer
Embedded Systems Structure
MCU Main Board

Digital and Analog

Interfacing USART, IEEE1394,
USB, I2C and SPI

Microcontroller Structure
A/D Port
Buffering and
Serial Port Direct Memory Access
CPU (DMA)
External Memory Port
Memory,
Interfacing to Memory,
External Interrupt Port
Memory Timing
Interrupt and applications
External Timer Port Interfacing LCD
Organization Timer and
Counter Simple I/O Port
Motor Interfacing

In this course, STM32 is used as a driving vehicle for delivering the concepts.
To be covered In progress Done

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 Expected Outcomes
• On successful completion of this topic, you will be able to
– Summarize the types of memory technologies
– Interpret both hardware and software interfacing including
• CPU memory interface
• Timing diagrams of memory accesses ( Read / Write / Refresh Operations)
– Explain key considerations of memory architectures including
• Memory Expansion
• Paging
– Analyze memory architecture for mobile embedded systems

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 Memory Technologies
FLASH
UVEPROM
•High density (UV Erasable Programmable ROM)
•Low cost
•High speed •Non-volatile
•Lower power •High density
•High reliability UVEPROM •Erasable by UV light (takes an hour)
•programmed many times (~100)
DRAM (Dynamic RAM)
E2PROM / EEPROM
SDRAM (Synchronous DRAM) EEPROM
DDR SDRAM (Double Data Rate SDRAM) (Electrically Erasable Programmable ROM)
Updateable Non-volatile •Non-volatile
•High density
•Low cost •Lower density
•High speed •Lower reliability
•Lower power
FLASH •Higher cost
•Refreshing is required •Erasable by electrical (takes few ms)
•programmed many times (~1000)
DRAM High
PROM (OTP)
SRAM Density PROM (Programmable ROM)
SRAM (Static RAM)
•Non-volatile
SSRAM (Synchronous SRAM)
•High density
•Low density •Reliable
•Low cost •Low cost
•High speed •One-time programmable (OTP)
•Lower power (suitable for mass production with stable code)

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 CPU-Memory Interface
• CPU-Memory interface usually consists of
– Unidirectional address bus
– Bidirectional data bus
– Read/write control lines
– Ready control lone
– Size (byte, word) control line

• Memory access involves memory bus transaction

– Read: set address, read and size, copy data when ready is set by memory
– Write: set address, write and size, done when ready is set

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 Example 1: EEPROM Timing for Read Access

1 Step 1: send the address to EEPROM

2 3 4
Step 2: chip enable (CE = 0)
Step 3: output enable (OE = 0)
Chip Enable Step 4: data is ready
Step 5: output disable (OE = 1)
Step 6: chip disable (CE = 1)

Any alternative sequence?

Output Enable

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 Example 2a: SRAM Timing for Read Access
1

7
2

6
4

Step 1: send the address to SRAM

Step 2: chip enable (CS = 0)
5
Step 3: read enable (WE = 1)
Step 4: output enable (OE = 0)
Step 5: data is ready
Step 6: output disable (OE = 1)
Step 7: chip disable (CE = 1)

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 Example 2b: SRAM Timing for Write Access

4 7

6
5
2

Step 1: send the address to SRAM

Step 2: output disable (OE = 1)
3 Step 3: data ready (D0 – D7)
Step 4: chip select (CS = 0)
Step 5: write enable (WE = 0)
Step 6: write disable (WE = 1)
Step 7: chip disable (CE = 1)

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 DRAM Memory Devices
• DRAM devices differ from SRAMs in these ways
– The data is stored as charge on a capacitor (which leaks away unless refreshed
for every 2ms)
– The organization is usually ‘bit-wide’ instead of ‘byte-wide’
– DRAMs are organized internally as a matrix of storage bits with each bit having a
row address and column address and multiplexing of these addresses is used

(1 bit)

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 Basic DRAM Operation
• Address is time multiplexed into separate row and column address latches
• Row and column addresses are decoded and strobed sequentially by RAS
and CAS signals
• Each sense amplifier both reads and restores the data to the bit cell

(RAS = 0, CAS = 1)

(RAS = 1, CAS = 0)

(1 bit)
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 Basic DRAM Operation

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 DRAM: Read Timing Diagram
Step 1: Send the address
- row address  row decoder (RAS = 0, CAS = 1)
- column address  column decoder
(RAS = 1, CAS = 0)
Step 2: Chip select (if necessary)
Step 3: Read enable (WE = 1)
Step 4: Data ready

Step 1

Step 3 Step 4

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 DRAM: Write Timing Diagram

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 DRAM: Refresh Timing Diagram

• Refresh: read out the voltage of each cell, amplify it, charge the capacitor
back to the original voltage
• All cells in a row are refreshed in parallel
• The entire DRAM is refreshed by providing each possible row address in
sequence by a counter to increment the row address at each refresh cycle
• For a 4Mx1-bit DRAM, 2048 refresh cycles are needed
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 STM32: Interfacing to DRAM

STM32 PA.0-PA.7
PB.0-PB.8

PC.0
PC.1
PC.2
9-bit Row Address Decoder: A0 -A8: Row0 - Row7, Col9

9-bit Col Address Decoder: A0 -A8: Col0 - Col8

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 STM32: Interfacing to DRAM

• Internal architecture of 256K DRAM: 256 rows 1024 cols

9-bit decoder

Row 0 – 7 ,
Col 9

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 STM32: Controlling DRAM by Software (Read Access)
Connect 8 DRAMs in parallel for data information (D0 – D7)

Assume: DRAM Memory Array

Address information:
ColAdd = 0x03AB; (10 bits) Row Address (8 bits) Column Address (10 bits)
Row 7 , Row 6, ……, Row 0 Col 9, Col 8, ……, Col 1, Col 0
RowAdd = 0x00F7; (8 bits)
Hardware Decoder
Control information:
Row Decoder (9 bits) Column Decoder (9 bits)
PC.2 = 1 ; /W
Row 0 – Row 7, Col 9 Col 0 – Col 8
PC.0 = 1 ; /RAS high
PC.1 = 1 ; /CAS high Pin Assignment in STM32
PB.0 – PB.7 (Row 0 – Row 7) PB.0 – PB.0 (Col 0 – Col 8)
Data information PB.8 (Col 9)
PA.0 (D0) – PA.7 (D7)

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STM32: Controlling DRAM by Software (Read Access)
Assume: This code does an actual DRAM read access.
ColAdd = 0x03AB; (10 bits) ……
RowAdd = 0x00F7; (8 bits) ; 9-bit Row Decoder
PC.2 = 1 ; /W GPIOBODR = ((ColAdd & 0x200) >> 1) | RowAdd;
PC.0 = 1 ; /RAS high
PC.1 = 1 ; /CAS high GPIOCODR = 0x06 ; /RAS low
Delay();
GPIOCODR = 0x07 ; /RAS high
Delay();

; 9-bit Column Decoder

GPIOBODR = ColAdd & 0x1FF;

GPIOCODR = 0x05 ; /CAS low

Delay();
GPIOCODR = 0x07 ; /CAS high
Delay();

data = GPIOAIDR ; Get the data (byte)

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 STM32: Refreshing DRAM by Software
Assume:
PC.2 = 1 ; /W This code refresh DRAM access.
PC.0 = 0 ; /RAS ……
PC.1 = 1 ; /CAS i = 0; ; Initialize refresh counter

GPIOCODR=0x07; /RAS high

Refresh
GPIOBODR= i ; Get next row address to refresh
cycle time
Delay() ; pre-charge time
GPIOCODR=0x06; /RAS low
Delay() ;
i++ ; increment the refresh counter
……
……
Repeat this 256 times. This is written in-line
rather than a loop to maximize speed
1
3

Delay2

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 Flash Memory and its applications

Applications Performance Type of Flash Memory

Code Program storage for Important: NOR

Storage - Cellular Phone - High speed random (full address and data
- Switcher for access lines)
telecommunications - Byte programming
-PDA / POS / PCA
-DVD Acceptable:
BIOS for - Slow programming
- PC and peripherals - Slow erase
File Memory Storage for Important: NAND
Storage - Digital camera - High speed (Commands and data
- Video camera programming are multiplexed onto
- Voice recorder - High speed erasing eight I/O lines)
- Audio recorder - High speed serial read
- PDA
Mass storage for Acceptable:
- Solid-State Disk -Slow random access
-- Hybrid HDD -I/O mapped access

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 Flash Organization

• First Generation of NAND flash

– Page size: (512 + 16) bytes Samsung K9F5608X0C (32M x 8 bits)
– Pages per block: 32
– Erase Unit: 16K bytes

Block 0

Block 1

Block 2

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 Flash Organization

• Second Generation of NAND Flash

– Page size: (2048 + 64) bytes
– Pages per block: 64
– Erase Unit: Blockwise Unit (128K bytes)
Samsung K9F1G08X0M (128M x 8 bits)

Block 0

Block 1

Block 2

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 Flash Memory Characteristics

• Operations
– Read
– Write or Program : Change state from 1 to 0
– Erase : Change state from 0 to 1
Erase
Write / Program
• Unit
– Page (sector) : management or program unit
– Block : erase unit

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 Paging in Memory Architecture
• There is an Address Space implied by the Address Lines on the bus
– e.g. 16-bit addresses on a 16-line address bus implies up 216 addressable
locations in the memory subsystem
• It is unusual to have one memory device spanning the whole address
space
• Instead, there is a Memory Map which maps storage locations in particular
memory components to addresses in the address space

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 The Memory Interfacing Task
• The bus connects to Memory Components via Memory-bus interface circuitry
• The tasks that this interface has to perform are
– Address decoding (the principal task)
– Matching bus control sign (RD/WR, PSEN, EA) to the control signals (RD/WR, OE,
CE) of the memory components

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 Address Decoding: An example

The address decoder is a

combinational logic to generate
the Chip-Select signals for each
memory component

1110 0000 0000 0000 – 1111 1111 1111 1111

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Memory architecture for mobile embedded system: Code storage

• NOR • NOR Shadowing

MCU MCU

SDRAM
SDRAM High (Data)
(Data) speed
(Code)

NOR Slow
NOR
(Code) speed (Code)
High
High cost
(Boot Code)
cost
EPROM replacement
Code is copied into high speed SDRAM
Support dynamically code update
Sometime, codes in NOR flash is stored in
Execute-In-Place (XIP): allows the system to a compressed format, and uncompressed
execute code directly from NOR flash into the SDRAM prior to execution

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Memory architecture for mobile embedded system: Code storage

• NAND Shadowing

MCU

SDRAM
(Data) Use a small amount of NOR / ERPOM
for holding the bootstrap code and the
(Code) OS image

NAND Gain control by decoding the power on

(Code) Low cost address execution

NOR / EPROM
(Boot Code)

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Memory architecture for mobile embedded system: Code storage

• NAND XIP
– Interface conversion from NAND to SRAM / NOR
• Boot image loading
• Error detection and correction coding (EDC/ECC)
• Level 2 Cache (SRAM): Code prefetching, Data preloading

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Memory architecture for mobile embedded system: Code storage

• Demand Paging Over NAND

– Motivation MCU

• Applications become larger.

SDRAM
• It is increasingly common to download new applications (Data)
from the network.
• All the applications are not active at the same time. (Code)

– Use NAND flash memory as the backing storage for Swap in / out
on demand
demand paging
NAND
– Advantages (Data)
• Space utilization
(Code)
• Power consumption
• Flexible
– Requires MMU (Memory Management Unit) NOR / EPROM
(Boot Code)

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Memory architecture for mobile embedded system: Data storage

• MultiMedia Card (MMC) / CompactFlash

– Host independence from details of erasing and
programming flash memory
– Sophisticated system for error (bad blocks, ECC)
– Power management for low power operation
– CompactFlash does not have any built in digital rights
management (DRM)
– Standard SD: 1 MB to 4 GB
SDHC: 4 GB to 32 GB
SDXC: 32 GB to 2 TB
Note:
Advanced Microcontroller Bus Architecture (AMBA) has
•Advanced eXtensible Interface (AXI)
•Advanced High-performance Bus (AHB)
•Advanced System Bus (ASB)
•Advanced Peripheral Bus (APB)

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 Memory architecture for mobile embedded system: 3G Cellular Phones

• 3G Phone with full-featured OS-based

Code execution

Buffer for DSP

Data and OS File

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 Memory architecture for smart phone processor

• A smart phone processor

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 Course Overview
Assembler

Instruction Set Architecture

Memory I/O System

Datapath & Control

Introduction to Basic Computer
Embedded Systems Structure
MCU Main Board

Digital and Analog

Interfacing USART, IEEE1394,
USB, I2C and SPI

Microcontroller Structure
A/D Port
Buffering and
Serial Port Direct Memory Access
CPU (DMA)
External Memory Port
Memory,
Interfacing to Memory,
External Interrupt Port
Memory Timing
Interrupt and applications
External Timer Port Interfacing LCD
Organization Timer and
Counter Simple I/O Port
Motor Interfacing

In this course, STM32 is used as a driving vehicle for delivering the concepts.
To be covered In progress Done

ELEC 3300 : Spring 17/18 Tim Woo 34

 Reflection (Self-evaluation)
• Do you …
– List several types of memory technologies ?
– Design both hardware and software memory interfacing ?
– Understand key considerations of memory architectures?
– Have a overview of memory architecture for mobile embedded
systems?
– List upcoming memory architecture?

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