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Computer Organization Exercise Answer8

The document discusses cache mapping for various memory addresses. It is asked to determine the block number that different memory addresses map to, given a cache with 64 blocks of 16 bytes each. Addresses 1728, 876 and 4 are provided. The summary calculates the block address by dividing the memory address by the block size in bytes. It then takes the modulo of the block address and the total number of blocks to determine the block number.

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116 views

Computer Organization Exercise Answer8

The document discusses cache mapping for various memory addresses. It is asked to determine the block number that different memory addresses map to, given a cache with 64 blocks of 16 bytes each. Addresses 1728, 876 and 4 are provided. The summary calculates the block address by dividing the memory address by the block size in bytes. It then takes the modulo of the block address and the total number of blocks to determine the block number.

Uploaded by

RD
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Architecture

Fall, 2022
Week 3
2021.09.26

組別：＿＿＿＿＿ 簽名：＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿
＿＿＿＿＿＿＿＿＿

[Group10]
Caches are important to providing a high-performance memory hierarchy to
processors. Below is a list of 32-bit memory address references, given as word
addresses.
3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253

For each of these references, identify the binary word address, the tag, the index,
and the offset given a direct-mapped cache with two-word blocks and a total size of
eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially
empty.

Ans:
[Group11]

Given the following code snippets, select the one that has better performance and
explain why.

1. Suppose the 2d-array x is in row major order (x[i] [j] and x[i] [j+1] is adjacent)

(a)
for (i =0; i <5000; i=i+1){
for (j =0; j<100; j=j+1){
x[i][j] = 2*x[i][j];
}
}
(b)
for (j = 0; j < 100; j= j+1){
for (i=0; i<5000; i=i+1){
x[i][j] = 2*x[i][j];
}
}

2. NxN Matrix Multiplication (N=9)

(a)
for (i = 0; i< N; i=i+1){
for (j =0; j < N; j = j+1){
r = 0;
for (k = 0; k<N; k = k +1){
r = r + y[i][k] * z[k][j];
}
x[i][j] = r;
}
}

(b)
for (jj = 0; jj < N; jj = jj+3){
for (kk = 0; kk < N; kk = kk+3){
for (i = 0; i<N; i= i+1){
for (j = jj; j<min(jj+3,N); j= j+1){
r = 0;
for (k = kk; k <min(kk+3,N); k=k +1){
r = r + y[i][k] * z[k][j];
}
x[i][j] = x[i][j] + r;
}
}
}
}

Answer:

1. (a)Since the 2d-array is in row major, we can improve spatial locality by loop
interchange.
2. (b) Improve temporal locality by blocking

[Group7]
Please answer the following questions using the caches with the following property
respectively:
i. 32 bytes per block, 256 blocks in a cache
ii. 16 bytes per block, 1024 blocks in a cache
iii. 128 bytes per block, 128 blocks in a cache
1. Subdivide the memory address for a 32-bit word into tag, index, and offset.
2. What does 34464(10) = 86A0(16) map with the above caches?

1.
i. 19-bit tag, 8-bit index, 5-bit offset
ii. 18-bit tag, 10-bit index, 4-bit offset
iii. 18-bit tag, 7-bit index, 7-bit offset
2.
i. tag = 4, index = 53, offset = 0
ii. tag = 2, index = 106, offset = 0
iii. tag = 2, index = 13, offset = 32
[Group3]
(A) DRAM is slow but cheap and dense; SRAM is fast but expensive, not very dense.
(B) Cache is the component with the highest level in the memory hierarchy.
(C) The main reason we need cache is the performance gap between Memory and
CPU
(D) SRAM is faster than DRAM, and both of their access time for all locations are the
same (random access)
(E) If cache has 64 blocks and each block has 16 bytes/block. The cache block
number which addresses 1200 map is 0010112
(F) SRAM and DRAM are both volatile memories.
(G) For upper level, DRAM is a better choice than SRAM because upper level needs
to be faster and smaller.
(H) In direct map cache, if we access to a location in cache with valid bit = 1, there is
no cache miss.

Ans
(A) TRUE
(B) False. Should be register.
(C) True, because of Moore's Law, the performance gap grows fast.
(D) True
(E) True
(F) False. Some types of SRAM are non-volatile, e.g., Non-volatile SRAM.
(G) False, SRAM is a better choice than DRAM
(H) False, the tag might be wrong.
[Group5]
1.Please choose the correct answer. (If it is wrong, please provide reasons.)
(A) Although DRAM needs to be refreshed to prevent data missing, it’s cheaper and
faster than SRAM.
(B)Loop is an example of Temporal locality.
(C)The unit of swapping data between Cache and Memory is Blocks, and is managed
by the OS.
(D)we need to save the full address as tag in Cache.
(E)write buffer is FIFO.
(F)the larger block size of cache, the larger miss penalty.
Ans: B E F
(A)Wrong, DRAM is slower than SRAM.
(C)Wrong, is managed by cache controller.
(D)Wrong, only need the high-order bits.
[Group 6]
a. In a fixed-sized cache, the larger the block size is, the lower the miss rate will
be, because of the Spatial Locality.
b. We can apply some techniques of hash to do the Block Placement.
c. Using direct mapping, to know which particular block is stored in a cache
location, we also need to store the whole memory address of the block in the Tag file
as well as data.
d. Using direct mapping, for a cache with 32-bits memory address、2K words、1
word per block , there are 20-bits Tag and 10-bits Index in the cache table.

Ans:
a. False, miss rate may increase when block size becomes larger.
b. Ture, e.g. Direct Mapped.
c. Flase, Tag only needs to store the higher bits.
d. Flase, 19-bits Tag and 11-bits Index

[Group14]
1. Assuming a cache of 64 blocks with 16 bytes per block, to which block
numbers do the following addresses map?
a. 1728
b. 876
c. 4

ans:
a. Block address: [1728/16] = 108
Block number: 108 modulo 64 = 44
b. Block address: [876/16] = 54
Block number: 54 modulo 64 = 54
c. Block address: [4/16] = 0
Block number: 0 modulo 64 = 0

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