Objectives:

The main objective of VLSI lab is to enhance the knowledge in designing combinational and
sequential digital circuits using Very High Speed Integrated Circuit Hardware Description Language
(VHDL).In this lab uses Xilinx ISE (Integrated Software Environment) software tool produced by
Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile")
their design, simulate the outputs, examine RTL diagrams and configure the target device with the
programmer.

.
Contents
 1. Design of Adder/Subtractor

Aim

To design a Four-bit Adder/Subtractor using VHDL.

Apparatus required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

An Adder/Subtractor is a combinational circuit that is capable of adding or subtracting binary numbers.

The choice of addition or subtraction operation is based on the value of control input ‘M’. When the control
input, M=0 the circuit performs addition operation and if M=1, the circuit performs subtraction operation. The
design is based on the fact that subtraction operation can be realized using an adder by complementing (2’s
complement) subtrahend and adding with minuend. A four-bit adder/subtractor circuit can be realized from four
full-adders and four X-OR gates, where carry-out of each full-adder is connected to carry-in of next higher
order full-adder. This type of adder is called ripple carry adder.

Procedure:

1. A VHDL program source code for the 4bit adder circuit is written and typed in the workspace.
2. It is implemented in xilinxISE simulator and Simulated.
3. Signals are provided and Output Waveforms are viewed.
4. Results are verified using FPGA trainer kit.
Four-Bit Adder/Subtractor

Waveform:

A
4’b1001 4’b0101 4’b1000

4’b1000 4’b0011 1001

S
4’b0001 4’b0010 4’b1111

Cout
Program

VHDL code for 4-Bit Adder/Subtractor Design

Library ieee;

use ieee.std_logic_1164.all;

entity addsub is

port (a,b: in std_logic_vector(3 downto 0);

s: out std_logic_vector(3 downto 0);

m: in std_logic;

cout: out std_logic);

end addsub;

architecture structural of addsub is

component logic_xor is

port (a, b : in std_logic ; z: out std_logic);

end component;

component fulladder is

port (a, b, c : in std_logic; sum, carry : out std_logic);

end component;

signal d0, d1, d2, d3, c0, c1, c2: std_logic;

begin

g0: logic_xor port map (m, b(0) , d0);

g1: logic_xor port map (m, b(1), d1);

g2: logic_xor port map (m, b(2), d2);

g3: logic_xor port map (m, b(3), d3);

FA0: fulladder port map (a(0) ,d0, m, s(0), c0);

FA1: fulladder port map (a(1), d1, c0, s(1), c1);

FA2: fulladder port map (a(2), d2, c1, s(2), c2);

FA3: fulladder port map (a(3), d3, c2, s(3), cout);

end structural;

- -submodule logic_xor

library ieee;

use ieee.std_logic_1164.all;

entity logic_xor is

port( a, b: in std_logic ; z: out std_logic);

end logic_xor;

architecture behavioral of logic_xor is

begin

z < = a xor b;

end behavioral;

- -submodule fulladder

Library ieee;

use ieee.std_logic_1164.all;

entity fulladder is

port( a, b, c: in std_logic ; sum, carry: out std_logic);

end fulladder;

Result

The four-bit adder/subtractor is designed using VHDL and its functionality has been verified
 2. Design of BCD Adder

Aim

To design Four-bit BCD Adder using VHDL.

Apparatus required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

A BCD (Binary Coded Decimal) adder consists of two binary 4-bit parallel adders and a few
combinational gates. The first 4-bit adder sums the two BCD inputs, resulting in a binary representation of this
sum. The second 4-bit adder and combinational logic converts the output of the first 4-bit adder from binary to
BCD. The highest possible value that can result from summing two BCD numbers and a carry bit is 19 (1001 +
1001 + 1 = 1910). Table 2.1 lists the possible binary outputs from the first 4-bit adder, along with the desired
BCD correction.

• If the sum is between 0 and 9, then no correction is needed, i.e nothing is added to binary sum.

• If the sum is between 10 and 19, then the carry bit becomes a ‘1’ and binary value 0110 is added to binary sum
through the bottom 4-bit binary adder.

The output carry can be expressed in Boolean function cout = s4 + s3s2 + s3s1

Procedure:

1. A VHDL program source code for the 4bit adder circuit is written and typed in the workspace.
2. It is implemented in xilinxISE simulator and Simulated.
3. Signals are provided and Output Waveforms are viewed.
4. Results are verified using FPGA trainer kit.
Possible sum outputs of BCD addition of two four bit numbers

BINARY SUM BCD SUM DECIMAL

S4 S3 S2 S1 S0 Z4 Z3 Z2 Z1 Z0

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 2

0 0 0 1 1 0 0 0 1 1 3

0 0 1 0 0 0 0 1 0 0 4

0 0 1 0 1 0 0 1 0 1 5

0 0 1 1 0 0 0 1 1 0 6

0 0 1 1 1 0 0 1 1 1 7

0 1 0 0 0 0 1 0 0 0 8

0 1 0 0 1 0 1 0 0 1 9

0 1 0 1 0 1 0 0 0 0 10

0 1 0 1 1 1 0 0 0 1 11

0 1 1 0 0 1 0 0 1 0 12

0 1 1 0 1 1 0 0 1 1 13

0 1 1 1 0 1 0 1 0 0 14

0 1 1 1 1 1 0 1 0 1 15

1 0 0 0 0 1 0 1 1 0 16

1 0 0 0 1 1 0 1 1 1 17

1 0 0 1 0 1 1 0 0 0 18

1 0 0 1 1 1 1 0 0 1 19
Four bit BCD adder

Waveform:

A 4’b1001 4’b0001 4’b 0101

4’b0010 4’b 1000 4’b1001

B

Cin

4’b0001 4’b1010 4’b0101

Z

Cout
Program

VHDL Code For 4-Bit BCDadder

Library ieee;

use ieee.std_logic_1164.all;

entity bcdadder is

port (a, b : in std_logic_vector (3 downto 0);

cin: in std_logic;

z : out std_logic_vector (3 downto 0);

cout : out std_logic);

end bcdadder;

architecture structural of bcdadder is

component fulladder is

port (a, b, c : in std_logic; sum, carry : out std_logic);

end component;

component logic_and is

port (a, b : in std_logic; z : out std_logic);

end component;

component logic_or is

port(a, b, c : in std_logic; z : out std_logic);

end component;

signal s0, s1, s2, s3, s4, s5, s6, s7, c0, c1, c2, c3, c4, c5, c6 : std_logic;

begin

fa0: fulladder port map (a(0), b(0), cin, s0, c0);

fa1: fulladder port map (a(1), b(1), c0, s1, c1);

fa2: fulladder port map (a(2), b(2), c1, s2, c2);

fa3 : fulladder port map (a(3), b(3), c2, s3, s4);

fa4: fulladder port map (s0, '0', '0', z(0), c3);

fa5 : fulladder port map (s1, s7, c3, z(1), c4);

fa6: fulladder port map (s2, s7, c4, z(2), c5);

fa7: fulladder port map (s3, '0', c5, z(3), c6);

x1: logic_and port map (s3, s2, s6);

x2: logic_and port map (s3, s1, s7);

x3: logic_or port map (s4, s6, s7, s5);

cout<=s5;

end structural;

- -submodule Fulladder

library ieee;

use ieee.std_logic_1164.all;

entity fulladder is

port (a, b, c : in std_logic; sum, carry : out std_logic);

end fulladder;

architecture behavioral of fulladder is

begin

sum < = a xor b xor c;

carry < = (a and b) or (b and c) or ( c and a);

end behavioral;

- -submodule logic_and

library ieee;

use ieee.std_logic_1164.all;
entity logic_and is

port(a, b: in std_logic; z: out std_logic);

end logic_and;

architecture behavioral of logic_and is

begin

z < = a and b;

end behavioral;

- -submodule logic_or

library ieee;

use ieee.std_logic_1164.all;

entity logic_or is

port(a, b , c: in std_logic; z: out std_logic);

end logic_or;

architecture behavioral of logic_or is

begin

z <= a or b or c;

end behavioral;

Result

The four-bit BCD adder is designed using VHDL and its functionality has been verified
 3. a ) Design of Multiplexer

Aim

To design a 4 to 1 multiplexer using VHDL.

Apparatus required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

A Digital multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. Multiplexing in the sense is transmitting a large number of
information units over a smaller number of channels or lines. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2n input lines and n selection lines whose bit
combinations determine which input is to be selected. Multiplexer circuits may have an enable input to control
the operation of the unit. The enable input (sometimes called strobe) can be used to expand two or more
multiplexers to digital multiplexers with larger number of inputs. The size of the multiplexer is specified by the
number of input lines and the single output line. The Boolean functions for the output of 4 to 1 multiplexer is

Y = ( S1’.S0’.I) + (S1’.S0.I1) + (S1.S0’.I2) + (S1.S0.I3).

Procedure:

1. The 4 to 1 multiplexer circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in ISE simulator and Simulated.
4. Signals are provided and Output Waveforms are viewed.
5. Results are verified in Spartan FPGA.
4 TO 1 MULTIPLEXER

Block Diagram

Truth Table

Control Inputs Output

Select lines Enable Y

S1 S0 E

X X 0 0

0 0 1 I0

0 1 1 I1

1 0 1 I2

1 1 1 I3
LOGIC DIAGRAM FOR 4 TO 1 MULTIPLEXER

Waveform

S1

S0

I0

I1

I2

I3

Y
Program

VHDL code for 4 to 1 multiplexer

Library ieee;

use ieee.std_logic_1164.all;

entity multiplexer is

port(i0, i1, i2 ,i3 , s0 ,s1 , enable : in std_logic;

y :out std_logic);

end multiplexer;

architecture structural of multiplexer is

component logic_invt is

port(s: in std_logic; sbar : out std_logic);

end component;

component logic_and is

port (a, b, c, d : in std_logic; z : out std_logic);

end component;

component logic_or is

port (a, b, c, d : in std_logic; z : out std_logic);

end component;

signal sbar0, sbar1, w0, w1, w2, w3:std_logic;

begin

g1: logic_invt port map (s0, sbar0);

g2: logic_invt port map (s1, sbar1);

g3: logic_and port map (i0, sbar0, sbar1, enable, w0);

g4: logic_and port map (i1, sbar1, s0, enable, w1);

g5: logic_and port map (i2, s1, sbar0, enable, w2);

g6: logic_and port map (i3, s1, s0, enable, w3);

g7 : logic_or port map (w0 ,w1, w2, w3 , y);

end structural;

- -submodule logic_invt

library ieee;

use ieee.std_logic_1164.all;

entity logic_invt is

port(s: in std_logic; sbar : out std_logic);

end logic_invt ;

architecture behavioral of logic_invt is

begin

sbar< = not s;

end behavioral;

- -submodule logic_and

library ieee;

use ieee.std_logic_1164.all;

entity logic_and is

port(a, b , c , d: in std_logic; z: out std_logic);

end logic_and;
architecture behavioral of logic_and is

begin

z < = a and b and c and d;

end behavioral;

- -submodule logic_or

library ieee;

use ieee.std_logic_1164.all;

entity logic_or is

port(a, b , c , d: in std_logic; z: out std_logic);

end logic_or;

architecture behavioral of logic_or is

begin

z < = a or b or c or d;

end behavioral;

Result

The 4 to 1 multiplexer is designed using VHDL and its functionality has been verified.
 3. b) Realiztion of De-Multiplexer

Aim

To design a 1 to 4 De-multiplexer using VHDL.

Apparatus required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

The De-multiplexer performs the reverse operation of a multiplexer. It is a combinational circuit which
accepts a single input and distributes it overall several outputs. The selection of a particular output line is
controlled by a set of selection lines. Normally, there are 2n output lines and n selection lines. De-multiplexer
circuit may have an enable input to control the operation of the unit. The circuit functions as normal de-
multiplexer only if the enable or strobe input line is activated. The size of the de-multiplexer is specified by the
single input line and the number 2n of its output lines. The Boolean functions for the outputs of 1 to 4 De-
multiplexer are

D0 = S1’.S0’.I; D1 = S1’.S0.I; D2 = S1.S0’.I; D3 = S1.S0.I.

Procedure:

1. The 1 to 4 demultiplexer circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in xilinxISE simulator and Simulated.
4. Signals are provided and Output Waveforms are viewed.
5. Results are verified in Spartan FPGA.
1 to 4 De-multiplexer

Block Diagram

Truth Table

Control inputs Outputs

Select lines Enable

S1 S0 E D0 D1 D2 D3

X X 0 0 0 0 0

0 0 1 I 0 0 0

0 1 1 0 I 0 0

1 0 1 0 0 I 0

1 1 1 0 0 0 I
LOGIC DIAGRAM FOR 1 TO 4 DE-MULTIPLEXER

Waveform:

S1

S0

I0

Y0

Y1

Y2

Y3
Program

VHDL code for 1 to 4 de multiplexer

Library ieee;

use ieee.std_logic_1164.all;

entity demultiplexer is

port(i , s0 ,s1 , enable : in std_logic;

y0, y1, y2, y3 :out std_logic);

end demultiplexer;

architecture structural of demultiplexer is

component logic_invt is

port(s: in std_logic; sbar : out std_logic);

end component;

component logic_and is

port (a, b, c, d : in std_logic; z : out std_logic);

end component;

signal sbar0, sbar1:std_logic;

begin

g1: logic_invt port map (s0, sbar0);

g2: logic_invt port map (s1, sbar1);

g3: logic_and port map (i, sbar0, sbar1, enable, y0);

g4: logic_and port map (i, sbar1, s0, enable, y1);

g5: logic_and port map (i, s1, sbar0, enable, y2);

g6: logic_and port map (i, s1, s0, enable, y3);

end structural;
- -submodule logic_invt

library ieee;

use ieee.std_logic_1164.all;

entity logic_invt is

port(s: in std_logic; sbar : out std_logic);

end logic_invt ;

architecture Behavioral of logic_invt is

begin

sbar<= not s;

end Behavioral;

- -submodule logic_and

library ieee;

use ieee.std_logic_1164.all;

entity logic_and is

port(a, b , c , d: in std_logic; z: out std_logic);

end logic_and;

architecture behavioral of logic_and is

begin

z < = a and b and c and d;

end behavioral;

Result

The 1 to 4 de-multiplexer is designed using VHDL and its functionality has been verified.
 4. Design of 4-bit magnitude comparator

Aim

To design a four-bit magnitude comparator using VHDL.

Requirements

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

A Four-bit comparator compares two four-bit binary words, A and B, and asserts outputs indicating
whether the decimal equivalent of word A is less than, greater than, or equal to that of word B. A four-bit
comparator can be implemented from two two-bit comparators with additional logic to generate the appropriate
outputs that result from comparing four-bit binary words. The logic for connecting the two-bit comparators is
based on the observation that a strict inequality in the higher order bit pairs determines relative magnitude of the
four-bit words; on the otherhand, if the high order bit pairs are equal, the lower–order bit pairs determine the
output. The simplified Boolean equations for the three outputs of two-bit comparator are

(X > Y) X.gt. Y = (X0 Y1’ Y0’) + (X1 Y1’) + (X1 X0 Y0’)

(X =Y) X .eq.Y = (X0 Y0) (X1 Y 1)

(X < Y) X .lt.Y = (X1’ X0’ Y0) + (X0’ Y1 Y0) + (X1’ Y1)

Procedure:

1. The VHDL program source code for the comparator circuit is written and typed in the workspace.
2. It is implemented in xilinxISE simulator and Simulated.
3. Signals are provided and Output Waveforms are viewed.
4. Results are verified in Spartan FPGA.
Truth Table for 2-bit comparator

INPUTS OUTPUTS

X1 X0 Y1 Y0 X.gt.Y X.eq.Y X.lt.Y

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

Hierarchical Structure of four-bit Comparator

Program

VHDL Code for Four-bit Comparator

Library ieee;

Use ieee.std_logic_1164.all;

entity comparator is

port(a, b: in std_logic_vector (3 downto 0);

a_gt_b, a_eq_b, a_lt_b : out std_logic);

end comparator;

architecture structural of comparator is

component twobit_comp is

port (x1, x0, y1, y0: in std_logic);

xgty, xeqy, xlty: out std_logic);

end component;

component logic_and is

port (a, b : in std_logic; z : out std_logic);

end component;

component logic_or is

port (a, b : in std_logic; z : out std_logic);

end component;

signal h0, h1, h2, L0, L1,L2, s0, s1:std_logic;

begin

c1: twobit_comp port map(a(3), a(2), b(3), b(2), h0, h1, h2);

c2: twobit_comp port map(a(1), a(0), b(1), b(0), L0,L1,L2);

g1: logic_and port map (h1, L1, a_eq_b);

g2: logic_and port map (h1, L0, s0);

g3: logic_and port map (h1, L2, s1);

g4: logic_or port map (h0, s0, a_gt_b);

g5: logic_or port map (h2, s1, a_lt_b);

end structural;

- -submodule twobit_comp

Library ieee;

Use ieee.std_logic_1164.all;

entity twobit_comp is

port (x1, x0, y1, y0: in std_logic);

xgty, xeqy, xlty: out std_logic);

end twobit_comp;

architecture behavioral of twobit_comp is

signal x1bar,x0bar,y1bar,y0bar: std_logic;

begin

x1bar<= not x1;

x0bar<= not x0;

y1bar<= not y1;

y0bar<= not y0;

xgty < = (x1 and y1bar) or (x0 and y1bar and y0bar) or (x1 and x0 and y0bar);

xeqy < = (x1 xnor y1) and (x0 xnor y0) ;

xlty < = (x1bar and y1) or (x0bar and y1 and y0) or (x1bar and x0bar and y0);

end behavioral;
- -submodule logic_and

library ieee;

use ieee.std_logic_1164.all;

entity logic_and is

port(a,b : in std_logic; z: out std_logic);

end logic_and;

architecture behavioral of logic_and is

begin

z < = a and b ;

end behavioral;

- -submodule logic_or

library ieee;

use ieee.std_logic_1164.all;

entity logic_or is

port(a, b: in std_logic; z: out std_logic);

end logic_or;

architecture behavioral of logic_or is

begin

z < = a or b ;

end behavioral;
Waveform

a
4’b1001 4’b1010 4’b1010

b
4’b1100 4’b1010 4’b0010

a_lt_b

a_gt_b

a_eq_b

Result

The four-bit magnitude comparator is designed using VHDL and its functionality has been verified.
 5. Design of Array Multiplier

Aim:

To design an array multiplier circuit for 4 inputs and 8 outputs using VHDL.

Apparatus required

1. Simulation and synthesis tool: Xilinx ISE.

2. Xilinx Spartan FPGA

Theory:

Binary multiplication can be accomplished by several approaches. The approach presented here is
realized entirely with combinational circuits. Such a circuit is called an array multiplier.

The term array is used to describe the multiplier because the multiplier is organized as an array
structure. Each row, called a partial product, is formed by a bit-by-bit multiplication of each operand.

For example, a partial product is formed when each bit of operand ‘a’ is multiplied by b0, resulting
in a3b0, a2b0,a1b0, a0b0. The binary multiplication table is identical to the AND truth table.

Each product bit {o(x)}, is formed by adding partial product columns. The product equations,
including the carry-in {c(x)}, from column c(x-1), are (the plus sign indicates addition not OR).

Each product term, p(x), is formed by AND gates and collection of product terms needed for the
multiplier. By adding appropriate p term outputs, the multiplier output equations are realized, as shown in
figure.

a3 a2 a1 a0 x b3 b2 b1 b0

a3 b0 a2 b0 a1b0 a0b0

a3b1 a2b1 a1b1 a0b1

a3b2 a2b2 a1b2 a0b2

a3b3 a2b3 a1b3 a0b3

O7 O6 O5 O4 O3 O2 O1 O0
Partial Products

Each row, called partial product, is formed by bit-by-bit multiplication of each operand. For example a partial
product is formed when each bit of operand a is multiplied by b0 resulting in a3 b0, a2 b0, a1b0 and a0b0. Each
product bit Ox is formed by adding partial product columns. The product equations including the carry-in, C x
from column (x-1), are

O0 = a0b0

O1 = a1b0 + a0b1 + C0

O2 = a2b0 + a1b1 + a0b2 + C1

O3 = a3 b0 + a2b1 + a1b2 + a0b3 + C2

O4 = a3b1 + a2b2 + a1b3 + C3

O5 = a3b2 + a2b3 + C4

O6 = a3b3 + C5

O7 = C6
Each product term Px is formed by AND gates. By adding appropriate product term outputs the multiplier
equations are realized. The adders are arranged in a carry-save chain where, the carry-out bits are fed to the next
available adder in the column to the left.

Procedure

1. A VHDL program source code for the multiplier circuit is typed in the workspace.
2. It is implemented in ISE simulator and Simulated.
3. Signals are provided and Output Waveforms are viewed.
4. Results are verified in Spartan FPGA.

Four-bit Array Multiplier

FA – Full Adder

HA – Half Adder
Program

VHDL code for Array Multiplier:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ary4x4multiplier is

Port ( a : in STD_LOGIC_vector(0 to 3);

b : in STD_LOGIC_vector(0 to 3);

op : out STD_LOGIC_vector(0 to 7));

end ary4x4multiplier;

architecture Behavioral of ary4x4multiplier is

component halfadder is

port (a, b : in std_logic; sum, carry : out std_logic);

end component;

component fulladder is

port (a, b, c : in std_logic; sum, carry : out std_logic);

end component;

signal prodt : STD_LOGIC_vector(0 to 15);

signal hasm : STD_LOGIC_vector(1 to 4);

signal hacy : STD_LOGIC_vector(1 to 4);

signal fasm : STD_LOGIC_vector(1 to 8);

signal facy : STD_LOGIC_vector(1 to 8);

begin

prodt(0) <= a(3) and b(3);

prodt(1) <= a(2) and b(3);

prodt(2) <= a(3) and b(2);

prodt(3) <= a(1) and b(3);

prodt(4) <= a(2) and b(2);

prodt(5) <= a(3) and b(1);

prodt(6) <= a(0) and b(3);

prodt(7) <= a(1) and b(2);

prodt(8) <= a(2) and b(1);

prodt(9) <= a(3) and b(0);

prodt(10) <= a(0) and b(2);

prodt(11) <= a(1) and b(1);

prodt(12) <= a(2) and b(0);

prodt(13) <= a(0) and b(1);

prodt(14) <= a(1) and b(0);

prodt(15) <= a(0) and b(0);

op(7) <= prodt(0);

k1: halfadder port map(prodt(1),prodt(2),hasm(1),hacy(1));

op(6) <= hasm(1);

k2: halfadder port map(prodt(3),prodt(4),hasm(2),hacy(2));

k3: fulladder port map(prodt(5),hasm(2),hacy(1),fasm(1),facy(1));

op(5) <= fasm(1);

k4: halfadder port map(prodt(6),prodt(7),hasm(3),hacy(3));

k5: fulladder port map(prodt(8),hacy(2),hasm(3),fasm(2),facy(2));

k6: fulladder port map(prodt(9),fasm(2),facy(1),fasm(3),facy(3));

op(4) <= fasm(3);

k7: fulladder port map(prodt(10),prodt(11),hacy(3),fasm(4),facy(4));

k8: fulladder port map(prodt(12),fasm(4),facy(2),fasm(5),facy(5));

k9: halfadder port map(fasm(5),facy(3),hasm(4),hacy(4));

op(3) <= hasm(4);

k10: fulladder port map(prodt(13),prodt(14),facy(4),fasm(6),facy(6));

k11: fulladder port map(fasm(6),facy(5),hacy(4),fasm(7),facy(7));

op(2) <= fasm(7);

k12: fulladder port map(prodt(15),facy(6),facy(7),fasm(8),facy(8));

op(1) <= fasm(8);

op(0) <= facy(8);

end Behavioral;

- -submodule halfadder

library ieee;

use ieee.std_logic_1164.all;

entity halfadder is

port (a,b: in std_logic; sum,carry : out std_logic);

end halfadder;

architecture behavioral of halfadder is

begin

sum <= a xor b;

carry <= a and b;

end behavioral;
- -submodule Fulladder

Library ieee;

use ieee.std_logic_1164.all;

entity fulladder is

port( a, b, c: in std_logic ; sum, carry: out std_logic);

end fulladder;

architecture behavioral of fulladder is

begin

sum < = a xor b xor c;

carry < = (a and b) or (b and c) or ( c and a);

end behavioral;

Waveform:

Result:

The array multiplier is designed in VHDL and the output is verified.

 6. Design of Flipflops

Aim

To design S-R, J-K, D and T Flip-flops using VHDL.

Apparatus required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

The Flip-flop is an electronic circuit (bi-stable multivibrator) that has two stable states and therefore
they are commonly used memory devices in sequential circuits. The flip-flop can be realized using NAND or
NOR gates. The flip-flop is usually controlled by one or two control signals and/or gate or clock signal. The
output often includes the complement as well as the normal output. The names flip-flops and latches are
sometimes used interchangeably; however, the term flip-flop is more appropriately associated with devices that
change state only on a clock edge or pulse whereas latches change state without being clocked. Four types of
flip-flops are commonly considered: SR, JK, D and T.

i) S-R flip-flop
An S-R flip-flop is similar to an S-R latch in that S=1 sets the Q output to 1, and R=1 resets Q
output to 0. The essential difference is that the flip-flop has clock input and the Q output can change
only after an active clock edge. When both S and R inputs are 0 the state of the flip-flop output Q
does not change. When both S and R inputs are high, state of the flip-flop output Q is
indeterminate. The characteristic equation for S-R flip-flop is Q t+1 = S+R’Qt .
ii) J-K flip-flop
The J-K flip-flop does not have an indeterminate input combination as in the S-R flip-flop. The J
and K inputs are analogous to the S (set) and R (reset) inputs respectively of S-R flip-flop. The
indeterminate input condition of the R-S latch causes the J-k flip-flop to toggle; when J=K=1
then . This toggling phenomenon is accomplished by connecting Q’ and Q outputs back to J and K
excitation inputs. The characteristic equation for J-K flip-flop is Q t+1 =JQt’+K’Qt.
 iii) D flip-flop
The data or D fip-flophas two inputs D and clock. The output changes only in response to the clock
edge. The state of the flip-flop after the active clock edge (Q t +1) is equal to the input (D) before the
active edge. The characteristic equation of the D flip-flop is Q t+1 = D.

iv) T flip-flop
In the T flip-flop also called the toggle flip-flop, when T = 1 the flip-flop changes the state after the
active edge of clock. When T = 0 no change of state occurs. The characteristic equation for T flip-
flop is Qt+1 = T Qt ..
Procedure
1. The VHDL program source code for the flipflops are typed in the workspace.
2. It is implemented in xilinxISE simulator and Simulated.
3. Signals are provided and Output Waveforms are viewed.
4. Results are verified in Spartan FPGA.
S-R FLIP-FLOP

Truth table

INPUTS OUTPUTS STATE

CLK S R Qt Qt+1

^ 0 0 0 0 NO CHANGE

^ 0 0 1 1 NO CHANGE

^ 0 1 0 0 RESET

^ 0 1 1 0 RESET

^ 1 0 0 1 SET

^ 1 0 1 1 SET

^ 1 1 0 X INDETERMINATE

^ 1 1 1 X INDETERMINATE

0 X X 0 0 NO CHANGE

0 X X 1 1 NO CHANGE

Logic Diagram
J-K FLIP-FLOP

Truth Table

PREVIOUS INPUTS OUTPUTS

STATE

Qt J K Qt+1

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Logic Diagram
D FLIP-FLOP
Truth table

INPUT OUTPUT STATE

CLK D Qt Qt+1

^ 0 X 0 RESET

^ 1 X 1 SET

0 X X Qt NO
CHANGE

Logic Diagram
T FLIP-FLOP
Truth table

REVIOUS INPUT OUTPUT

STATE

Qt T Qt+1

0 0 0

0 1 1

1 0 1

1 1 0

Logic Diagram
Program
VHDL code for D-flipflop
Library ieee;
Use ieee.std_logic_1164.all;

entity d_flipflop is
port (d, clock, reset : in std_logic; q, qbar: inout std_logic);
end d_flipflop ;

architecture behavioral of d_flipflop is

begin
process (clock, reset)
begin
if reset= '1’ then
q < = '0';
elsif clock'event and clock='1' then
q < = d;
end if;
end process;
qbar < = not q;
end behavioral;
VHDL CODE FOR T- FLIPFLOP

Library ieee;
Use ieee.std_logic_1164.all;

entity t_flipflop is
port (t, clock, reset : in std_logic; q, qbar: inout std_logic);
end t_flipflop ;

architecture behavioral of t_flipflop is

begin
process (clock, reset)
begin
if reset= '1’ then
q < = '0';
elsif clock'event and clock='1' then
case t is
when ‘0’ = > q < = q;
when ‘1’ = > q < = not q;
when others = > q < = ‘-’ ;
end case;
end if;
end process;
qbar < = not q;
end behavioral;
VHDL CODE FOR SR- FLIPFLOP

Library ieee;
Use ieee.std_logic_1164.all;

entity sr_flipflop is
port (s ,r , clock, reset : in std_logic; q, qbar: inout std_logic);
end sr_flipflop ;

architecture behavioral of sr_flipflop is

begin

process(clock,reset)

variable s_r : std_logic_vector (1 downto 0);

begin

if reset = ' 1' then

q < = '0';

elsif clock'event and clock= '1' then

s_r := (s & r);

case s_r is
when "00" = > q < = q;

when "01" => q < = '0';

when "10" = > q < = '1';

when "11"= > q < = '-';

when others = > q < = '-’ ;

end case;

end if;

end process;

qbar < = not q;

end behavioral;
VHDL CODE FOR JK- FLIPFLOP

Library ieee;
Use ieee.std_logic_1164.all;
entity jk_flipflop is
port (j ,k , clock, reset : in std_logic; q, qbar: inout std_logic);
end jk_flipflop ;

architecture behavioral of jk_flipflop is

begin

process(clock,reset)

variable j_k: std_logic_vector(1 downto 0);

begin

if reset = ' 1' then

q < = '0';

elsif clock'event and clock= '1' then

j_k := j & k;

case j_k is
when "00" = > q < = q;

when "01" => q < = '0';

when "10" = > q < = '1';

when "11"= > q < = not q;

when others = > q < = '- ;

end case;

end if;

end process;

qbar < = not q;

end behavioral;

Result: The S-R, J-K, D and T flip-flops are designed using VHDL and their functionalities have been
verified.
 7.Design of Synchronous Counters

Aim

To design a three-bit synchronous up and down counters using VHDL.

Apparatus required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

In Synchronous counters, all the flip-flops are triggered by same clock pulse thus all the flip-flops
change their states simultaneously. Synchronous counters have regular pattern and can be easily constructed
with complementing flip-flops (J-K with J and K tied or T type) and logic gates. Synchronous binary counter
can be classified into two types: up-counter, which increments its output by one for every clock transition and
down-counter, which decrements its output by one for every clock transition. In up-counters, the flip-flop in the
LSB position is complemented for every clock whereas other flip-flops are complemented only when all their
lower order bits are equal to 1. Similarly, for down-counters the flip-flop in the LSB position is complemented
for every clock whereas other flip-flops are complemented only when all their lower order bits are equal to 0.

Procedure:

1. A VHDL program source code for the circuit is typed in the workspace.
2. It is implemented in xilinxISE simulator and Simulated.
3. Signals are provided and Output Waveforms are viewed.
Excitation table for three-bit synchronous up-counter

Present State Next State Flip-flop inputs

Q2 Q1 Q0 Q2 Q1 Q0 T2 T1 T0

0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Flip-flop input equations

(J-K)2 = T2 = Q1 . Q0 , (J-K)1 = T1 = Q0 (J-K)0 = T0 =1

Three-bit synchronous up-counter

Waveform
Excitation table for three-bit synchronous down-counter

Present State Next State Flip-flop inputs

Q2 Q1 Q0 Q2 Q1 Q0 T2 T1 T0
1 1 1 1 1 0 0 0 1
1 1 0 1 0 1 0 1 1
1 0 1 1 0 0 0 0 1
1 0 0 0 1 1 1 1 1
0 1 1 0 1 0 0 0 1
0 1 0 0 0 1 0 1 1
0 0 1 0 0 0 0 0 1
0 0 0 1 1 1 1 1 1

Flip-flop input equations

(J-K)2 = T2 = Q1’ . Q0’ , (J-K)1 = T1 = Q0’ ,(J-K)0 = T0 =1

Three-bit synchronous down-counter

Waveform
Program

VHDL Code for three-bit synchronous up-counter

Library ieee;
Use ieee.std_logic_1164.all;

Entity upcounter is

Port (reset ,clock : in std_logic; q : out std_logic_vector(2 downto 0));

end upcounter;

architecture structural of upcounter is

component t_flipflop is

port (t, clock, reset : in std_logic; q, qbar : inout std_logic);

end component;

component logic_and is

port (a, b: in std_logic; z : out std_logic);

end component;

signal s1, s2, s3, s4, s5, s6, s7 : std_logic;

begin

c : t_flipflop port map ('1', clock, reset, s1, s2);

b : t_flipflop port map (s1, clock, reset ,s3, s4);

a : t_flipflop port map (s7, clock, reset , s5, s6);

g : logic_and port map ( s1, s3, s7 );

q (0) < = s1;

q (1) < = s3;

q (2) < = s5;

end structural;
- -submodule t-flipflop

Library ieee;

Use ieee.std_logic_1164.all;

entity t_flipflop is

port (t, clock, reset : in std_logic; q, qbar: inout std_logic);

end t_flipflop ;

architecture behavioral of t_flipflop is

begin

process (clock, reset)

begin

if reset = '1’ then

q < = '0';

elsif clock'event and clock='1' then

case t is

when ‘0’ = > q < = q;

when ‘1’ = > q < = not q;

when others = > q < = ‘-’ ;

end case;

end if;

end process;

qbar < = not q;

end behavioral;
- -submodule logic_and

library ieee;

use ieee.std_logic_1164.all;

entity logic_and is

port(a, b : in std_logic; z: out std_logic);

end logic_and;

architecture behavioral of logic_and is

begin

z < = a and b ;

end behavioral;
VHDL Code For 3-Bit Synchronous Down-Counter

Library ieee;
Use ieee.std_logic_1164.all;

Entity downcounter is

Port (reset ,clock : in std_logic; q : out std_logic_vector(2 downto 0));

end downcounter;

architecture structural of downcounter is

component t_flipflop is

port (t, clock, reset : in std_logic; q, qbar : inout std_logic);

end component;

component logic_and is

port (a, b: in std_logic; z : out std_logic);

end component;

signal s1, s2, s3, s4, s5, s6, s7 : std_logic;

begin

c : t_flipflop port map ('1', clock, reset, s1, s2);

b : t_flipflop port map (s2, clock, reset ,s3, s4);

a : t_flipflop port map (s7, clock, reset , s5, s6);

g : logic_and port map ( s2, s4, s7);

q (0) < = s1;

q (1) < = s3;

q (2) < = s5;

end structural;
- -submodule t_flipflop

Library ieee;

Use ieee.std_logic_1164.all;

entity t_flipflop is

port (t, clock, reset : in std_logic; q, qbar: inout std_logic);

end t_flipflop ;

architecture behavioral of t_flipflop is

begin

process (clock, reset)

begin

if reset = '1’ then

q < = '0';

elsif clock'event and clock='1' then

case t is

when ‘0’ = > q < = q;

when ‘1’ = > q < = not q;

when others = > q < = ‘-’;

end case;

end if;

end process;

qbar < = not q;

end behavioral;
- -submodule logic_and

library ieee;

use ieee.std_logic_1164.all;

entity logic_and is

port(a, b : in std_logic; z: out std_logic);

end logic_and;

architecture behavioral of logic_and is

begin

z <= a and b ;

end behavioral;

Result

The three-bit synchronous up and down binary counters are designed using VHDL and their
functionalities have been verified.
 8. Design of Scrambler and De-Scrambler

Aim

To design Scrambler and de-scrambler circuit using VHDL.

Apparatus required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

Scramblers are circuits that pseudo-randomly change the values of some bits in a data block with the
purpose of whitening (that is spread it so that no strong spectral component will exist, thus reducing
electromagnetic interference) or to introduce security. In addition to its use as a stream cipher, a scrambler is
commonly used to avoid long strings of 0’s and 1’s which are responsible for DC wander and synchronization
problems in communication circuits. Scramblers can be implemented using a linear feedback shift register
(LFSR). An LFSR is a simple register composed of memory elements (flip-flops) and modulo-2 adders (XOR
gates). Feedback is taken from two or more memory elements, which are XOR ed and feedback to the first stage
of the LFSR. There are two types of scramblers, additive scramblers and multiplicative scramblers. Additive
scramblers are also called synchronous (because they require the initial state of both scrambler and descrambler
to be same) or non-recursive (because they do not have feedback loops) transform the input data stream by
applying pseudo-random binary sequence. For synchronous operation transmitting and receiver LFSR, sync-
word must be used. Multiplicative scramblers are also called asynchronous (because they do not need LFSR
synchronization) or recursive (they have feedback loops) the input signal by scrambler’s transfer function. They
are discrete time-invariant systems. Multiplicative scramblers/descramblers are self- synchronizing, that they do
not need to start from the same initial state.

Procedure

1. A VHDL code for scrambler and descrambler are typed in the work space.
2. It is implemented in xilinxISE simulator and Simulated.
3. Signals are provided and Output Waveforms are viewed using test bench wave form.
 Scrambler

DATA OUT

D F/F D F/F D F/F D F/F D F/F D F/F D F/F

1 2 3 4 5 6 7

DATA IN

De-scrambler

DATA IN

D F/F D F/F D F/F D F/F D F/F D F/F D F/F

1 2 3 4 5 6 7

DATA OUT

MODULO 2 ADDER(XOR GATE)

Program

VHDL code for Scrambler

Library ieee;

Use ieee.std_logic_1164.all;

entity scrambler is

port (data_in, clock, reset: in std_logic; data_out : out std_logic);

end scrambler;

architecture structural of scrambler is

component d_flipflop is

port (d, clock, reset : in std_logic; q: out std_logic);

end component;

component logic_xor is

port (a, b: in std_logic; z: out std_logic);

end component;

signal Lfsr: std_logic_vector (7 downto 0);

signal s: std_logic;

begin

g: for i in 1 to 7 generate

f : d_flipflop port map (Lfsr(i-1), clock, reset, Lfsr(i));

end generate g;

g1: logic_xor port map (Lfsr(4), Lfsr(7), s);

g2: logic_xor port map (s, data_in, Lfsr(0));

process (clock)

begin

if (clock'event and clock = '1' ) then

data_out < = Lfsr(0);

end if;

end process;

end structural;

- -submodule d_flipflop

Library ieee;
Use ieee.std_logic_1164.all;

entity d_flipflop is
port (d, clock, reset : in std_logic; q: out std_logic);
end d_flipflop ;

architecture behavioral of d_flipflop is

begin
process (clock, reset)
begin
if reset = '1’ then
q < = '0';
elsif clock'event and clock='1' then
q< = d;
end if;
end process;
end behavioral;
- -submodule logic_xor

library ieee;

use ieee.std_logic_1164.all;

entity logic_xor is

port(a, b : in std_logic; z: out std_logic);

end logic_xor;

architecture behavioral of logic_xor is

begin

z <= a xor b ;

end behavioral;
VHDL code for de-scrambler

Library ieee;

Use ieee.std_logic_1164.all;

entity descrambler is

port (data_in, clock, reset: in std_logic; data_out : out std_logic);

end descrambler;

architecture structural of descrambler is

component d_flipflop is

port (d, clock, reset : in std_logic; q: out std_logic);

end component;

component logic_xor is

port (a, b: in std_logic; z: out std_logic);

end component;

signal Lfsr: std_logic_vector (7 downto 0);

signal s: std_logic;

begin

g: for i in 1 to 7 generate

f : d_flipflop port map (Lfsr(i-1), clock, reset, Lfsr(i));

end generate g;

g1: logic_xor port map (Lfsr(4), Lfsr(7), s);

g2: logic_xor port map (s, Lfsr(0), data_out);

process (clock)

begin

if (clock'event and clock = '1' ) then

Lfsr(0) < = data_in;

end if;

end process;

end structural;

- -submodule d_flipflop

Library ieee;
Use ieee.std_logic_1164.all;

entity d_flipflop is
port (d, clock, reset : in std_logic; q: out std_logic);
end d_flipflop ;

architecture behavioral of d_flipflop is

begin
process (clock, reset)
begin
if reset = '1’ then
q < = '0';
elsif clock'event and clock='1' then
q< = d;
end if;
end process;
end behavioral;
- -submodule logic_xor

library ieee;

use ieee.std_logic_1164.all;

entity logic_xor is

port(a, b : in std_logic; z: out std_logic);

end logic_xor;

architecture behavioral of logic_xor is

begin

z <= a xor b ;

end behavioral;

Result

The logic circuit for Scrambler and De-scrambler is designed using VHDL and its functionality has been
verified.
Additional Programs
 Design of HALF ADDER

Aim

To design a half adder using VHDL.

Apparatus Required:

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory:

A combinational circuit that performs the addition of two bits is called a half-adder. This circuit needs
two binary inputs and produces two binary outputs. One of the input variables designates the augend and other
designates the addend. The output variables produce the sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as below:

Sum S = a’b +ab’

Carry C = a.b

Where a and b are the two input variables.

Procedure:

1. The half-adder circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in ISE simulator and Simulated.
4. Signals are provided and Output Waveforms are viewed.
Truth Table:

HALF ADDER

INPUT OUTPUT

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Logic Diagram:

Waveform
VHDL code for Half adder

library ieee;

use ieee.std_logic_1164.all;

entity halfadder is

port (a,b: in std_logic; sum,carry : out std_logic);

end halfadder;

architecture behavioral of halfadder is

begin

sum <= a xor b;

carry <= a and b;

end behavioral;

Result

The Half Adder is designed in VHDL and the output is verified.

 Design of Fulladder

Aim

To design a full adder using VHDL.

Apparatus Required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

A combinational circuit that performs the addition of three bits is called a half-adder. This circuit needs
three binary inputs and produces two binary outputs. One of the input variables designates the augend and other
designates the addend. Mostly, the third input represents the carry from the previous lower significant position.
The output variables produce the sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as below:

Sum S = a + b + c

Carry C = a.b + a.c + b.c

Where a,b & c are the two input variables.

Procedure:

1. The full-adder circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in ISE Simulator and Simulated.
4. Signals are provided and Output Waveforms are viewed.

.
FULL ADDER

Truth table

INPUT OUTPUT

A B CIN SUM CARRY

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logic Diagram:

Waveform:
Program

VHDL code for full adder

library ieee;

use ieee.std_logic_1164.all;

entity fulladder is

port (a,b,c: in std_logic; sum,carry : out std_logic);

end fulladder;

architecture my_arch of fulladder is

begin

sum <= a xor b xor c;

carry<= (a and b) or (a and c) or (b and c);

end my_arch;

Result

The Full Adder is designed in VHDL and the output is verified.

 Design of Half subtractor

Aim

To design a half subtractor using VHDL.

Apparatus Required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

A half subtractor is a combinational circuit that subtracts two binary inputs and produces their
difference. It also has an output to specify if a 1 has been borrowed. The circuit has two inputs, one representing
the Minuend bit and the other Subtrahend bit. The circuit produces two outputs, the difference and borrow. The
Boolean functions for the tow outputs can be written as

Differnce = a’b + ab’

Borrow = a’b

Procedure

1. The half subtractor circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in ISE simulator and Simulated.
4. Signals are provided and Output Waveforms are viewed.
Truth Table:

HALF SUBTRACTOR

INPUT OUTPUT

A B Difference Borrow
D

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Logic Diagram:

Waveform:
Program:

Half Subtractor Design in VHDL

library ieee;

use ieee.std_logic_1164.all;

entity halfsub is

port (a,b: in std_logic; differnce,borrow : out std_logic);

end halfsub;

architecture halfsubarch of halfsub is

begin

differnce <=a xor b;

borrow <= ((not (a)) and b);

end halfsubarch;

Result

The Half Subtractor is designed in VHDL and the output is verified.

 Design of Full subtractor

Aim

To design a full subtractor using VHDL

Apparatus required

1. Simulation and synthesis tool: Xilinx ISE.

2. FPGA/CPLD Trainer kit.

Theory

A full subtractor is a combinational circuit that subtraction between two binary inputs, taking into
account that a 1 may have been borrowed by a lower significant sage. The circuit has three inputs, representing
the minuend bit, the Subtrahend bit and the previous borrow bit respectively. The two outputs, d and b represent
the difference and output borrows. The Boolean functions for the tow outputs can be written as

Differnce = a’bc + ab’c+ab’c’+abc.

Borrow = a’b+a’b+ab.

Procedure:

1. The full subtractor circuit is designed and the Boolean function is found out.
2. The VHDL program source code for the circuit is written.
3. It is implemented in ISE simulator and Simulated.
4. Signals are provided and Output Waveforms are viewed.
Truth Table:

FULL SUBTRACTOR

INPUT OUTPUT

A B CIN differnce Borrow

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Logic Diagram:

Waveform:
Program:

Full Subtractor Design in VHDL

library ieee;

use ieee.std_logic_1164.all;

entity fullsub is

port (a,b,c: in std_logic; differnce,borrow : out std_logic);

end fullsub;

architecture fulsubarch of fullsub is

begin

d <= a xor b xor c;

b <= ((not (a)) and b) or ( b and c) or ((not(a)) and c);

end fulsubarch;

Result

The Full Subtractor is designed in VHDL and the output is verified.

 Design Of ALU

Aim

To design the Arithmetic & Logic Unit in VHDL

Apparatus Required

1.Synthesis and simulation tool: Xilinx ISE.

2. FPGA trainer kit.

Theory

An Arithmetic logic unit is a logic circuit that performs various Boolean and arithmetic
operations on n-bit operands. In this design, ALU has 2 four-bit data inputs, A and B, a three-bit select input, S
and a four-bit output F.F is defined by various arithmetic or Boolean operations on the inputs A & B as shown
in the below table.

operation select Inputs(s2 s1 s0) Outputs F

Clear 000 0000

B–A 001 B–A

A–B 010 A–B

ADD 011 A+B

XOR 100 A XOR B

OR 101 A OR B

AND 110 A AND B

Preset 111 1111

ALU

Procedure:

1. The 4 bit Arithmetic logic unit is designed.

2. The VHDL program source code for the circuit is written.

3. It is implemented in ISE and Simulated.

4. Signals are provided and Output Waveforms are viewed.

Program

VHDL Coding

library ieee;

use ieee.std_logic_1164.all;

entity alu is

port(a,b : in std_logic_vector(3 downto 0);

s : in std_logic_vector(2 downto 0);

f : out std_logic_vector(3 downto 0));

end alu;

architecture arch_alu of alu is

begin

process(s,a,b)

begin

if (s = "0000") then

begin

f <= "0000";

else if (s == "001")then

f <= b - a;

else if (s == "010")then

f <= a - b;

else if (s == "011")then

f <= a + b;

else if (s == "100")then

f <= a xor b;

else if (s == "101")then
f <= a or b;

else if (s == "110")then

f <= a and b;

else if (s == "111")then

f <= "1111";

end if;

end if;

end;

end if;

end process;

end arch_alu;

Result:

The arithmetic logic unit is designed and simulated using VHDL.

 Design of Asynchronous Ripple Counter

Aim

To design an asynchronous ripple counter in VHDL.

Apparatus required

1.Synthesis and simulation tool: Xilinx ISE.

2. FPGA trainer kit.

Theory

In a ripple counter, the flip-flop output transition serves as a source for triggering other flip-
flops. In other words, the Clock Pulse inputs of all flip-flops (except the first) are triggered not by the incoming
pulses, but rather by the transition that occurs in other flip-flops. A binary ripple counter consists of a series
connection of complementing flip-flops (JK or T type), with the output of each flip-flop connected to the Clock
Pulse input of the next higher-order flip-flop. The flip-flop holding the LSB receives the incoming count pulses.
All J and K inputs are equal to 1. The small circle in the Clock Pulse /Count Pulse indicates that the flip-flop
complements during a negative-going transition or when the output to which it is connected goes from 1 to 0.
The flip-flops change one at a time in rapid succession, and the signal propagates through the counter in a ripple
fashion. A binary counter with reverse count is called a binary down-counter. In binary down-counter, the
binary count is decremented by 1 with every input count pulse.

Procedure:

1. The 4 bit asynchronous ripple counter circuit is designed.

2. The Verilog Module Source for the circuit is written.

3. It is implemented xilinxISE simulator and Simulated.

4. Signals are provided and Output Waveforms are viewed.

4 bit Asynchronous Ripple Counter

Program

VHDL code for Aynchronous up counter

library ieee;

use ieee.std_logic_1164.all;

entity asyncbinripcount is

port (clk,clr : in std_logic; q,qbar : inout std_logic_vector (0 to 3));

end asyncbinripcount;

architecture asyncbinripcountarch of asyncbinripcount is

component jkflipflop

port (j,k,clk,clr : in std_logic; q,qbar : inout std_logic);

end component;

signal high: std_logic :='1';

begin
a1 : jkflipflop port map (high,high,clk,clr,q(0),qbar(0));

a2 : jkflipflop port map (high,high,q(0),clr,q(1),qbar(1));

a3 : jkflipflop port map (high,high,q(1),clr,q(2),qbar(2));

a4 : jkflipflop port map (high,high,q(2),clr,q(3),qbar(3));

end asyncbinripcountarch;

--submodule jkflipflop

library ieee;

use ieee.std_logic_1164.all;

entity jkflipflop is

port (j,k,clk,clr : in std_logic; q,qbar : inout std_logic);

end jkflipflop;

architecture behavioral of jkflipflop is

begin

process (clr,clk)

begin

if (clr = '1') then

if (falling_edge (clk)) then

if (j = '0' and k = '0') then

q <= q ;

qbar <= qbar ;

elsif (j = '1' and k ='0') then

q <= '1' ;

qbar <= '0' ;

elsif (j = '0' and k = '1') then

q <= '0' ;

qbar <= '1';

elsif (j ='1' and k ='1') then

 q <= not(q) ;

qbar <= not (qbar) ;

end if;

end if;

elsif (clr = '0') then

q <= '0';

qbar <= '1';

end if;

end process;

end behavioral;

Result:

The asynchronous ripple counter is designed in VHDL and the output is verified.