19-2531; Rev 2; 12/05

Low-Power Dual-/Triple-Voltage SC70 µP

Supervisory Circuits
General Description Features

MAX6736–MAX6745
The MAX6736–MAX6745 are low-power dual-/triple- ♦ Dual-/Triple-Supply Reset Voltage Monitors
voltage microprocessor (µP) supervisors. These ♦ Precision Factory-Set Reset Thresholds for
devices assert a reset if any monitored supply falls Monitoring from 0.9V to 5.0V
below its factory-trimmed or adjustable threshold and
maintain reset for a minimum timeout period after all ♦ Adjustable Reset Input Down to 0.488V
supplies rise above their thresholds. The integrated ♦ 150ms and 1200ms (min) Reset Timeout Period
dual/triple supervisory circuits significantly reduce size Options
and power compared to separate ICs or discrete com- ♦ VCC1 Power-OK Output for Power-Supply
ponents. The low supply current of 6µA makes these Sequencing Applications (MAX6741/MAX6744)
devices ideal for portable equipment.
♦ Power-Fail Input/Power-Fail Output
The MAX6736/MAX6737 are dual fixed-voltage µP (MAX6742/MAX6745)
supervisors with a manual reset input. The MAX6738/
MAX6739 have one fixed and one adjustable reset ♦ 6µA Supply Current
threshold and a manual reset input. The MAX6740/ ♦ Tiny SC70 Package
MAX6743 are triple-voltage µP supervisors with two
fixed and one user-adjustable reset threshold inputs. Ordering Information
The MAX6741/MAX6744 are dual-voltage µP supervi-
sors with a power-OK (POK) output ideal for power- PART TEMP RANGE PIN-PACKAGE
supply sequencing. The MAX6742/MAX6745 monitor MAX6736XK_ _D_-T -40°C to +85°C 5 SC70-5
the primary V CC supply and have an independent MAX6737XK_ _D_-T -40°C to +85°C 5 SC70-5
power-fail comparator. Note: The first “_ _” or “_” are placeholders for the threshold
The MAX6736–MAX6745 monitor I/O supply voltages voltage levels of the devices. Desired threshold levels are set
(V CC1) from 1.8V to 5.0V and core supply voltages by the part number suffix found in Tables 1 and 2. The “_” after
(VCC2) from 0.9V to 3.3V with factory-trimmed reset the D is a placeholder for the reset timeout period suffix found
threshold voltage options (Table 1). An external in Table 3. For example, the MAX6736XKLTD3-T is a dual-volt-
age supervisor VTH1 = 4.625V, VTH2 = 3.075V, and a 150ms
adjustable RSTIN input option allows monitoring volt- minimum reset timeout period. All devices are available in
ages down to 0.5V. tape-and-reel only. There is a 2500-piece minimum order
A variety of push-pull or open-drain reset outputs along increment for standard versions (see Table 1). Sample stock is
with manual reset input and power-fail input/output fea- typically held on standard versions only. Nonstandard versions
tures are available (see the Selector Guide). The require a minimum order increment of 10,000 pieces. Contact
factory for availability.
MAX6736–MAX6745 are offered in a space-saving 5-pin
Devices are available in both leaded and lead-free packaging.
SC70 package and operate over the -40°C to +85°C
Specify lead-free by replacing “-T” with “+T” when ordering.
temperature range.
Ordering Information and Selector Guide continued at end
Applications of data sheet.
Portable/Battery- Controllers Pin Configurations, Typical Application Circuits, and
Powered Equipment PDAs Functional Diagram appear at end of data sheet.
Multivoltage Systems GPS Equipment
Notebook Computers POS Equipment
Selector Guide
POWER-FAIL
VOLTAGE OPEN-DRAIN PUSH-PULL MANUAL POK RSTIN
PART INPUT/
MONITORS RESET RESET RESET OUTPUT INPUT
OUTPUT
MAX6736 2 fixed X — X — — —
MAX6737 2 fixed — X X — — —
MAX6738 1 fixed, 1 adj X — X — — X
*Manual reset detect on RESET output.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
ABSOLUTE MAXIMUM RATINGS
MAX6736–MAX6745

VCC1, VCC2, POK1 to GND ......................................-0.3V to +6V Operating Temperature Range ...........................-40°C to +85°C
Open-Drain RESET, PFO to GND.............................-0.3V to +6V Junction Temperature ......................................................+150°C
Push-Pull RESET to GND..........................-0.3V to (VCC1 + 0.3V) Storage Temperature Range .............................-65°C to +150°C
MR, RSTIN, PFI to GND............................-0.3V to (VCC1 + 0.3V) Lead Temperature (soldering, 10s) .................................+300°C
Input/Output Current, All Pins .............................................20mA
Continuous Power Dissipation (TA = +70°C)
5-Pin SC70 (derate 3.1mW/°C above +70°C) ..............247mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC1, TA = -40°C to 0°C 1.2 5.5
Operating Voltage Range V
VCC2 TA = 0°C to +85°C 1.0 5.5
VCC1 = 3.3V, VCC1 > VCC2, no load, reset
5 10
not asserted
VCC1 Supply Current ICC1 µA
VCC1 = 1.8V, VCC1 < VCC2, no load, reset
5 10
not asserted
VCC2 = 1.8V, VCC2 < VCC1, no load, reset
1 2
not asserted
VCC2 Supply Current ICC2 µA
VCC2 = 3.3V, VCC2 > VCC1, no load, reset
10 20
not asserted
TA = 0°C to +85°C 4.500 4.625 4.750
MAX67_ _L
TA = -40°C to +85°C 4.425 4.825
TA = 0°C to +85°C 4.250 4.375 4.500
MAX67_ _M
TA = -40°C to +85°C 4.175 4.575
TA = 0°C to +85°C 3.000 3.075 3.150
MAX67_ _T
TA = -40°C to +85°C 2.950 3.200
TA = 0°C to +85°C 2.850 2.925 3.000
MAX67_ _S
TA = -40°C to +85°C 2.800 3.050
TA = 0°C to +85°C 2.550 2.625 2.700
Reset Threshold for VCC1 VTH1 MAX67_ _R V
TA = -40°C to +85°C 2.505 2.745
TA = 0°C to +85°C 2.250 2.313 2.375
MAX67_ _Z
TA = -40°C to +85°C 2.213 2.413
TA = 0°C to +85°C 2.125 2.188 2.250
MAX67_ _Y
TA = -40°C to +85°C 2.088 2.288
TA = 0°C to +85°C 1.620 1.665 1.710
MAX67_ _W
TA = -40°C to +85°C 1.593 1.737
TA = 0°C to +85°C 1.530 1.575 1.620
MAX67_ _V
TA = -40°C to +85°C 1.503 1.647

2 _______________________________________________________________________________________
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)

MAX6736–MAX6745
(VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TA = 0°C to +85°C 3.000 3.075 3.150
MAX67_ _T
TA = -40°C to +85°C 2.905 3.050
TA = 0°C to +85°C 2.850 2.925 3.000
MAX67_ _S
TA = -40°C to +85°C 2.800 3.050
TA = 0°C to +85°C 2.550 2.625 2.700
MAX67_ _R
TA = -40°C to +85°C 2.505 2.745
TA = 0°C to +85°C 2.250 2.313 2.375
MAX67_ _Z
TA = -40°C to +85°C 2.213 2.413
TA = 0°C to +85°C 2.125 2.188 2.250
MAX67_ _Y
TA = -40°C to +85°C 2.088 2.288
TA = 0°C to +85°C 1.620 1.665 1.710
MAX67_ _W
TA = -40°C to +85°C 1.593 1.737
TA = 0°C to +85°C 1.530 1.575 1.620
Reset Threshold for VCC2 VTH2 MAX67_ _V V
TA = -40°C to +85°C 1.503 1.647
TA = 0°C to +85°C 1.350 1.388 1.425
MAX67_ _I
TA = -40°C to +85°C 1.328 1.448
TA = 0°C to +85°C 1.275 1.313 1.350
MAX67_ _H
TA = -40°C to +85°C 1.253 1.373
TA = 0°C to +85°C 1.080 1.110 1.140
MAX67_ _G
TA = -40°C to +85°C 1.062 1.158
TA = 0°C to +85°C 1.020 1.050 1.080
MAX67_ _F
TA = -40°C to +85°C 1.002 1.098
TA = 0°C to +85°C 0.810 0.833 0.855
MAX67_ _E
TA = -40°C to +85°C 0.797 0.869
TA = 0°C to + 85°C 0.765 0.788 0.810
MAX67_ _D
TA = -40°C to +85°C 0.752 0.824
RSTIN Threshold (MAX6738/ TA = 0°C to +85°C 0.476 0.488 0.500
VTH-RSTIN V
MAX6739/MAX6740/MAX6743) TA = -40°C to +85°C 0.468 0.507
RSTIN Input Current VRSTIN ≥ 0.1V (Note 2) -10 +10 nA
Reset Threshold Hysteresis VTH1, VTH2, RSTIN, PFI 0.5 %
VCC1 ≥ 1.0V, ISINK = 50µA, TA = 0°C to
0.3
+85°C
RESET, POK1 Output Low VOL VCC1 ≥ 1.2V, ISINK = 100µA 0.3 V
VCC1 ≥ 2.13V, ISINK = 1.2mA 0.3
VCC1 ≥ 4.25V, ISINK = 3.2mA, 0.4
VCC1 ≥ 2.38V, ISOURCE = 500µA, output 0.8 ×
deasserted VCC
RESET Output High (Push-Pull) VOH V
VCC1 ≥ 4.75V, ISOURCE = 800µA, output 0.8 ×
deasserted VCC

_______________________________________________________________________________________ 3
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
MAX6736–MAX6745

(VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

RESET Output Open-Drain
Leakage Current ILKG Output not asserted low (Note 2) 500 nA
(MAX6736/MAX6738)

POK1 Output Open-Drain

Output not asserted low (Note 2) 500 nA
Leakage
VCC1, VCC2, or RSTIN falling at 10mV/µs
VCC Reset Delay tRD 35 µs
from VTH + 100mV to VTH - 100mV
VCC Reset Timeout Period MAX67_ _ _ _ XK_ _D3 150 225 300
tRP ms
(Note 3) MAX67_ _ _ _ XK_ _ D7 1200 1800 2400
MANUAL RESET (MAX6736–MAX6739 only)
MR to VCC1 Internal Pullup
0.75 1.5 3.00 kΩ
Impedance
MR Timeout Period tMRP Both D3 and D7 timing options 150 225 300 ms
MR Minimum Input Pulse Width tMPW 1 µs
MR Glitch Rejection 100 ns
0.3 ×
VIL
VCC1
MR Input Voltage V
0.8 ×
VIH
VCC1
MR to RESET Delay 300 ns
VCC1 POWER-OK OUTPUT (MAX6741/MAX6744 only)
POK1 Timeout Period tPOKP 37.5 56.25 75.0 ms
PUSHBUTTON RESET (MAX6740/MAX6741/MAX6742 only)
RESET to VCC1 Internal Pullup
25 50 100 kΩ
Impedance
Manual Reset Detect Debounce
tDEB (Note 4) 37.5 56.25 75.0 ms
Period
Manual Reset Timeout MAX67_ _ _ _ XK_ _D3 150 225 300
tMRP ms
Period (Note 3) MAX67_ _ _ _ XK_ _ D7 1200 1800 2400
Manual Reset Minimum Input
tMPW (Note 4) 1 µs
Pulse Width
Manual Reset Release Detect 0.5 ×
(Note 4) V
Threshold VCC1
Manual Reset Glitch Rejection (Note 4) 100 ns
Manual Reset to RESET Delay 300 ns

4 _______________________________________________________________________________________
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)

MAX6736–MAX6745
(VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER-FAIL COMPARATOR (MAX6742/MAX6745 only)
TA = 0°C to +85°C 0.476 0.488 0.500
Power Fail In Threshold (Note 5) VTH-PFI V
TA = -40°C to +85°C 0.468 0.507
Power Fail In Current IPFI VPFI ≥ 0.1V (Note 2) -10 +10 nA
VCC1 ≥ 1.53V, ISINK = 500µA 0.3
PFO Output Low VOL VCC1 ≥ 2.03V, ISINK = 1.2mA 0.3 V
VCC1 ≥ 4.25V, ISINK = 3.2mA 0.4
PFI falling at 10mV/µs from VTH-PFI +
100mV to VTH-PFI - 100mV or rising at
PFI to PFO Propagation Delay tP 35 µs
10mV/µs from VTH-PFI - 100mV to VTH-PFI +
100mV (Note 5)
PFO Startup Delay To output valid (Note 5) 5 ms
Note 1: All devices are 100% tested at TA = +25°C. All temperature limits are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: tRD timeout period begins after POK1 timeout period (tPOKP) and VCC2 ≥ VTH2 (max) (MAX6741/MAX6744).
Note 4: Refers to the manual reset function obtained by forcing the RESET output low.
Note 5: VCC1 ≥ 1.6V.

Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE
10 10 10
MAX6736-45 toc01

MAX6736-45 toc02

MAX6736-45 toc03
VCC1 = 3.3V, VCC2 = 2.5V VCC1 = 2.5V, VCC2 = 1.8V VCC1 = 1.8V, VCC2 = 1.2V
9 9 9
8 8 8
SUPPLY CURRENT (µA)

SUPPLY CURRENT (µA)

SUPPLY CURRENT (µA)

7 7 7
TOTAL
6 6 TOTAL 6
ICC1 TOTAL
5 5 5
ICC1
4 4 4
3 3 3 ICC1

2 ICC2 2 2
ICC2 ICC2
1 1 1
0 0 0
-40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

_______________________________________________________________________________________ 5
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
Typical Operating Characteristics (continued)
MAX6736–MAX6745

(TA = +25°C, unless otherwise noted.)

NORMALIZED VCC/POK1/MR MAXIMUM VCC1/VCC2 TRANSIENT DURATION

TIMEOUT PERIOD vs. TEMPERATURE vs. RESET THRESHOLD OVERDRIVE

MAXIMUM VCC1/VCC2 TRANSIENT DURATION (µs)

10,000

MAX6736-45 toc05
MAX6736-45 toc04
1.019
NORMALIZED VCC/POK1/MR RESET

1.014 VCC1
1000
1.009
TIMEOUT PERIOD

RESET OCCURS ABOVE

THESE LINES
1.004
100
0.999

0.994 VCC2
10

0.989

0.984 0
-40 -20 0 20 40 60 80 10 100 1000
TEMPERATURE (°C) RESET THRESHOLD OVERDRIVE (mV)

NORMALIZED VCC RESET THRESHOLD VCC TO RESET OUTPUT DELAY

vs. TEMPERATURE vs. TEMPERATURE
1.008
MAX6736-45 toc06

MAX6736-45 toc07
100mV OVERDRIVE
48.5
NORMALIZED VCC RESET THRESHOLD

VCC TO RESET OUTPUT DELAY (µs)

1.003
43.5

0.998
38.5

0.993 33.5

NORMALIZED TO +25°C
0.988 28.5
-40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80
TEMPERATURE (°C) TEMPERATURE (°C)

RESET INPUT TO RESET OUTPUT DELAY POWER-FAIL INPUT TO POWER-FAIL

vs. TEMPERATURE OUTPUT DELAY vs. TEMPERATURE
35
MAX6736-45 toc09
MAX6736-45 toc08

100mV OVERDRIVE 49 100mV OVERDRIVE

RSTIN TO RESET OUTPUT DELAY (µs)

44
PFI TO PFO DELAY (µs)

RISING EDGE
30
39

34
25

29 FALLING EDGE

20 24
-40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80
TEMPERATURE (°C) TEMPERATURE (°C)

6 _______________________________________________________________________________________
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
Typical Operating Characteristics (continued)

MAX6736–MAX6745
(TA = +25°C, unless otherwise noted.)

POWER-FAIL INPUT TO
MR TO RESET OUTPUT DELAY POWER-FAIL OUTPUT DELAY
MAX6736-45 toc10 MAX6736-45 toc11

PFI
VMR 200mV/div
2V/div

PFO
VRESET 2V/div
2V/div

100ns/div 10µs/div

OUTPUT LOW VOLTAGE

VCC TO RESET OUTPUT DELAY vs. SINK CURRENT
MAX6736-45 toc12
500

MAX6736-45 toc13
VCC = 3.3V

400
OUTPUT LOW VOLTAGE (mV)

VCC
200mV/div
AC-COUPLED
300

200

VRESET
2V/div 100

0
4µs/div 0 1 2 3 4 5 6 7 8 9 10
SINK CURRENT (mA)

OUTPUT HIGH VOLTAGE

vs. SOURCE CURRENT
4
MAX6736-45 toc14

VCC = 3.3V
OUTPUT HIGH VOLTAGE (V)

0
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
SOURCING CURRENT (mA)

_______________________________________________________________________________________ 7
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
Pin Description
MAX6736–MAX6745

PIN
MAX6736 MAX6738 MAX6740 MAX6741 MAX6742 NAME FUNCTION
MAX6737 MAX6739 MAX6743 MAX6744 MAX6745
Reset Output, Push-Pull or Open Drain Active Low. RESET
changes from high to low when any monitored power-supply
input (VCC1, VCC2, RSTIN) drops below its selected reset
threshold. It remains low until all monitored power-supply
inputs exceed their selected reset thresholds for the VCC
reset timeout period. RESET is forced low if MR is low for at
1 1 1 1 1 RESET least the MR minimum input pulse width. It remains low for
the MR reset timeout period after MR goes high. The push-
pull output is referenced to VCC1. The MAX6736/MAX6738
open-drain outputs require an external pullup resistor. The
MAX6740/MAX6741/MAX6742 open-drain outputs have an
internal 50kΩ pullup resistor to VCC1 and provide a manual
reset function.
2 2 2 2 2 GND Ground
Manual Reset, Active Low. Pull low for at least MR minimum
input pulse width to force RESET low. Reset remains active
3 3 — — — MR as long as MR is low and for the MR reset timeout period
after MR goes high. There is an internal 1.5kΩ pullup resistor
to VCC1.
Voltage Input 1. Power supply and input for the secondary
4 — 4 4 — VCC2
µP voltage reset monitor.

Adjustable Reset Threshold Input. RESET is asserted when

RSTIN is below the internal 0.488V reference level. Set the
— 4 3 — — RSTIN
adjustable reset threshold with an external resistor-divider
network. Connect RSTIN to VCC1 if unused.

Voltage Input 2. Power supply and input for the primary µP

5 5 5 5 5 VCC1
voltage reset monitor.
Power-Fail Comparator Input. PFO is asserted when PFI is
below 0.488V. PFO is deasserted without any reset timeout
— — — — 4 PFI period when PFI goes above 0.488V. Connect PFI to an
external resistor network to set the desired monitor
threshold.
Power-Fail Comparator Output, Open Drain Active Low. PFO
— — — — 3 PFO
is asserted when PFI is below 0.488V.
VCC1 Power-OK Output, Open Drain Active High. POK1
remains low as long as VCC1 is below VTH1. POK1 output
goes high after VCC1 exceeds VTH1 for the POK1 timeout
— — — 3 — POK1
period. POK1 logic is independent of the MR or VCC2 inputs.
The output can be used to control VCC1-to-VCC2 supply
sequencing.

8 _______________________________________________________________________________________
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits

MAX6736–MAX6745
Table 1. Reset Voltage Threshold Suffix Guide for MAX6736/MAX6737/MAX6740/
MAX6741/MAX6743/MAX6744
PART NO. VCC1 NOMINAL VCC2 NOMINAL PART NO. VCC1 NOMINAL VCC2 NOMINAL
SUFFIX VOLTAGE VOLTAGE SUFFIX VOLTAGE VOLTAGE
(__) THRESHOLD (V) THRESHOLD (V) (__) THRESHOLD (V) THRESHOLD (V)
LT 4.625 3.075 RD 2.625 0.788
MS 4.375 2.925 ZW 2.313 1.665
MR 4.375 2.625 ZI 2.313 1.388
TZ 3.075 2.313 ZG 2.313 1.110
TW 3.075 1.665 ZE 2.313 0.833
TI 3.075 1.388 YV 2.188 1.575
TG 3.075 1.110 YH 2.188 1.313
TE 3.075 0.833 YF 2.188 1.050
SY 2.925 2.188 YD 2.188 0.788
SV 2.925 1.575 WT 1.665 3.075
SH 2.925 1.313 WI 1.665 1.388
SF 2.925 1.050 WG 1.665 1.110
SD 2.925 0.788 WE 1.665 0.833
RY 2.625 2.188 VR 1.575 2.625
RV 2.625 1.575 VH 1.575 1.313
RH 2.625 1.313 VF 1.575 1.050
RF 2.625 1.050 VD 1.575 0.788
Note: Standard versions, shown in bold, are available in the D3 timeout option only. Samples are typically held on standard versions
only. There is a 10,000-piece order increment on nonstandard versions. Other threshold voltage combinations may be available;
contact factory for availability.

Table 2. Reset Voltage Threshold Suffix

Guide for MAX6738/MAX6739/MAX6742/ Table 3. VCC Timeout Period Suffix
MAX6745 Guide
PART NO. VCC1 NOMINAL TIMEOUT ACTIVE TIMEOUT PERIOD
SUFFIX VOLTAGE PERIOD
(_) THRESHOLD (V) SUFFIX MIN (ms) MAX (ms)
D3 150 300
L 4.625
D7 1200 2400
M 4.375
T 3.075
S 2.925
R 2.625
Z 2.313
Y 2.188
W 1.665
V 1.575
Note: Standard versions, shown in bold, are available in the
D3 timeout option only. Samples are typically held on standard
versions only. There is a 10,000-piece order increment on non-
standard versions. Other threshold voltages may be avail-
able; contact factory for availability.

_______________________________________________________________________________________ 9
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
MAX6736–MAX6745

VCC1
VTH1

GND

POK1
tPOKP

GND

VCC2
VTH2

GND

SWITCH SWITCH
BOUNCE BOUNCE
MR

GND

RESET
tRP

GND
tMRP

Figure 1. Timing Diagram

Detailed Description Reset Output

The MAX6736–MAX6745 provide an active-low reset out-
Supply Voltages put (RESET). RESET is asserted when the voltage at
The MAX6736–MAX6745 µP supervisory circuits main- either VCC1 or VCC2 falls below the voltage threshold
tain system integrity by alerting the µP to fault condi- level, RSTIN drops below the threshold, or MR is pulled
tions. These devices are optimized for systems that low. Once reset is asserted, it stays low for the reset time-
monitor two or three supply voltages. The reset output out period. If VCC1, VCC2, or RSTIN goes below the reset
state is guaranteed to remain valid while either VCC1 or threshold before the reset timeout period is completed,
VCC2 is above 1.2V. the internal timer restarts. The MAX6736/MAX6738/
Threshold Levels MAX6740/MAX6741/MAX6742 have open-drain reset out-
The MAX6736/MAX6737/MAX6740/MAX6741/MAX6743/ puts, while the MAX6737/MAX6739/MAX6743/MAX6744/
MAX6744 input voltage threshold combinations are indi- MAX6745 have push-pull reset outputs (Figure 1).
cated by a two-letter code in Table 1. The MAX6738/ The MAX6740/MAX6741/MAX6742 include a RESET
MAX6739/MAX6742/MAX6745 input voltage thresholds output with a manual reset detect function. The open-
are indicated by a one-letter code in Table 2. Contact the drain RESET output has an internal 50kΩ pullup to
factory for the availability of other voltage thresholds. V CC 1. The RESET output is low while the output is
pulled to GND and remains low for at least the manual
reset timeout period after the external GND pulldown is

10 ______________________________________________________________________________________
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits

MAX6736–MAX6745
SWITCH SWITCH SWITCH SWITCH
BOUNCE BOUNCE BOUNCE BOUNCE
OPEN

PUSHBUTTON
SWITCH

CLOSED

VCC1
tDEB tMRP tDEB tMRP
RESET

GND

Figure 2. MAX6740/MAX6741/MAX6742 Manual Reset Timing Diagram

released. The manual reset detect function is internally cally 488mV. Connect a resistor-divider network to the
debounced for the tDEB timeout period, so the output circuit as shown in Figure 3 to establish an externally
can be connected directly to a momentary pushbutton controlled threshold voltage, VEXT_TH.
switch, if desired (Figure 2). VEXT_TH = 0.488V((R1 + R2) / R2)
Manual Reset Input Low leakage current at RSTIN allows the use of large-
Many microprocessor-based products require manual valued resistors, resulting in reduced power consump-
reset capability, allowing the operator, a test techni- tion of the system.
cian, or external logic circuitry to initiate a reset while
the monitored supplies remain above their reset thresh- Power-Fail Comparator
olds. The MAX6736–MAX6739 have a dedicated PFI is the noninverting input to an auxiliary comparator. A
active-low MR input. The RESET is asserted low while 488mV internal reference (VTH-PFI) is connected to the
MR is held low and remains asserted for the manual inverting input of the comparator. If PFI is less than
reset timeout period after MR returns high. The MR 488mV, PFO is asserted low. PFO deasserts without a
input has an internal 1.5kΩ pullup resistor to VCC1 and timeout period when PFI rises above the externally set
can be left unconnected if not used. MR can be driven threshold. Common uses for the power-fail comparator
with CMOS logic levels, open-drain/open-collector out- include monitoring for low battery conditions or a failing
puts, or a momentary pushbutton switch to GND to cre- DC-DC converter input voltage (see the Typical
ate a manual reset function. Application Circuits). The asserted PFO output can place
a system in a low-power suspend mode or support an
Adjustable Input Voltage orderly system shutdown before monitored VCC voltages
The MAX6738/MAX6739 and MAX6740/MAX6743 pro- drop below the reset thresholds. Connect PFI to an exter-
vide an additional input to monitor a second or third nal resistor-divider network as shown in Figure 4 to set
system voltage. The threshold voltage at RSTIN is typi- the desired trip threshold. Connect PFI to VCC1 if unused.
Applications Information
Interfacing to the µP with
VEXT_TH Bidirectional Reset Pins
MAX6738
Most microprocessors with bidirectional reset pins can
MAX6739
R1
MAX6740
interface directly to open-drain RESET output options.
MAX6743 Systems simultaneously requiring a push-pull RESET
RSTIN output and a bidirectional reset interface can be in
logic contention. To prevent contention, connect a
R2
4.7kΩ resistor between RESET and the µP’s reset I/O
port as shown in Figure 5.
GND

Figure 3. Monitoring an Additional Voltage

______________________________________________________________________________________ 11
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
shown in Figure 6. Select the values of R1, R2, and R3
MAX6736–MAX6745

A) VIN IS POSITIVE such that PFI sees VTH-PFI (488mV) when VEXT falls to
its power-fail trip point (VFAIL) and when VEXT rises to
its power-good trip point (VGOOD). The hysteresis win-
VEXT_TH MAX6742 dow extends between the specified VFAIL and VGOOD
R1
MAX6745 VEXT_TH = VTH-PFI ( R1 + R2
R2 ) thresholds. R3 adds the additional hysteresis by sink-
ing current from the R1/R2 divider network when the
PFI PFO
PFO output is logic low and sourcing current into the
R2 network when PFO is logic high. R3 is typically an order
of magnitude greater than R1 or R2.
GND
The current through R2 should be at least 1µA to ensure
that the 10nA (max) PFI input current does not significant-
ly shift the trip points. Therefore, for most applications:
R2 < VTH-PFI / 1mA < 0.488V / 1mA < 488kΩ
B) VIN IS NEGATIVE PFO is an open-drain output requiring an external
pullup resistor, R4. Select R4 to be less than 1% of R3.
VCC
MAX6742
VEXT_TH = R2 (
(VTH-PFI)
)( 1 + 1
R1 R2) V
- CC
R1 VGOOD = DESIRED VEXT GOOD VOLTAGE THRESHOLD
MAX6745 VPFI = 488mV
R1 VFAIL = DESIRED VEXT FAIL VOLTAGE THRESHOLD
PFI PFO
VPU = VPULLUP (FOR OPEN-DRAIN PFO)
R2
R2 = 488kΩ (FOR >1µA R2 CURRENT)

(VTH- PFI (VGOOD - VFAIL )

VEXT_TH GND

(VGOOD - VTH−PFI ) − VPU

Figure 4. Using Power-Fail Input to Monitor an Additional R1 = R2
VTH - PFI
Power Supply

Adding Hysteresis to the R3 = (R1 x VPU) / (VGOOD - VFAIL)

Power-Fail Comparator R4 ≤ 0.01 x R3
The power-fail comparator has a typical input hystere-
sis of 2.5mV. This is sufficient for most applications in Power Sequencing Applications
which a power-supply line is being monitored through Many dual-voltage processors/ASICs require specific
an external voltage-divider. If additional noise margin is power-up/power-down sequences for the I/O and core
desired, connect a resistor between PFO and PFI, as supplies.

R3 VPULLUP
VCC1 VCC2 RESET TO OTHER SYSTEM COMPONENTS

VGOOD
VIN VFAIL

MAX6737 PFO
VEXT MAX6742
MAX6739 MAX6745
MAX6743 µP R1 R4
4.7kΩ
VCC2 MAX6744 RESET RESET
MAX6745 PFI PFO
VCC1 VGOOD = DESIRED VEXT GOOD VOLTAGE THRESHOLD
R2 VFAIL = DESIRED VEXT FAIL VOLTAGE THRESHOLD
VOH = VCC1 (FOR PUSH-PULL PFO)
R2 = 200kΩ (FOR > 2.5µA R2 CURRENT)
R1 = R2 ((VGOOD - VTH-PFI) - (VTH-PFI)(VGOOD - VFAIL) / VPU) / VTH-PFI
GND GND GND R3 = (R1 x VOH) / (VGOOD - VFAIL)

Figure 5. Interfacing to µPs with Bidirectional Reset I/O Figure 6. Adding Hysteresis to Power Fail for Push-Pull PFO

12 ______________________________________________________________________________________
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
The MAX6741/MAX6744 offer a VCC1 POK (POK1) ideal Transient Immunity

MAX6736–MAX6745
for VCC1-to-VCC2 sequencing. POK1 remains low as The MAX6736–MAX6745 supervisors are relatively
long as VCC1 is below its VTH1 threshold. When VCC1 immune to short-duration falling VCC transients (glitch-
exceeds VTH1 for the POK1 timeout period (tPOKP), the es). It is usually undesirable to reset the µP when VCC
open-drain POK1 output is deasserted. The POK1 output experiences only small glitches. The Typical Operating
can then enable the VCC2 power supply (use an external Characteristics show Maximum VCC1/VCC2 Transient
POK1 pullup resistor). RESET is deasserted when both Duration vs. Reset Threshold Overdrive, for which reset
VCC1 and VCC2 remain above their selected thresholds pulses are not generated. The graph shows the maxi-
for the reset timeout period (tRP). The POK1 output can mum pulse width that a falling VCC transient might typi-
be used for I/O before core or core before I/O sequenc- cally have without causing a reset pulse to be issued.
ing, depending on the selected VCC1/VCC2 thresholds. As the amplitude of the transient increases, the maxi-
See the Typical Application Circuit and Figure 1. mum allowable pulse width decreases. A 0.1µF bypass
capacitor mounted close to the VCC pin provides addi-
Monitoring a Negative Voltage
tional transient immunity.
The power-fail comparator can be used to monitor a
negative supply voltage using the circuit shown in
Figure 4. When the negative supply is valid, PFO is low.
When the negative supply voltage drops, PFO goes
Chip Information
high. The circuit’s accuracy is affected by the PFI TRANSISTOR COUNT: 249
threshold tolerance, VCC, R1, and R2. PROCESS: BiCMOS

Functional Diagram

VCC1

MAX6736–
MAX6745

PFO
DELAY POK1

VCC1 VCC2

RSTIN/PFI RESET RESET

TIMEOUT OUTPUT
PERIOD
RESET

VCC2

VCC1

MR
PULLUP

VCC1
0.488V
1.23V

MR

______________________________________________________________________________________ 13
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
Selector Guide (continued)
MAX6736–MAX6745

POWER-FAIL
VOLTAGE OPEN-DRAIN PUSH-PULL MANUAL POK RSTIN
PART INPUT/
MONITORS RESET RESET RESET OUTPUT INPUT
OUTPUT
MAX6739 1 fixed, 1 adj — X X — — X
MAX6740 2 fixed, 1 adj X* — X* — — X
MAX6741 2 fixed X* — X* — X —
MAX6742 1 fixed X* — X* X — —
MAX6743 2 fixed, 1adj — X — — — X
MAX6744 2 fixed — X — — X —
MAX6745 1 fixed — X — X — —
*Manual reset detect on RESET output.

Typical Application Circuits

DC/DC
CONVERTER
UNREGULATED IN OUT
DC VBATT IN OUT
DC/DC
CONVERTER
IN OUT
DC/DC
CONVERTER VCC
VCC1
SHDN PFO

VCC2 VCC1 CORE I/O MAX6742 µP

SUPPLY SUPPLY
PFI RESET RESET
µP
MAX6741 GND GND

POK1 RESET RESET GND

GND PUSHBUTTON
SWITCH

PUSHBUTTON
SWITCH

14 ______________________________________________________________________________________
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
Pin Configurations

MAX6736–MAX6745
TOP VIEW

RESET 1 5 VCC1 RESET 1 5 VCC1 RESET 1 5 VCC1

MAX6736 MAX6738 MAX6740

GND 2 GND 2 MAX6739 GND 2 MAX6743
MAX6737

MR 3 4 VCC2 MR 3 4 RSTIN RSTIN 3 4 VCC2

SC70 SC70 SC70

RESET 1 5 VCC1 RESET 1 5 VCC1

MAX6741 MAX6742
GND 2 MAX6744 GND 2 MAX6745

POK1 3 4 VCC2 PFO 3 4 PFI

SC70 SC70

Ordering Information (continued)

PART TEMP RANGE PIN-PACKAGE
MAX6738XK_D_-T -40°C to +85°C 5 SC70-5
MAX6739XK_D_-T -40°C to +85°C 5 SC70-5
MAX6740XK_ _D_-T -40°C to +85°C 5 SC70-5
MAX6741XK_ _D_-T -40°C to +85°C 5 SC70-5
MAX6742XK_D_-T -40°C to +85°C 5 SC70-5
MAX6743XK_ _D_-T -40°C to +85°C 5 SC70-5
MAX6744XK_ _D_-T -40°C to +85°C 5 SC70-5
MAX6745XK_D_-T -40°C to +85°C 5 SC70-5
Note: The first “_ _” or “_” are placeholders for the threshold
voltage levels of the devices. Desired threshold levels are set
by the part number suffix found in Tables 1 and 2. The “_” after
the D is a placeholder for the reset timeout period suffix found
in Table 3. For example, the MAX6736XKLTD3-T is a dual-volt-
age supervisor VTH1 = 4.625V, VTH2 = 3.075V, and a 150ms
minimum reset timeout period. All devices are available in
tape-and-reel only. There is a 2500-piece minimum order
increment for standard versions (see Table 1). Sample stock is
typically held on standard versions only. Nonstandard versions
require a minimum order increment of 10,000 pieces. Contact
factory for availability.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.

______________________________________________________________________________________ 15
 Low-Power Dual-/Triple-Voltage SC70 µP
Supervisory Circuits
Package Information
MAX6736–MAX6745

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

SC70, 5L.EPS
PACKAGE OUTLINE, 5L SC70
1
21-0076 C 1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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