Max6966 Max6967

19-3487; Rev 2; 4/05
KIT
ATION
EVALU BLE
AVA ILA
10-Port Constant-Current LED Drivers and I/O

Expanders with PWM Intensity Control
General Description Features
MAX6966/MAX6967
The MAX6966/MAX6967 serial-interfaced peripherals ♦ High-Speed 26MHz SPI-™/QSPI-™/MICROWIRE™-
provide microprocessors with 10 I/O ports rated to 7V. Compatible Serial Interface
Each port can be individually configured as either:
♦ 2.25V to 3.6V Operation
• A 20mA constant-current LED driver (static or pulse-
width modulated (PWM)). ♦ I/O Ports Default to High-Z (LEDs Off) on Power-Up
• A 10mA constant-current LED driver (static or PWM). ♦ I/O Port Inputs Are Overvoltage Protected to 7V
• An open-drain logic output. ♦ I/O Port Outputs Are 7V-Rated Open Drain
• An overvoltage-protected Schmitt logic input. ♦ I/O Port Outputs Are 10mA or 20mA Constant-
Analog and switching LED intensity control is built in: Current Static/PWM LED Drivers, or Open-Drain
• Individual 8-bit PWM control per output. Logic Outputs
• Individual 1-bit analog control (half/full) per output. ♦ I/O Ports Support Hot Insertion
• Global 3-bit analog control applies to all LED outputs. ♦ Individual 8-Bit PWM Intensity Control for Each LED
PWM timing of the 10 port outputs may be optionally ♦ Any Output May Use or Not Use PWM Control
staggered, consecutively phased in 45° increments.
This spreads the PWM load currents over time in eight ♦ Exit Shutdown (Warm Start) with Simple CS Pulse
steps, helping to even out the power-supply current ♦ Auto Ramp-Down into Shutdown
and reduce the RMS current.
♦ Auto Ramp-Up Out from Shutdown
The MAX6966/MAX6967 can be configured to awake
from shutdown on receipt of a minimum 3ms pulse on ♦ 0.8µA (typ), 2µA (max) Shutdown Current
the CS input. This hardware-wakeup feature allows a
power-management controller or similar ASIC to enable ♦ Tiny 3mm x 3mm, 0.8mm High Thin QFN Package
the MAX6966/MAX6967 with preconfigured LED intensi- ♦ -40°C to +125°C Temperature Range
ty settings.
Shutdown can be programmed to wait up to 4s, fade
Ordering Information
down the sink currents to zero for a period of 1/16s to TEMP PIN- TOP PKG
4s, and then shut down. A similar ramp-up from shut- PART
RANGE PACKAGE MARK CODE
down can be programmed for 1/16s to 4s.
16 Thin QFN
The MAX6966/MAX6967 support hot insertion. All port -40°C to
MAX6966ATE 3mm x 3mm x ACF T1633-4
pins remain high impedance in power-down (V+ = 0V) +125°C
0.8mm
with up to 8V asserted on them.
The DOUT/OSC pin can be configured as either the -40°C to
MAX6966AEE 16 QSOP — —
serial interface data output or optional PWM clock +125°C
input. The MAX6966 powers up defaulting as DOUT 16 Thin QFN
output. The MAX6967 defaults as OSC input. -40°C to
MAX6967ATE 3mm x 3mm x ACG T1633-4
+125°C
For a similar part without the constant-current controls, 0.8mm
refer to the MAX7317 data sheet.
-40°C to
MAX6967AEE 16 QSOP — —
Applications +125°C
LCD Backlights RGB LED Drivers

Keypad Backlights Portable Equipment
LED Status Indication Cellular Phones
SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS
MAX6966/MAX6967
Voltage (with respect to GND) Continuous Power Dissipation

V+ .............................................................................-0.3V to +4V 16-Pin QSOP (derate 8.3mW/°C over TA = +70°C) ....667mW
SCLK, DIN, CS, DOUT/OSC.........................-0.3V to (V+ + 0.3V) 16-Pin QFN (derate 14.7mW/°C over TA = +70°C) ...1176mW
P_ .............................................................................-0.3V to +8V Operating Temperature Range (TMIN to TMAX) .-40°C to +125°C
DC Current into P_ .............................................................24mA Junction Temperature ......................................................+150°C
DC Current into DOUT/OSC................................................10mA Storage Temperature Range .............................-65°C to +150°C
Total GND Current ............................................................280mA Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.25V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA =
+25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage V+ 2.25 3.60 V
Output Load External Supply
VEXT 7 V
Voltage P0–P9
Standby Current TA = +25°C 0.7 1.5

(Interface Idle, CS Run Disabled, CS at V+; other digital
ISTBY TA= TMIN to +85°C 1.7 µA
PWM Disabled, All Ports High inputs at V+ or GND
Impedance) TA= TMIN to TMAX 1.9
Supply-Current Interface Only TA = +25°C 390 620

fSCLK = 26MHz, other
(CS Run Enabled, PWM
I+ digital inputs at V+ or TA = TMIN to +85°C 680 µA
Disabled, All Ports High
GND; DOUT unloaded
Impedance) TA = TMIN to TMAX 730
Delta Supply Current per 10mA

Port (Interface Idle, Global TA = +25°C 1.58 1.8
Current Register Set to 0x07, One
Port's Output Register Set to Digital inputs at V+ or
∆I+10 TA = TMIN to +85°C 1.9 mA
0x02 and Its Output Current GND
Register Bit Cleared; All Other
Ports’ Output Registers Set to TA = TMIN to TMAX 2
0x00, 0x01, or 0xFF)
Delta Supply Current per 20mA
Port TA = +25°C 3.2 3.6
(Interface Idle, Global Current
Register Set to 0x07, One Port's Digital inputs at V+ or
∆I+20 TA = TMIN to +85°C 3.8 mA
Output Register Set to 0x02 and Its GND
Output Current Register Bit Set; All
Other Ports’ Output Registers Set to TA = TMIN to TMAX 4.0
0x00, 0x01, or 0xFF)
2 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
MAX6966/MAX6967
+25°C.) (Note 1)
Input High Voltage 0.7 x
VIH P0–P9: output register set to 0x01 V
(P0–P9, DIN, SCLK, CS, OSC) V+
Input Low Voltage 0.3 x
VIL P0–P9: output register set to 0x01 V
(P0–P9, DIN, SCLK, CS, OSC) V+
Input Leakage Current
IIH, IIL -0.2 +0.2 µA
(P0–P9, DIN, SCLK, CS, OSC)
Input Capacitance
(Note 2) 10 pF
(P0–P9, DIN, SCLK, CS, OSC)
Port Nominal Sink Constant Output register set to 19.3 20 21.1

TA = +25°C
Current 0x02, 9.5 10 10.7
IOUT mA
(P0–P9) (Global Current Register V+ = 3.3V, VEXT - VLED = TA = TMIN to 18.8 21.8
Set to 0x07) 1V to 2.5V (Note 3) +85°C 9.1 11.0
Port Logic Output Low Voltage Output register set to 0x00,
VOLP_ 0.4 V
(P0–P9) ISINK = 0.5mA
Port Logic Output Low Short- Output register set to 0x00,
10.8 20 mA
Circuit Current (P0–P9) VOLP_ = 5V
Port Slew Time From 20% current to 80% current 2 µs
TA = +25°C, V+ = 3.3V, VEXT - VLED = 1.4V,
±1.5 ±4
Port Sink Constant-Current IOUT = 20mA
∆IOUT %
Matching TA = +25°C, V+ = 3.3V, VEXT - VLED = 1.4V,
±2 ±5
IOUT = 10mA
Output High Voltage V+ -
VOHDOUT ISOURCE = 6mA V
(DOUT) 0.3V
Output Low Voltage
VOLDOUT ISINK = 6mA 0.3 V
(DOUT)
_______________________________________________________________________________________ 3
TIMING CHARACTERISTICS
MAX6966/MAX6967
+25°C.) (Note 1)
Internal PWM Clock Frequency fINT 27000 45000 Hz
External PWM Clock Frequency fOSC 100 kHz
SCLK Clock Period tCP 38.4 ns
SCLK Pulse Width High tCH 19 ns
SCLK Pulse Width Low tCL 19 ns
CS Fall to SCLK Rise Setup Time tCSS 9.5 ns
SCLK Rise to CS Rise Hold Time tCSH 0 ns
DIN Setup Time tDS 9.5 ns
DIN Hold Time tDH 0 ns
Output Data Propagation Delay tDO 21 ns
DOUT Output Rise and Fall
tFT CLOAD = 20pF 10 ns
Times
Minimum CS Pulse High tCSW 38.4 ns
CS Pulse Low to Not Activate CS
tCSRUN CS run enabled 640 µs
Run
CS Pulse Width to Activate CS
tCSRUN CS run enabled 3 ms
Run
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: Port current is factory trimmed to meet a median sink current of 20mA and 10mA over all 10 ports. The ∆IOUT specification
guarantees current matching between ports.
4 _______________________________________________________________________________________
Typical Operating Characteristics
MAX6966/MAX6967
(TA = +25°C, unless otherwise noted.)
STANDBY CURRENT (ISTBY1) SUPPLY CURRENT (I+) OUTPUT SINKING CURRENT

vs. TEMPERATURE vs. TEMPERATURE vs. VEXT - VLED AT 10mA
1.2 0.5 14
MAX6966/67 toc01
MAX6966/67 toc02
MAX6966/67 toc03
1.1 V+ = 3.6V
V+ = 3.3V 12
OUTPUT SINKING CURRENT (mA)

V+ = 3.6V 0.4
1.0
STANDBY CURRENT (µA)
SUPPLY CURRENT (mA)

V+ = 3.3V 10
0.9 0.3
V+ = 2.7V 8
0.8 V+ = 2.7V
0.2 6
0.7
V+ = 2.25V 4
0.6
0.1
0.5 V+ = 2.25V 2
0.4 0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 1 2 3 4 5
TEMPERATURE (°C) TEMPERATURE (°C) VEXT - VLED (V)
OUTPUT SINKING CURRENT INTERNAL OSCILLATOR FREQUENCY

vs. VEXT - VLED AT 20mA vs. TEMPERATURE
24 45
MAX6966/67 toc05
MAX6966/67 toc04
43
20
OUTPUT SINKING CURRENT (mA)
41 V+ = 3.3V
V+ = 3.6V
FREQUENCY (kHz)
16 39
37
12
35
8 33 V+ = 2.7V
V+ = 2.25V
31
4
29
0 27
0 1 2 3 4 5 -40 -25 -10 5 20 35 50 65 80 95 110 125
VEXT - VLED (V) TEMPERATURE (°C)
STAGGER PWM PORT WAVEFORMS

SAMPLE PWM WAVEFORMS (OUTPUT REGISTERS SET TO 0x80)
MAX6966/67 toc06 MAX6966/67 toc07
OUTPUT
REGISTER PORT P4
= 0x03
OUTPUT
REGISTER PORT P0
= 0x80
OUTPUT
REGISTER PORT P1
= 0xFE
2ms 2ms
_______________________________________________________________________________________ 5
Pin Description
MAX6966/MAX6967
PIN
NAME FUNCTION
QSOP TQFN
Serial-Clock Input. On SCLK’s rising edge, data shifts into the internal shift register. On SCLK’s
1 15 SCLK
falling edge, data is clocked out of DOUT. SCLK is active only while CS is low.
Chip-Select Input. Serial data is loaded into the shift register while CS is low. The most recent 16
2 16 CS
bits of data latch on CS’s rising edge.
I/O Ports. P0 to P9 can be configured as open-drain current-sink outputs rated at 20mA

3–7, 1–5,
P0-P9 maximum, or as CMOS-logic inputs, or as open-drain logic outputs. Loads should be connected
9-13 7-11
to a supply voltage no higher than 7V.
8 6 GND Ground
Serial-Data Output. The data into DIN is valid at DOUT 15.5 clock cycles later. Use this pin to
daisy-chain several devices or allow data readback. Output is push-pull.
14 12 DOUT/OSC OSC Input. Apply a square-wave CMOS clock up to 100kHz as alternate PWM clock source.
The MAX6966 powers up with DOUT/OSC defaulting as DOUT output.
The MAX6967 powers up with DOUT/OSC defaulting as OSC input.
Serial-Data Input. Data from DIN loads into the internal 16-bit shift register on SCLK’s rising
15 13 DIN
edge.
16 14 V+ Positive Supply Voltage. Bypass V+ to GND with a 0.1µF ceramic capacitor.
Exposed
— PAD Exposed Pad on Package Underside. Connect to GND.
pad
Quick-Start Guide any ports are used as logic input, or if the applica-
tion needs read-after-write validation, then
This section describes how to configure a MAX6966 or
DOUT/OSC needs to be configured as DOUT. Note
MAX6967 on power-up.
that both the MAX6966 and MAX6967 can configure
Software engineers can use this section as a plain-text DOUT/OSC as either DOUT output or OSC clock
guide to the device’s initialization routine. Hardware input; the only difference is the power-up default.
engineers can use this section to get a quick overview
4) Allocate port functionality for the 10 I/O ports. All
of the device’s capabilities and feature tradeoffs:
ports have the same features, so allocate ports for
1) Before power-up, all 10 I/O ports P0 to P9 are high either software convenience or board-routing rea-
impedance. They may be connected to inputs up to sons. Any port can be constant-current LED drivers
+7V or loads connected to independent rails up to (static or PWM), an open-drain logic output, or a
+7V. The SPI bus inputs (SCLK, CS, DIN) are not logic input. If fewer than 10 ports are used as con-
overvoltage protected, and must not be driven from stant-current drivers, see the Applications
a voltage higher than V+. Information section for details on how to optimize the
2) After power-up, all 10 I/O ports P0 to P9 remain PWM phasing to minimize load supply-current mod-
high impedance. They may be connected to inputs ulation.
up to +7V or loads connected to V+ or independent 5) Decide how to implement LED intensity control.
rails up to +7V. The ports are not configured as logic The MAX6966/MAX6967 provide:
inputs even though the ports are high impedance.
• Individual 8-bit PWM control per constant-current
The device is in shutdown mode, and draws mini-
output
mum supply current regardless of I/O ports connec-
tions. • Individual 1-bit analog control (half/full) per
constant-current output
3) Decide whether the DOUT/OSC pin will be used
as SPI data output or PWM clock input, and • Global 3-bit analog control, which applies to all
choose the MAX6966 or MAX6967 accordingly. If constant-current outputs
6 _______________________________________________________________________________________
The tradeoff for LED intensity control is between simple overshoot-damping terminations may be
MAX6966/MAX6967
depth of current-control resolution, noise constraints, required if the tracks are long.
and software complexity:
Detailed Description
• For high LED resolution where each LED needs
individual intensity settings, use the 8-bit PWM The MAX6966/MAX6967 are general-purpose input/out-
control plus the 1-bit analog control to get 9 bits put (GPIO) peripherals that provide 10 I/O ports, P0 to
of individual LED intensity control. P9, controlled through a high-speed SPI-compatible
serial interface. The 10 I/O ports can be used as logic
• For absolute maximum LED resolution where the inputs, open-drain logic outputs, or constant-current
LED uses the same intensity settings, use the 8- sinks in any combination. Ports withstand 7V indepen-
bit PWM control plus the 1-bit analog control, dent of the MAX6966’s or MAX6967’s supply voltage
plus the global 3-bit analog control to get 12 bits whether used as logic inputs, logic outputs, or con-
of LED intensity control. stant-current sinks.
• For lowest noise applications where PWM cannot Ports configured as constant-current outputs can be set
be used, 1 bit of individual analog control is to sink either a constant current of either 10mA or 20mA.
available. If all LEDs use the same intensity set- The static port current may be PWM with a duty cycle
tings, the 1-bit analog control plus the global 3- ranging from 3/256 to 254/256 to reduce the average
bit analog control provide 4 bits of static LED current, or remain static.
intensity control.
Ports configured as open-drain logic outputs have a
• If the standard half/full constant-current settings relatively weak sink capability, which should still be
of 10mA/20mA are not acceptable, then the adequate for normal logic-level outputs. Open-drain
global 3-bit analog control can be used to logic outputs typically require external pullup resistors
reduce the currents for all the constant-current to the appropriate positive supply to provide the logic-
outputs. high reference. The weak drive means that the short-
6) Take care with PC board layout. The MAX6966/ circuit current is low enough that inadvertently driving
MAX6967 are switching moderate currents in PWM an LED from a port configured as a logic output is
applications, so the MAX6966/MAX6967 and the unlikely to damage the LED.
load supplies need careful decoupling to minimize The MAX6966/MAX6967 are rated for all 10 outputs to
conducted noise. Also, the serial interface is fast, so carry their maximum 20mA loads at the same time. The
port configuration options are shown in Table 1.
Table 1. Port Configuration Options

OUTPUT BEHAVIOR OUT OF BEHAVIOR IN SHUTDOWN
PORT TYPE REGISTER SHUTDOWN (CONFIGURATION (CONFIGURATION REGISTER APPLICATION NOTES
CODE REGISTER BIT D0 = 1) BIT D0 = 0)
Low-logic
0x00 Logic-low output, not constant current
output
Lowest supply current
High-logic Logic-high output with external pullup resistor; otherwise, high unaffected by shutdown
output 0x01 impedance
Logic input CMOS logic input
Constant-
Static constant-current sink Full constant-current drive
current static 0x02
output with no PWM noise
sink output
High impedance
Constant-
current PWM 0x03–0xFE PWM constant-current sink output Adjustable constant current
output
Logic-high output with external pullup resistor; otherwise, high

LED off 0xFF LED off
impedance
_______________________________________________________________________________________ 7
MAX6966/MAX6967
I/O PORT
A B
POSITION A: 0x00 - 0x01
POSITION B: 0x02 - 0xFF
ENABLE = 0x00
CLOSE SWITCH: 0x02-0xFE
8-BIT LATCH
OUTPUT PORT PWM
REGISTER GENERATOR
ENABLE
1-BIT LATCH MSB SET N
OUTPUT CURRENT CURRENT
TO/FROM REGISTER
SERIAL
INTERFACE 4-BIT DAC
3-BIT LATCH
GLOBAL CURRENT
REGISTER
READ I/O
PORT COMMAND
Figure 1. Simplified Schematic of I/O Ports
Figure 1 shows the I/O port structure of the MAX6966/ and off through the serial interface, as well as by the
MAX6967. I/O ports P0 to P9 default to high impedance PWM intensity control.
on power-up, so LED or other port loads connected
draw no current, and ports used as inputs do not load Shutdown Mode
their source signals. In shutdown mode, all ports configured as constant-cur-
rent outputs (output register set to a value between 0x02
Standby Mode and Operating Current and 0xFE) are switched off, and these outputs go high
When all the ports are configured as logic inputs or out- impedance as if their registers were set to value 0xFF.
puts (all output registers set to value 0x00 or 0x01) or Ports configured as logic inputs or outputs (output regis-
LED off (output register set to value 0xFF), the ters set to value 0x00 or 0x01) are unaffected (Table 1).
MAX6966/MAX6967 operate at their lowest supply cur- This means that any ports used for GPIOs are still fully
rent, called standby mode. operational in shutdown mode, and port inputs can be
When PWM intensity control is used (one or more out- read and output ports can be toggled at any time using
put registers set to a value between 0x03 and 0xFE), the serial interface. The MAX6966/MAX6967 can there-
the operating current increases because the internal fore be used for a mix of logic inputs, logic outputs, and
PWM circuitry is running. PWM LED drivers, and only the LED drivers are turned
off automatically in shutdown.
The operating current also increases whenever a port
that is set is active low as a constant-current output The MAX6966/MAX6967 are put into shutdown mode
(output register set to a value between 0x02 and 0xFE), by clearing the run bit (bit D0) in the configuration reg-
even if a load is not applied to the port. This current ister (Table 4). Shutdown is exited by setting the run bit
increase is due to an internal current mirror being through the serial interface, or by using the CS run
enabled for that port output to provide the accurate option discussed below. The MAX6966/MAX6967 can
constant-current sink. There is a gated mirror for each be configured and controlled in the normal way through
output, and each mirror is only enabled when required. the serial interface in shutdown mode. All registers are
When PWM is used, a current mirror is only turned on accessible in shutdown mode, and no register is
for the output’s on-time. This means that operating cur- changed by shutdown mode. When shutdown mode is
rent varies as constant-current outputs are turned on exited, ports configured as constant-current outputs at
that time start instantly with their current PWM values.
8 _______________________________________________________________________________________
If a port is changed from static logic low (0x00) or static The maximum pulse on CS to ensure that CS run is not
MAX6966/MAX6967
logic high (0x01) to a constant-current value triggered (when enabled) is 255 periods of the PWM
(0x02–0xFE) in shutdown mode, then that output is clock. For the internal oscillator, this time is 255 / 45000
automatically turned off (logic high, or high impedance) = 5.66ms. Since a transmission on the serial interface
like any other constant-current outputs that are dis- comprises 16 clocks with CS low, a minimum 2.83kHz
abled in shutdown. When shutdown mode is exited, the SCLK frequency ensures that CS run is not triggered.
new constant-current output starts just like any other For the external PWM clock, this time is 255 / OSC and
constant-current outputs. has a shortest time of 2.55ms when OSC is set to the
If a port is changed from a constant-current value maximum allowed frequency of 100kHz.
(0x02–0xFE) to static logic low (0x00) or static logic The SPI serial interface circuitry is independent of the
high (0x01) in shutdown mode, then that output is CS run circuitry. Activity on SCLK and DIN is ignored
instantly set to that value as a GPIO output. When shut- by the CS run circuitry. A slow SPI transmission to the
down mode is exited, the new GPIO output is unaffect- MAX6966/MAX6967 can therefore be used as both a
ed just like any other GPIO outputs. valid data transmission (read or write), and as a means
for exiting shutdown. The CS run action (i.e., setting the
CS Run Option run bit in the configuration register) occurs before any
The MAX6966/MAX6967 can be configured so that a coincident data transmission is processed. This means
relatively long pulse on the CS input brings the driver that a slow transmission containing a write command to
out of shutdown, as an alternative method to the normal the configuration register clearing the run bit would
method of writing the configuration register through the work, since the write command is implemented internal-
serial interface. When the CS run option is enabled, a ly after the CS run action that sets the run bit.
minimum pulse on CS sets the run bit in the configura-
tion register, bringing the driver out of shutdown and The "slow transmission" cut-off data rate is expected to
activating any preconfigured ramp-up. Also, the SPI be lower than the SPI interface speed in the majority of
interface must be operated at a minimum data rate to applications. If this is not the case, the CS run option
ensure that a normal active-low CS pulse during a 16- can still be used. Consider the situation when the
bit regular data transmission is not mistaken for a CS MAX6966/MAX6967 have been put into shutdown with
run command. the CS run option enabled. The application uses the
MAX6966/MAX6967 with some ports configured as
The CS run timing uses the PWM clock, which is either logic inputs or outputs, which need to be accessed in
the internal nominal 32kHz oscillator or a user-provided shutdown. The SPI interface speed is slow, so any
clock fed into the dual-use DOUT/OSC pin (see the PWM transmission brings the MAX6966/MAX6967 out of shut-
Clock section for details on configuring the PWM clock). down. So, how are the I/O ports accessed in shut-
The minimum pulse on CS to trigger CS run and bring down? The solution is to write the configuration register
the driver out of shutdown is 256 to 257 periods of the disabling CS run (bit D1 = 0) and invoking shutdown
PWM clock. For the internal oscillator, this time is 257 / (bit D0 = 0) as the first command. Now any other regis-
27000 = 9.52ms. For the external PWM clock, this time ters can be accessed while the MAX6966/MAX6967
is 257 / OSC and has a shortest possible time of remain in shutdown. Finally, write the configuration reg-
2.57ms when OSC is set to the maximum allowed ister reenabling CS run (bit D1 = 1) and invoking shut-
100kHz frequency. down (bit D0 = 0) to restore the original status.
_______________________________________________________________________________________ 9
Register Structure 0x0A–0x0D allow more than one register to be written
MAX6966/MAX6967
The MAX6966/MAX6967 contain 16 internal registers, with the same data to simplify software. The no-op
addressed as 0x00–0x09, and 0x10–0x15, which con- address, 0x20, causes no action when written or read,
figure and control the peripheral (Table 2). Two and is used as a dummy register when accessing one
addresses, 0x0E and 0x0F, do not store data but return MAX6966/MAX6967 out of multiple cascaded devices.
the port input status when read. Four virtual addresses,
Table 2. Register Address Map

COMMAND ADDRESS HEX
REGISTER
D15 D14 D13 D12 D11 D10 D9 D8 CODE
Port P0 output level or PWM R/W 0 0 0 0 0 0 0 0x00
Write ports P0 through P9 with same output level or
0
PWM 0 0 0 1 0 1 0 0x0A
Read port P0 output level or PWM 1
0
PWM 0 0 0 1 0 1 1 0x0B
0
PWM 0 0 0 1 1 0 0 0x0C
Write ports P8 or P9 with same output level or PWM 0
0 0 0 1 1 0 1 0x0D
Read ports P7 through P0 inputs 1 0 0 0 1 1 1 0 0x0E
Read ports P9 and P8 inputs 1 0 0 0 1 1 1 1 0x0F
Configuration R/W 0 0 1 0 0 0 0 0x10
Ramp-down R/W 0 0 1 0 0 0 1 0x11
Ramp-up R/W 0 0 1 0 0 1 0 0x12
Output current ISET70 R/W 0 0 1 0 0 1 1 0x13
Output current ISET98 R/W 0 0 1 0 1 0 0 0x14
Global current R/W 0 0 1 0 1 0 1 0x15
No-op R/W 0 1 0 0 0 0 0 0x20
Factory reserved; do not write to this register R/W 1 1 1 1 1 0 1 0x7D
10 ______________________________________________________________________________________
Initial Power-Up lator and PWM logic are disabled automatically, and
MAX6966/MAX6967
On power-up, all control registers are reset (Table 3). the MAX6966/MAX6967 operating current is lowest.
Power-up status sets I/O ports P0 to P9 high imped- The internal 32kHz oscillator can be replaced by a user
ance, and puts the device into shutdown mode. This clock up to 100kHz if a precise or synchronized PWM
means that any LED (or other) loads are effectively frequency source is desired. The clock is fed into the
turned off, and the MAX6966/MAX6967 start in its low- dual-use DOUT/OSC pin, which is switched between a
est power condition. port output and a clock input using the OSC bit in the
configuration register (Table 4).
PWM Clock
An internal 32kHz oscillator generates PWM timing. If
all output ports are set to static levels, the internal oscil-
Table 3. Initial Power-Up Register Status

ADDRESS REGISTER DATA
REGISTER POWER-UP CONDITION
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
Port P0 output level or PWM Port 0 high impedance 0x00 1 1 1 1 1 1 1 1
Shutdown mode,
Configuration (MAX6966
CS run disabled, 0
only)
DOUT/OSC is DOUT output
0x10 0 0 0 0 0 0 0
Shutdown mode,
Configuration (MAX6967
CS run disabled, 1
only)
DOUT/OSC is OSC input
Ramp-down Fade disabled 0x11 0 0 0 0 0 0 0 0
Ramp-up — 0x12 0 0 0 0 0 0 0 0
Output current ISET70 IPEAK = 10mA for ports P7–P0 0x13 0 0 0 0 0 0 0 0
Output current ISET98 IPEAK = 10mA for ports P9, P8 0x14 0 0 0 0 0 0 0 0
Global current Full current 0x15 0 0 0 0 0 1 1 1
______________________________________________________________________________________ 11
PWM Timing and Phasing that if, for example, all outputs are set to 128/256 duty
MAX6966/MAX6967
A PWM period comprises 256 cycles of the nominal cycle, the current draw would be zero (all loads off) for
32kHz PWM clock (Figure 2). Ports can be set individu- half the time and full (all loads on) for the other half.
ally to a PWM duty between 3/256 and 254/256. When the stagger bit is set, the PWM timing of the 10 port
PWM timing can be configured one of two ways by the outputs is staggered by 32 counts of the 256-count PWM
setting of the stagger bit in the configuration register period (i.e., 1/8), distributing the port output switching
(Table 4). When the stagger bit is clear, all outputs using points across the PWM period (Figure 3). The staggering
PWM switch at the same time use the timing shown in reduces the di/dt output-switching transient on the supply,
Figure 2. All outputs therefore draw load current at exact- and also reduces the peak/mean current requirement.
ly the same time for the same PWM setting. This means
OUTPUT
REGISTER
VALUE 7.8125ms NOMINAL PWM PERIOD
HIGH-Z
0x00 OUTPUT STATIC-LOW LOGIC DRIVE WITH INPUT BUFFER ENABLED (GPI)
LOW
HIGH-Z
0x01 OUTPUT STATIC-HIGH LOGIC DRIVE WITH INPUT BUFFER ENABLED (GPI)
LOW
HIGH-Z
0x02 OUTPUT STATIC-LOW CONSTANT CURRENT WITH INPUT BUFFER DISABLED (STATIC LED DRIVE ON)
LOW
HIGH-Z
0x03
OUTPUT LOW 3/256 DUTY CONSTANT CURRENT WITH INPUT BUFFER DISABLED (PWM LED DRIVE) LOW
HIGH-Z
0x04
OUTPUT LOW 4/256 DUTY CONSTANT CURRENT WITH INPUT BUFFER DISABLED (PWM LED DRIVE) LOW
HIGH-Z
OUTPUT LOW 252/256 DUTY CONSTANT CURRENT WITH INPUT BUFFER DISABLED (PWM LED DRIVE)
0xFC
LOW
OUTPUT LOW 253/256 DUTY CONSTANT CURRENT WITH INPUT BUFFER DISABLED (PWM LED DRIVE) HIGH-Z
0xFD
LOW
HIGH-Z
OUTPUT LOW 254/256 DUTY CONSTANT CURRENT WITH INPUT BUFFER DISABLED (PWM LED DRIVE)
0xFE
LOW
HIGH-Z
0xFF OUTPUT STATIC HIGH IMPEDANCE WITH INPUT BUFFER DISABLED (STATIC LED DRIVE OFF)
LOW
Figure 2. Static and PWM Constant-Current Waveforms
7.8125ms NOMINAL PWM PERIOD NEXT PWM PERIOD NEXT PWM PERIOD
0 32 64 96 128 160 192 224 256

OUTPUTS P0, O8 IN-PHASE PWM PERIOD OUTPUTS P0, O8 IN-PHASE PWM PERIOD OUTPUTS P0, O8 IN-PHASE PWM PERIOD
OUTPUT P1, O9 STAGGERED PWM PERIOD OUTPUT P1, O9 STAGGERED PWM PERIOD OUTPUT P1, O9 STAGGERED PWM PERIOD
OUTPUT P2 STAGGERED PWM PERIOD OUTPUT P2 STAGGERED PWM PERIOD
Figure 3. Staggered PWM Waveform
12 ______________________________________________________________________________________
Table 4. Configuration Register
MAX6966/MAX6967
REGISTER R/W CODE
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
Ramp-
Hold- Fade-
DOUT PWM up Shutdown/
CONFIGURATION X off off CS run
/OSC stagger enable/ run
status status
status
Ramp-
Write device configuration 0 up
Hold- Fade- enable
OSC X Stagger CS run Run
off off Ramp-
0x10
Read-back device configuration 1 up
status
Shutdown mode (CS run disabled)
Put or keep device in shutdown, 0 X X X X X X 0 0
disable CS run
Shutdown mode (CS run enabled)
Put or keep device in shutdown, 0 X X X X X X 1 0
enable CS run
Run mode
0 X X X 0* 0* X X 1
(device is currently in run mode)
Run (exit shutdown) without ramp-up
(device is currently in shutdown);
0 X X X 0* 0* 0 X 1
bring device out of shutdown
instantly, ignoring fade register setting
Run (exit shutdown) with ramp-up
(device is currently in shutdown);
0 X X X 0* 0* 1 X 1
bring device out of shutdown using
fade register ramp-up setting
Run (abort shutdown sequence) 0* 1*
(device is currently in hold-off/fade-off 1* 0*
sequence to shutdown); 0 X X X 1 X 1
bring device out of shutdown 1* 1*
instantly, ignoring fade register setting
Status: shutdown mode 1 X X Stagger 0 0 0 CS run 0
Status: in fade-off sequence to
1 X X Stagger 0 1 0 CS run 0
shutdown mode
Status: in hold-off sequence to
shutdown mode
Status: run mode 1 X X Stagger 0 0 0 CS run 1
Status: in ramp-up sequence to run
mode
PWM outputs are in phase X X X 0 X X X X X
PWM outputs stagger phase X X X 1 X X X X X
DOUT/OSC is DOUT output,
X 0 X X X X X X X
PWM clock source is internal oscillator
DOUT/OSC is OSC input,
X 1 X X X X X X X
PWM clock source is OSC
*Current read status of this bit.
______________________________________________________________________________________ 13
The stagger bit is ideally set or cleared when the Output Registers and
MAX6966/MAX6967
MAX6966/MAX6967 are in shutdown. If not, there may be PWM Intensity Control

a perceived transient flicker in any PWM-controlled LEDs The MAX6966/MAX6967 use one 8-bit register to control
because the fundamental PWM timing is being changed. each output port (Table 6). Each port may be configured
as a logic input, open-drain logic output, or constant-cur-
Configuration Register rent sink with programmable current and PWM duty
The configuration register is used to select PWM phas- cycle. Ports withstand 7V independent of the MAX6966’s
ing between outputs, test fade status, enable hardware or MAX6967’s supply voltage, whether used as logic
startup from shutdown, and select shutdown or run inputs, logic outputs, or constant-current sinks.
mode (Table 4).
Ports configured as constant-current outputs sink a con-
GPIO Port Direction Configuration stant current set by the output current registers (Table 7)
The 10 I/O ports P0 through P9 can be configured to and the global current registers (Table 8). This current
any combination of logic inputs, logic outputs, and con- may be PWM with a duty cycle ranging from 3/256 to
stant-current outputs. Configure any port as a logic 254/256 to reduce the average current, or remain static.
input by setting its output register to 0x01, which sets The 10 registers 0x00 through 0x09 control an I/O port
the port output high impedance (Table 6). each (Table 6). Five pseudo-register addresses, 0x0B
Input Ports Registers through 0x0F, allow groups of outputs to be set to the
Reading an input port register returns the logic levels at same value with a single command by writing the same
the I/O port pins for ports that have been configured as a data to multiple output registers.
logic input (Table 5). A port is configured as a logic input PWM timing for LED intensity control is generated using
by writing 0x01 to the port’s output register (Table 5). An either the internal 32kHz oscillator, or an external clock
input ports register returns logic 0 in the appropriate bit on DOUT/OSC. The PWM clock source is selected by
position for a port not configured as a logic input. configuration register bit D7 (Table 4). The MAX6966
The input ports registers are read only. A write to an powers up configured to use the internal 32kHz oscilla-
input ports register is ignored. tor by default. The MAX6967 powers up configured to
use the external clock source by default.
Table 5. Input Ports Register

REGISTER R/W CODE
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
Read input ports P7–P0 1 0x0E Port P7 Port P6 Port P5 Port P4 Port P3 Port P2 Port P1 Port P0
Read input ports P9–P8 1 0x0F 0 0 0 0 0 0 Port P9 Port P8
14 ______________________________________________________________________________________
Table 6. Output Registers Format
MAX6966/MAX6967
REGISTER R/W CODE BINARY HEX
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
PORT P0 LEVEL OR PWM X MSB OUTPUT P0 LEVEL AND PWM LSB
Port P0 is static-low logic-level logic
port with logic input buffer enabled;
X 0 0 0 0 0 0 0 0 0x00
reading this port returns 0. Still active
in shutdown.
Port P0 is static-high logic-level logic
port (high impedance without external
pullup) or logic input with logic input
X 0 0 0 0 0 0 0 1 0x01
buffer enabled; reading this port
returns 0 or 1, depending on external
conditions. Still active in shutdown.
Port P0 is static-low constant-current
sink (PWM disabled). Logic input
buffer is disabled; reading this port X 0 0 0 0 0 0 1 0 0x02
always returns 0. High impedance in
shutdown.
Port P0 duty cycle is 3/256 current
sink. GPI logic input buffer is
disabled; reading this port always X 0 0 0 0 0 0 1 1 0x03
returns 0. High impedance in
shutdown.
0x00
disabled; reading this port always X 0 0 0 0 0 1 0 0 0x04
shutdown.
— X — — — — — — — — —
disabled; reading this port always X 1 1 1 1 1 1 0 1 0xFD
shutdown.
disabled; reading this port always X 1 1 1 1 1 1 1 0 0xFE
shutdown.
Port P0 is static high impedance
(PWM disabled). GPI logic input
buffer is disabled; reading this port X 1 1 1 1 1 1 1 1 0xFF
always returns 0. High impedance in
shutdown.
______________________________________________________________________________________ 15
Table 6. Output Registers Format (continued)
MAX6966/MAX6967
REGISTER DATA
ADDRESS
BINARY HEX
REGISTER R/W CODE
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
MSB OUTPUT P0 LEVEL AND PWM LSB
Port P1 level or PWM X 0x01 MSB Port P1 level or PWM LSB

0x00
Writes ports P0 through P9 with
0 MSB Ports P0 through P9 level or PWM LSB
same level or PWM 0x0A to
Reads port P0 level or PWM 1 MSB Port P0 level or PWM LSB
0xFF
same level or PWM 0x0B
same level or PWM 0x0C
Write ports P8 and P9 with same
0 MSB Ports P8, P9 level, or PWM LSB
level or PWM 0x0D
16 ______________________________________________________________________________________
Output Current Registers Each output current can be set individually to best suit
MAX6966/MAX6967
Each output port’s individual constant-current sink can the maximum operating current of an LED load, or even
be set to be either half or full global current. The indi- adjusted on the fly to double the effective intensity con-
vidual currents are set by the output current registers trol range of each output. When the global current reg-
(Table 7). The global current is set by the global current ister is set to maximum, the individual current selection
register (Table 8). is 10mA (half) or 20mA (full).
Table 7. Output Current Register Format

REGISTER R/W
CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
IOUT IOUT IOUT IOUT IOUT IOUT IOUT IOUT
OUTPUT CURRENT IOUT70 X
7 6 5 4 3 2 1 0
Output P0 is set to half constant current X X X X X X X X 0
Output P0 is set to full constant current X X X X X X X X 1
Output P1 is set to half constant current X X X X X X X 0 X
Output P1 is set to full constant current X X X X X X X 1 X
Output P2 is set to half constant current X X X X X X 0 X X
Output P2 is set to full constant current X X X X X X 1 X X
Output P3 is set to half constant current X X X X X 0 X X X
0x13
Output P3 is set to full constant current X X X X X 1 X X X
Output P4 is set to half constant current X X X X 0 X X X X
Output P4 is set to full constant current X X X X 1 X X X X
Output P5 is set to half constant current X X X 0 X X X X X
Output P5 is set to full constant current X X X 1 X X X X X
Output P6 is set to half constant current X X 0 X X X X X X
Output P6 is set to full constant current X X 1 X X X X X X
Output P7 is set to half constant current X 0 X X X X X X X
Output P7 is set to full constant current X 1 X X X X X X X
0 X X X X X X IOUT9 IOUT8
OUTPUT CURRENT IOUT98
1 0 0 0 0 0 0 IOUT9 IOUT8
Output P8 is set to half constant current X X X X X X X X 0
0x14
Output P8 is set to full constant current X X X X X X X X 1
Output P9 is set to half constant current X X X X X X X 0 X
Output P9 is set to full constant current X X X X X X X 1 X
______________________________________________________________________________________ 17
Table 8. Global Current Register Format
MAX6966/MAX6967

REGISTER R/W
CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
0 X X X X X ISET2 ISET1 ISET0
GLOBAL CURRENT
1 0 0 0 0 0 ISET2 ISET1 ISET0
Full current is 2.5mA; half current is
X X X X X X 0 0 0
1.25mA
Full current is 5mA; half current is 2.5mA X X X X X X 0 0 1
X X X X X X 0 1 0
3.75mA
0x15
Full current is 10mA; half current is 5mA X X X X X X 0 1 1
X X X X X X 1 0 0
6.25mA
Full current is 15mA; half current is 7.5mA X X X X X X 1 0 1
X X X X X X 1 1 0
8.75mA
Full current is 20mA; half current is 10mA X X X X X X 1 1 1
Global Current Register ZERO TO 4s CURRENT RAMP-UP AFTER CS RUN

The global current register sets the full (maximum) con-
stant current sunk into an I/O port (Table 8). Each out- 1/8s
1/16s
put port’s individual constant-current sink can be set to
be either half or full global current by the output current 1/4s 1/2s 1s 2s 4s
registers (Table 7). By default, maximum current is
20mA, so the default half current is 10mA.
Ramp-Up and Ramp-Down Controls
The MAX6966/MAX6967 provide automatic controls EXIT SHUTDOWN COMMAND
that allow the currents’ outputs to be ramped down into
automatic shutdown (ramp-down), and ramped up Figure 4. Ramp-Up Behavior
again out of shutdown (ramp-up) without further inter-
action (Figures 4 and 5). Ramp-down comprises a pro- fade-off time, during which the currents’ outputs are
grammable hold-off delay, which also maintains the ramped down.
outputs at full current for a time before the programmed
ZERO TO 8s CURRENT RAMP-DOWN
ZERO TO 4s HOLD-OFF DELAY BEFORE FADE-OFF ZERO TO 4s CURRENT FADE-OFF AFTER HOLD-OFF DELAY
1/4s 1/2s 1s 2s 4s 1/4s 1/2s 1s 2s 4s

1/8s 1/8s
1/16s 1/16s
Figure 5. Ramp-Down, Hold-Off, and Fade-Off Behavior
18 ______________________________________________________________________________________
The ramp-down register sets the hold-off and fade-off register) and determine whether CS run is enabled for
MAX6966/MAX6967
times and allows hold-off and fade-off to be disabled restart, and whether ramp-up is to be used for restart.
(zero delay), if desired (Table 9). The ramp-up register
sets the ramp-up time and allows ramp-up to be dis-
abled (zero delay), if desired (Table 10). The configura-
tion register contains 3 status bits that identify whether
the MAX6966/MAX6967 are in hold-off, fade-off, or ramp-
up condition (Table 4). The configuration register also
enables or disables ramp-up. One write to the configura-
tion register can put the MAX6966/MAX6967 into shut-
down (using hold-off and fade-off settings in the fade
Table 9. Ramp-Down Register Format

REGISTER R/W CODE
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
Write ramp-down 0 X X
Hold-off Fade-off
Read ramp-down 1 0 0
Fade-off time (fPWM = 32768Hz)

Instant going into shutdown after hold-off delay X X X X X X 0 0 0
1/16s ramp-down from full current before shutdown after
X X X X X X 0 0 1
hold-off delay
X X X X X X 0 1 0
hold-off delay
X X X X X X 0 1 1
hold-off delay
X X X X X X 1 0 0
hold-off delay
1s ramp-down from full current before shutdown after
X X X X X X 1 0 1
hold-off delay 0x11
X X X X X X 1 1 0
hold-off delay
X X X X X X 1 1 1
hold-off delay
Hold-off time (fPWM = 32768Hz)

Zero hold-off delay before fade-off going into shutdown X X X 0 0 0 X X X
1/16s hold-off delay before fade-off going into shutdown X X X 0 0 1 X X X
1s hold-off delay before fade-off going into shutdown X X X 1 0 1 X X X
______________________________________________________________________________________ 19
Table 10. Ramp-Up Register Format
MAX6966/MAX6967

REGISTER R/W CODE
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
Write ramp-up 0 X X X X X
Ramp-up
Read ramp-up 1 0 0 0 0 0
0x12
Ramp-up time (fPWM = 32768Hz)
Instant full current coming out from shutdown X X X X X X 0 0 0
1/16s ramp-up to full current coming out from shutdown X X X X X X 0 0 1
1s ramp-up to full current coming out from shutdown X X X X X X 1 0 1
Ramp-up and ramp-down use the PWM clock for timing. are adjusted at the same ratio with respect to each
If the external oscillator is selected, then this clock other. This means that LEDs are always faded at the
should be provided until the end of the sequence. If the same rate even if their different intensity settings are
internal oscillator is selected, it always runs during a totally different. Figure 6 shows output fade DAC.
fade sequence, even if none of the ports are using PWM. The maximum port output current set by the global cur-
The ramp-up and ramp-down circuit operates a 3-bit rent register (Table 8) also sets the point during ramp-
DAC. The DAC adjusts the internal current reference down that the current starts falling, and the point during
used to set the constant-current outputs in a similar ramp-up that the current stops rising. Figure 7 shows
manner to the global current register (Table 8). the ramp waveforms that occur with different global
Because it is the master current reference that is current register settings.
scaled, all output constant-current and PWM settings
CURRENT GLOBAL CURRENT = 0x07

20mA
CURRENT PORT CURRENT = FULL
20mA
GLOBAL CURRENT = 0x06
17.5mA
17.5mA
15mA
15mA
12.5mA
12.5mA
PORT CURRENT = HALF

10mA
10mA

7.5mA 7.5mA
5mA
5mA
2.5mA GLOBAL CURRENT = 0x00

2.5mA
0mA
FULL 7/8 6/8 5/8 4/8 3/8 2/8 1/8 ZERO 0mA
CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT FULL 7/8 6/8 5/8 4/8 3/8 2/8 1/8 ZERO
FADE-UP CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT
FADE-OFF FADE-UP
FADE-OFF
Figure 6. Output Fade DAC (Global Current = 0x07) Figure 7. Global Current Modifies Fade Behavior
20 ______________________________________________________________________________________
Serial Interface Control and Operation Using the 4-Wire
MAX6966/MAX6967
Interface
The MAX6966/MAX6967 communicate through an SPI-
compatible 4-wire serial interface. The interface has Controlling the MAX6966/MAX6967 requires sending a
three inputs: clock (SCLK), chip select (CS), and data 16-bit word. The first byte, D15 through D8, is the com-
in (DIN), and one output, data out (DOUT). CS must be mand, and the second byte, D7 through D0, is the data
low to clock data into or out of the device, and DIN byte (Table 11).
must be stable when sampled on the rising edge of
SCLK. DOUT is stable on the rising edge of SCLK.
Connecting Multiple MAX6966/MAX6967s
to the 4-Wire Bus
Note that the SPI protocol expects DOUT to be high Multiple MAX6966/MAX6967s can be interfaced to a
impedance when the MAX6966/MAX6967 are not being common SPI bus by connecting DIN inputs together,
accessed; DOUT on the MAX6966/MAX6967 is never connecting SCLK inputs together, and providing an
high impedance. Go to www.maxim-ic.com/an1879 for individual CS per MAX6966/MAX6967 device (Figure
ways to convert the MAX6966/MAX6967 to tri-state, 8). This connection works regardless of the configura-
if required. tion of DOUT/OSC, but does not allow the MAX6966/
SCLK and DIN can be used to transmit data to other MAX6967s to be read.
peripherals. The MAX6966/MAX6967 ignore all activity
on SCLK and DIN except when CS is low.
Table 11. Serial-Data Format

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R/W MSB ADDRESS LSB MSB DATA LSB
CS3
CS2
µC
CS1 CS1 CS2 CS3
MAX6966 MAX6966 MAX6966
MAX6967 DIN
MAX6967 DIN
MAX6967
MOSI DIN
SCLK SCLK SCLK SCLK
Figure 8. MAX6966/MAX6967 Multiple CS Connection
______________________________________________________________________________________ 21
Alternatively, the MAX6966/MAX6967s can be daisy- ed together. For daisy-chaining to work, DOUT/OSC
MAX6966/MAX6967
chained by connecting the DOUT of one device to the must be configured as DOUT by clearing configuration
DIN of the next, and driving SCLK and CS lines in paral- register bit D7 to zero (Table 4). Note that the MAX6966
lel (Figure 9). This connection allows the MAX6966/ powers up with DOUT/OSC configured as DOUT output
MAX6967s to be read. Data at DIN propagates through by default, while the MAX6967 powers up with
the internal shift registers and appears at DOUT 15.5 DOUT/OSC configured as OSC input by default. The
clock cycles later, clocked out on the falling edge of serial-interface speed (maximum SCLK) is limited to
SCLK. When sending commands to daisy-chained 17.5MHz when multiple devices are daisy-chained due
MAX6966/MAX6967s, all devices are accessed at the to the DOUT propagation delay and DIN setup time.
same time. An access requires (16 x n) clock cycles, Figure 10 is the timing diagram.
where n is the number of MAX6966/MAX6967s connect-
MOSI DIN DOUT DIN DOUT DIN DOUT
CS CS CS CS
MAX6966 MAX6966 MAX6966
µC SCLK SCLK MAX6967 SCLK MAX6967 SCLK MAX6967
MISO
Figure 9. MAX6966/MAX6967 Daisy-Chain Connection
CS
tCSW
tCL tCSH
tCSS tCH tCP
SCLK
tDS
tDH
DIN D15 D14 D1 D0
tDO
DOUT D15
Figure 10. Timing Diagram
22 ______________________________________________________________________________________
The MAX6966/MAX6967 are written to using the follow- Reading Device Registers
MAX6966/MAX6967
ing sequence (Figure 11): Any register data within the MAX6966/MAX6967 can be
1) Take SCLK low. read by sending a logic high to bit D15. The sequence is:
2) Take CS low. This enables the internal 16-bit shift reg- 1) Take SCLK low.
ister. 2) Take CS low. This enables the internal 16-bit shift
3) Clock 16 bits of data into DIN, D15 first to D0 last, register.
observing the setup and hold times. Bit D15 is low, 3) Clock 16 bits of data into DIN, D15 first to D0 last.
indicating a write command. D15 is high, indicating a read command and bits
4) Take CS high (either while SCLK is still high after D14 through D8 contain the address of the register
clocking in the last data bit, or after taking SCLK to read. Bits D7 to D0 contain dummy data, which is
low). discarded.
5) Take SCLK low (if not already low). 4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
If fewer or greater than 16 bits are clocked into the low). Positions D7 through D0 in the shift register are
MAX6966/MAX6967 between taking CS low and taking now loaded with the register data addressed by bits
CS high again, the MAX6966/MAX6967 store the last 16 D15 through D8.
bits received, including the previous transmission(s).
The general case is when n bits (where n > 16) are 5) Take SCLK low (if not already low).
transmitted to the MAX6966/MAX6967. The last bits 6) Issue another read or write command, and examine
comprising bits {n-15} to {n}, are retained, and are par- the bit stream at DOUT; the second 8 bits are the
allel loaded into the 16-bit latch as bits D15 to D0, contents of the register addressed by bits D14
respectively (Figure 12). through D8 in step 3).
CS
SCLK
DIN D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
=0
DOUT D15 = 0
.
Figure 11. 16-Bit Write Transmission to the MAX6966/MAX6967
CS
SCLK
DIN BIT BIT N-15 N-14 N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N
1 2
DOUT N-31 N-30 N-29 N-28 N-27 N-26 N-25 N-24 N-23 N-22 N-21 N-20 N-19 N-18 N-17 N-16
.
Figure 12. Transmission of More than 16 Bits to the MAX6966/MAX6967
______________________________________________________________________________________ 23
Applications Information In most applications, the software can be written so that
MAX6966/MAX6967
either MAX6966 or MAX6967 can be fitted, and

Hot Insertion DOUT/OSC is configured appropriately on power-up. If
The I/O ports P0–P9 remain high impedance with up to DOUT/OSC is used as OSC, fit a series resistor
8V asserted on them when the MAX6966/MAX6967 are between the PWM clock source and DOUT/OSC pin. A
powered down (V+ = 0V). The MAX6966/MAX6967 can resistor value of 2.2kΩ is recommended as a starting
therefore be used in hot-swap applications. point, but other values may be more suitable depend-
ing on the serial-interface speed and clock-source
SPI Routing Considerations drive capability. This limits the loading on the PWM
The MAX6966/MAX6967s’ SPI interface is guaranteed to clock source on power-up when a MAX6966 is fitted,
operate at 26Mbps on a 2.5V supply, and on a 3.3V sup- because DOUT/OSC initializes as an output. If
ply typically operate at 35Mbps. This means that trans- DOUT/OSC is used as DOUT, remember that a
mission-line issues should be considered when the MAX6967 cannot be read after power-up until
interface connections are longer than 100mm, particular- DOUT/OSC has been reconfigured from OSC to DOUT.
ly with higher supply voltages. Avoid running long adja-
cent tracks for SCLK, DIN, and CS without interleaving Driving LEDs into Brownout
GND traces; otherwise, the signals may cross-couple, The MAX6966/MAX6967 correctly regulate the con-
giving false clock or chip-select transitions. Ringing may stant-current outputs, provided there is a minimum volt-
manifest itself as communication issues, often intermit- age drop across the port output. This port output
tent, typically due to double clocking due to ringing at voltage is the difference between the load (typically
the SCLK input. Fit a 1kΩ to 10kΩ parallel termination LED) supply and the load voltage drop (LED forward
resistor to either GND or V+ at the DIN, SCLK, and CS voltage). If the LED supply drops so that the minimum
inputs to damp ringing for moderately long interface port output voltage is not maintained, the driver output
runs. Use line-impedance matching terminations when stages brownout and the load current falls. The mini-
making connections between boards. mum port voltage is approximately 0.5V at 10mA sink
current, and approximately 1V at 20mA sink current.
Differences Between the MAX6966 and
MAX6967 In battery applications, it may be important to operate
The MAX6966 powers up with DOUT/OSC configured the LEDs directly from a battery supply. For example,
as DOUT output by default. The MAX6967 powers up the LED supply voltage could be a single rechargeable
with DOUT/OSC configured as OSC input by default. Li+ battery with a maximum terminal voltage of 4.2V on
Both parts allow the DOUT/OSC pin function to be charge, 3.4V to 3.7V most of the time, and down to 3V
changed through the configuration register (Table 4). If when discharged. In this scenario, the LED supply falls
any port is used as a logic input, then configure significantly below the brownout point when the battery
DOUT/OSC as DOUT to allow the MAX6966/MAX6967 is at end-of-life voltage.
to be read.
24 ______________________________________________________________________________________
Figure 13 shows the typical current sunk by a LITEON Using Stagger with Fewer Ports
MAX6966/MAX6967
LTST-C170TBKT 3.0V blue LED as the LED supply volt- The stagger option, when selected, applies to all ports
age is varied from 2.5V to 7V. The LED currents shown configured as constant-current outputs. The 10 ports’
are for ports programmed for 10mA and 20mA constant PWM cycles are separated to eight evenly spaced start
current, swept over a 2.5V to 7V LED supply voltage positions (Figure 3). This phasing can be optimized if
range. It can be seen that the LED forward voltage falls fewer than 10 ports are used as constant-current out-
with current, allowing the LED current to fall gracefully, puts by allocating the ports with the most appropriate
not abruptly, in brownout. In practice, the LED current start positions. If eight constant-current outputs are
drops to 6mA to 7mA at a 3V LED supply voltage, needed, choose P0–P7 because these all have differ-
which is an acceptable performance at end-of-life in ent PWM start positions. If four constant-current outputs
many backlight applications. are needed, choose P0, P2, P4, P6 or P1, P3, P5, P7
Output Level Translation because the PWM start positions are evenly spaced. In
general, choose the ports that spread the PWM start
The open-drain output architecture allows the ports to positions as evenly as possible. This optimally spreads
level translate the outputs to higher or lower voltages out the current demand from the ports’ load supply.
than the MAX6966/MAX6967 supply. An external pullup
resistor can be used on any output to convert the high- Generating a Shutdown/Run Output
impedance logic-high condition to a positive voltage An I/O port can be used to automatically generate a
level. The resistor can be connected to any voltage up shutdown/run output from the MAX6966/MAX6967. The
to 7V. When using a pullup on a constant-current out- shutdown/run output is active low when the
put, select the resistor value to sink no more than a few MAX6966/MAX6967 are in run mode, hold-off, fade-off,
hundred µA in logic-low condition. This ensures that the or ramp-up, and go high automatically when the
current sink output saturates close to GND. For inter- MAX6966/MAX6967 finally enter shutdown after fade-
facing CMOS inputs, a pullup resistor value of 220kΩ is off. Program the port’s output register to value 0x00,
a good starting point. Use a lower resistance to which puts the output into static constant-current mode
improve noise immunity in applications where power (Table 6). Program the port’s output current register to
consumption is less critical, or where a faster rise time half current (Table 7) to minimize operating current. Fit
is needed for a given capacitive load. a 220kΩ pullup resistor to this port.
VLED vs. VLED SUPPLY ILED vs. VLED SUPPLY

3.05
20
3.00
18
2.95
16
2.90
14
2.85
ILED (mA)
VLED (V)
12
2.80
2.75 10
2.70 8
2.65 6
2.60 4
2.55 2
2.50 0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VLED SUPPLY (V) VLED SUPPLY (V)
Figure 13. LED Brownout
______________________________________________________________________________________ 25
In run mode, the output port goes low, approaching 0V, be driven using ports P0, P1, P2, and P3 connected in
MAX6966/MAX6967
as the port’s static constant current saturates trying to parallel (shorted together). Three of the ports should be
sink a higher current than the 220kΩ pullup resistor configured for full current (20mA), and the last port
can source. should be configured for half current (10mA) to meet
In shutdown mode, the output goes high impedance the 70mA requirement. The four ports can be controlled
together with any other constant-current outputs. This simultaneously with one write access using register
output remains low during ramp-up and fade-down 0x0B (Table 6). Note that because the output ports
sequences because the current drawn by the 220kΩ have current limiting, they do not have to be switched
pullup resistor is much smaller than the available output simultaneously to ensure safe current sharing.
constant current, even at the lowest fade current step. Power-Supply Considerations
Driving Load Currents Higher than 20mA The MAX6966/MAX6967 operate with a power-supply
The MAX6966/MAX6967 can be used to drive loads voltage of 2.25V to 3.6V. Bypass the power supply to
needing more than 20mA, like high-current white LEDs, GND with a 0.1µF ceramic capacitor as close to the
by paralleling outputs. For example, consider a white device as possible. For the TQFN version, connect the
LED that needs to be driven with 70mA. This LED can underside exposed pad to GND.
Typical Application Circuit

+3.3V
+5V +5V +5V

D1 D2 D3
V+
µC
MAX6966 P0
SCLK SCLK P1
P2
MOSI DIN P3
MISO DOUT P4
P5
CS CS P6
P7
P8
P9 LOGIC INPUT
GND
Pin Configurations
DOUT/OSC
TOP VIEW
P9
P8
P7
SCLK 1 16 V+
12 11 10 9
CS 2 15 DIN
DIN 13 8 P6 P0 3 14 DOUT/OSC
V+ 14 7 P5 P1 4 MAX6966ATE 13 P9
MAX6966ATE MAX6967ATE
SCLK 15 MAX6967ATE 6 GND P2 5 12 P8
CS 16 5 P4 P3 6 11 P7
P4 7 10 P6
1 2 3 4
GND 8 9 P5
P0
P1
P2
P3
THIN QFN QSOP
26 ______________________________________________________________________________________
Block Diagram
MAX6966/MAX6967
RAMP-UP/RAMP-DOWN
CURRENT REFERENCE CONTROLS
P0
P1
INTERNAL PWM CONTROLLER
OSCILLATOR P2
I/O PORTS P3
P4
P5
P6
OSC EXTERNAL CLOCK INPUT P7
P8
P9
CONFIGURATION
REGISTER I/O REGISTER
CLK
CS
DIN 4-WIRE SERIAL INTERFACE
DOUT
Chip Information
TRANSISTOR COUNT: 14,865
PROCESS: BiCMOS
______________________________________________________________________________________ 27
Package Information
MAX6966/MAX6967
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055 F 1
28 ______________________________________________________________________________________
Package Information (continued)
MAX6966/MAX6967
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS

(NE - 1) X e
MARKING E
E/2
D2/2
(ND - 1) X e
D/2 AAAA e
D CL D2
k
b 0.10 M C A B
CL
L E2/2
E2
C
L C
L
0.10 C 0.08 C
A
A2
A1 L L
e e
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
1
21-0136 I 2
PKG 8L 3x3 12L 3x3 16L 3x3

EXPOSED PAD VARIATIONS
REF. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
PKG. D2 E2
A 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 CODES PIN ID JEDEC
MIN. NOM. MAX. MIN. NOM. MAX.
b 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30
TQ833-1 0.25 0.70 1.25 0.25 0.70 1.25 0.35 x 45° WEEC
D 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 1.25
T1233-1 0.95 1.10 0.95 1.10 1.25 0.35 x 45° WEED-1
E 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10
T1233-3 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-1
e 0.65 BSC. 0.50 BSC. 0.50 BSC.
T1233-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-1
L 0.35 0.55 0.75 0.45 0.55 0.65 0.30 0.40 0.50
T1633-2 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2
N 8 12 16
T1633F-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45° WEED-2
ND 2 3 4
T1633FH-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45° WEED-2
NE 2 3 4
T1633-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2
A1 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05
A2 0.20 REF 0.20 REF 0.20 REF T1633-5 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2
k 0.25 - - 0.25 - - 0.25 - -
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
12. WARPAGE NOT TO EXCEED 0.10mm.
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
2
21-0136 I 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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19-3487; Rev 2; 4/05

10-Port Constant-Current LED Drivers and I/O

LCD Backlights RGB LED Drivers

SPI and QSPI are trademarks of Motorola, Inc.

________________________________________________________________ Maxim Integrated Products 1

Voltage (with respect to GND) Continuous Power Dissipation

Standby Current TA = +25°C 0.7 1.5

Supply-Current Interface Only TA = +25°C 390 620

Delta Supply Current per 10mA

Port Nominal Sink Constant Output register set to 19.3 20 21.1

STANDBY CURRENT (ISTBY1) SUPPLY CURRENT (I+) OUTPUT SINKING CURRENT

OUTPUT SINKING CURRENT (mA)

SUPPLY CURRENT (mA)

OUTPUT SINKING CURRENT INTERNAL OSCILLATOR FREQUENCY

STAGGER PWM PORT WAVEFORMS

I/O Ports. P0 to P9 can be configured as open-drain current-sink outputs rated at 20mA

Table 1. Port Configuration Options

Logic-high output with external pullup resistor; otherwise, high

Figure 1. Simplified Schematic of I/O Ports

Table 2. Register Address Map

Table 3. Initial Power-Up Register Status

Figure 2. Static and PWM Constant-Current Waveforms

0 32 64 96 128 160 192 224 256

Figure 3. Staggered PWM Waveform

MAX6966/MAX6967 are in shutdown. If not, there may be PWM Intensity Control

Table 5. Input Ports Register

Port P1 level or PWM X 0x01 MSB Port P1 level or PWM LSB

Table 7. Output Current Register Format

ADDRESS REGISTER DATA

Global Current Register ZERO TO 4s CURRENT RAMP-UP AFTER CS RUN

ZERO TO 8s CURRENT RAMP-DOWN

1/4s 1/2s 1s 2s 4s 1/4s 1/2s 1s 2s 4s

Figure 5. Ramp-Down, Hold-Off, and Fade-Off Behavior

Table 9. Ramp-Down Register Format

Fade-off time (fPWM = 32768Hz)

Hold-off time (fPWM = 32768Hz)

ADDRESS REGISTER DATA

CURRENT GLOBAL CURRENT = 0x07

PORT CURRENT = HALF

GLOBAL CURRENT = 0x02

2.5mA GLOBAL CURRENT = 0x00

Table 11. Serial-Data Format

SCLK SCLK SCLK SCLK

Figure 8. MAX6966/MAX6967 Multiple CS Connection

MOSI DIN DOUT DIN DOUT DIN DOUT

Figure 9. MAX6966/MAX6967 Daisy-Chain Connection

DIN D15 D14 D1 D0

Figure 10. Timing Diagram

Figure 11. 16-Bit Write Transmission to the MAX6966/MAX6967

Figure 12. Transmission of More than 16 Bits to the MAX6966/MAX6967

either MAX6966 or MAX6967 can be fitted, and

VLED vs. VLED SUPPLY ILED vs. VLED SUPPLY

Figure 13. LED Brownout

Typical Application Circuit

+5V +5V +5V

THIN QFN QSOP

12x16L QFN THIN.EPS

PKG 8L 3x3 12L 3x3 16L 3x3

k 0.25 - - 0.25 - - 0.25 - -