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Experiment # 2 (Basic Logic Gates) at Proteus

This experiment involves verifying the truth tables of basic logic gates (AND, OR, NOT, NAND, NOR, XOR) using integrated circuits in Proteus software. Equipment like 7404, 7408, 7432, 7400, 7402 and 7486 ICs and connecting wires are used to build circuits for each gate. The document provides background on logic states and gate symbols. It includes the procedure of building circuits in Proteus, applying all input combinations and observing outputs to complete truth tables for each gate.

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Umer Farooq
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0% found this document useful (0 votes)
1K views

Experiment # 2 (Basic Logic Gates) at Proteus

This experiment involves verifying the truth tables of basic logic gates (AND, OR, NOT, NAND, NOR, XOR) using integrated circuits in Proteus software. Equipment like 7404, 7408, 7432, 7400, 7402 and 7486 ICs and connecting wires are used to build circuits for each gate. The document provides background on logic states and gate symbols. It includes the procedure of building circuits in Proteus, applying all input combinations and observing outputs to complete truth tables for each gate.

Uploaded by

Umer Farooq
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment # 2

Verification of Truth Tables of Logic Gates (AND, OR, NOT), &


(NAND, NOR, XOR)

Objectives:
 To become familiar with the operation of Basic Gates, AND, OR, NOT, NAND, NOR,
XOR using ICs.
 To become familiar how to determine the truth tables for logic gates

Equipment Required:
 Ptroteus 8 professional
 7404 hex NOT (Inverter) gate IC
 7408 quad 2-input AND gate IC
 7432 quad 2-input OR gate IC
 7400 quad 2-input NAND gate IC
 7402 quad 2-input NOR gate IC
 7486 quad 2-input XOR gate IC
 Connecting Wires

Background Theory
Logic deals with only two normal conditions: logic TURE or logic FALSE. In Boolean
logic, TRUE is often represented by the term HIGH or the number 1 and FALSE is
represented by the term LOW or the number 0. HIGH and LOW (1 or 0) are logic terms;
they do not indicate whether the voltage is higher or lower. In positive logic the more
positive voltage is TRUE and the less positive voltage is FALSE i.e +2.5V = HIGH and
+0.5V = LOW. With the negative logic this definition is reversed.

The basic logic gates and their symbols are summarized in the following pages. The
truth table with all possible input combination is given and the output is left empty to you
as an exercise. All possible combination of inputs involve counting in binary from 0 to 2 n
– 1 where n is the number of inputs.

In this experiment you will look at the truth tables for several arrangements of simple
gates.

1
GATES, THEIR IC PIN CONFIGURATION & TRUTH TABLES:

Vcc 14 13 12 11 10 9 8
NOT Gate

X 1
A1
1
A1 Y

1 2 3 4 5 6 7
GND
NOT Gate (Hex Inverter) 7404

2-Input AND Gate Vcc 14 13 12 11 10 9 8

X
Z
Y

1 2 3 4 5 6 7 GND
Quad 2-input AND gate 7408

Vcc 14 13 12 11 10 9 8
2-Input OR Gate

X
Z
Y
1 2 3 4 5 6 7 GND
Quad 2-input OR gate 7432

2
2 Input NAND Gate
Vcc 14 13 12 11 10 9 8

X
Z
Y

1 2 3 4 5 6 7
GND
Quad 2-input NAND gate 7400

2 Input NOR
Vcc 14 13 12 11 10 9 8

X
Z
Y

1 2 3 4 5 6 7
GND
Quad 2-input NOR gate 7402

2 Input XOR
Vcc 14 13 12 11 10 9 8

X
Z
Y

1 2 3 4 5 6 7 GND

Quad 2-input XOR gate 7486

3
Procedure
1. Open the software and select new project from the menu.
2. Select the components required in the circuit from the search box.
3. Click the specific component, it will be added in your list.
4. To add the component double click it and bring it in its exact position.
5. Now make connections using wires as required.
6. Apply all the combinations of inputs / Logic state and observe the output on the
Logic probe / LED to verify the truth tables of the logic gates.

Truth Table
Record the results by filling the table below:

Input Output

X Y X‘ XY X+Y

0 0

0 1

1 0

1 1

4
Truth Table

Record the results by filling the table below:

Input Output

X Y (XY)’ (X+Y)’ X (xor) Y

0 0

0 1

1 0

1 1

Conclusion:

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