DATASHEET

ISL28191, ISL28291 FN6156

Single and Dual Single Supply Ultra-Low Noise, Low Distortion Rail-to-Rail Rev 10.00
Output, Op Amp July 22, 2014

The ISL28191 and ISL28291 are tiny single and dual ultra-low
noise, ultra-low distortion operational amplifiers. They are fully
Features
specified to operate down to +3V single supply. These • 1.7nV/√Hz input voltage noise at 1kHz
amplifiers have outputs that swing rail-to-rail and an input • 1kHz THD+N typical 0.00018% at 2VP-P VOUT
common mode voltage that extends to ground
• Harmonic Distortion -76dBc, -70dBc, fo = 1MHz
(ground sensing).
• 61MHz -3dB bandwidth
The ISL28191 and ISL28291 are unity gain stable with an
input referred voltage noise of 1.7nV/Hz. Both parts feature • 630µV maximum offset voltage
0.00018% THD+N at 1kHz. • 3µA input bias current
The ISL28191 is available in the space-saving 6 Ld UTDFN • 100dB typical CMRR
(1.6mmx1.6mm) and 6 Ld SOT-23 packages. The ISL28291 is • 3V to 5.5V single supply voltage range
available in the 8 Ld SOIC, 10 Ld 1.8mmx1.4mm UTQFN and
10 Ld MSOP packages. All devices are guaranteed over -40°C • Rail-to-rail output
to +125°C. • Ground Sensing

Ordering Information • Enable pin (not available in the 8 Ld SOIC package option)
• Pb-free (RoHS compliant)
PART NUMBER PART PACKAGE PKG.
(Note 5) MARKING (Pb-free) DWG. #
Applications
ISL28191FHZ-T7 (Notes 1, 2) GABJ 6 Ld SOT-23 P6.064A
(Note 4)
• Low noise signal processing

ISL28191FRUZ-T7 (Notes 1, 3) M8 6 Ld UTDFN L6.1.6x1.6A • Low noise microphones/preamplifiers

ISL28291FUZ (Note 2) 8291Z 10 Ld MSOP M10.118A • ADC buffers
ISL28291FUZ-T7 (Notes 1, 2) 8291Z 10 Ld MSOP M10.118A • DAC output amplifiers
ISL28291FBZ (Note 2) 28291 FBZ 8 Ld SOIC M8.15E • Digital scales
ISL28291FBZ-T7 (Notes 1, 2) 28291 FBZ 8 Ld SOIC M8.15E • Strain gauges/sensor amplifiers
ISL28291FRUZ-T7 (Notes 1, 3) F 10 Ld UTQFN L10.1.8x1.4A • Radio systems
ISL28191EVAL1Z Evaluation Board • Portable equipment
ISL28291EVAL1Z Evaluation Board • Infrared detectors
NOTES:
1. Please refer to TB347 for details on reel specifications. Related Literature
2. These Intersil Pb-free plastic packaged products employ special Pb- • AN1343: ISL2829xEVAL1Z, ISL5529xEVAL1Z Evaluation
free material sets, molding compounds/die attach materials, and Board User’s Guide
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-
free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
4. The part marking is located on the bottom of the part.
5. For Moisture Sensitivity Level (MSL), please see device information
page for ISL28191, ISL28291. For more information on MSL please
see techbrief TB363.

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ISL28191, ISL28291

Pin Configurations
ISL28191 ISL28191
(6 LD SOT-23) (6 LD 1.6X1.6X0.5 UTDFN)
TOP VIEW TOP VIEW

OUT 1 6 V+ OUT 1 6 V+

V- 2 5 EN IN- 2 5 EN
+ -

- +
IN+ 3 4 IN- IN+ 3 4 V-

ISL28291 ISL28291
(8 LD SOIC) (10 LD MSOP)
TOP VIEW TOP VIEW

OUT_A 1 8 V+ OUT_A 1 10 V+

IN-_A 2 7 OUT_B IN-_A 2 9 OUT_B

- -
+ +
IN+_A 3 6 IN-_B IN+_A 3 8 IN-_B
- -
+ +
V- 4 5 IN+_B V- 4 7 IN+_B

EN_A 5 6 EN_B

ISL28291
(10 LD UTQFN)
TOP VIEW
OUT_A

OUT_B
V+

10 9 8

IN-_A 1 7 IN-_B
- -
+ +
IN+_A 2 6 IN+_B

3 4 5
V-

EN_A

EN_B

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Pin Descriptions
ISL28191 ISL28191 ISL28291 ISL28291 ISL28291 PIN
(6 Ld SOT-23) (6 Ld UTDFN) (8 Ld SOIC) (10 Ld MSOP) (10 Ld UTQFN) NAME FUNCTION EQUIVALENT CIRCUIT
4 2 IN- Inverting input V+
2 (A) 2 (A) 1 (A) IN-_A
6 (B) 8 (B) 7 (B) IN-_B

IN- IN+

V-
Circuit 1

3 3 IN+ Non-inverting (See circuit 1)

3 (A) 3 (A) 2 (A) IN+_B input
5 (B) 7 (B) 6 (B) IN+_B
2 4 4 4 3 V- Negative supply
1 1 OUT Output V+
1 (A) 1 (A) 10 (A) OUT_A
7 (B) 9 (B) 8 (B) OUT_B
OUT

V-
Circuit 2

6 6 8 10 9 V+ Positive supply
5 5 N/A EN Enable BAR V+
5 (A) 4 (A) EN_A pin internal
6 (B) 5 (B) EN_B pull-down; Logic
“1” selects the EN
disabled state;
Logic “0” selects V-
the enabled
state. Circuit 3

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Absolute Maximum Ratings (TA = +25°C) Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs 6 Ld SOT-23 Package (Notes 6, 9) . . . . . . . 170 105
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA 6 Ld UTDFN Package (Notes 7, 8) . . . . . . . 125 80
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V 8 Ld SOIC Package (Notes 6, 9) . . . . . . . . . 110 82
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V 10 Ld MSOP Package (Notes 6, 9) . . . . . . . 175 90
ESD Tolerance 10 Ld UTQFN Package (Notes 6, 9) . . . . . . 190 140
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200V http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.

NOTE:
6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
9. For JC, the “case temp” location is taken at the package top center.

Electrical Specifications V+ = 5.0V, V- = GND, RL = Open RF = 1kAV = -1unless otherwise specified. Parameters are per amplifier.
Typical values are at V+= 5V, TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C.
MIN MAX
PARAMETER DESCRIPTION CONDITIONS (Note 10) TYP (Note 10) UNIT
DC SPECIFICATIONS
VOS Input Offset Voltage 270 630 µV
840
V OS Input Offset Drift vs Temperature Figure 21 3.1 µV/°C
---------------
-
T
IIO Input Offset Current 35 500 nA
900
IB Input Bias Current 3 6 µA
7
CMIR Common-Mode Input Range 0 3.8 V
CMRR Common-Mode Rejection Ratio VCM = 0V to 3.8V 78 100 dB
PSRR Power Supply Rejection Ratio VS = 3V to 5V 74 80 dB
AVOL Large Signal Voltage Gain VO = 0.5V to 4V, RL = 1k 90 98 dB
86
VOUT Maximum Output Voltage Swing Output low, RL = 1k 20 50 mV
80
Output high, RL = 1kV+ = 5V 4.95 4.97 V
4.92
IS,ON Supply Current per Amplifier, Enabled 2.6 3.5 mA
3.9
IS,OFF Supply Current per Amplifier, Disabled 26 35 µA
48
IO+ Short-Circuit Output Current RL = 10 95 130 mA
90

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ISL28191, ISL28291

Electrical Specifications V+ = 5.0V, V- = GND, RL = Open RF = 1kAV = -1unless otherwise specified. Parameters are per amplifier.
Typical values are at V+= 5V, TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN MAX
PARAMETER DESCRIPTION CONDITIONS (Note 10) TYP (Note 10) UNIT
IO- Short-Circuit Output Current RL = 10 95 130 mA
90
VSUPPLY Supply Operating Range V+ to V- 3 5.5 V
VENH EN High Level Referred to V- 2 V
VENL EN Low Level Referred to V- 0.8 V
IENH EN Pin Input High Current VEN = V+ 0.8 1.1 µA
1.3
IENL EN Pin Input Low Current VEN = V- 20 80 nA
100
AC SPECIFICATIONS
GBW -3dB Unity Gain Bandwidth RF = 0 CL = 20pF, AV = 1, RL = 10k 61 MHz
THD+N Total Harmonic Distortion + Noise f = 1kHz. VOUT + 2VP-P, AV = +1, RL = 10k 0.0001 %
8
HD 2nd Harmonic Distortion 2VP-P output voltage, AV = 1 -76 dBc
(1MHz)
3rd Harmonic Distortion -70 dBc
ISO Off-state Isolation AV = +1, VIN = 100mVP-P, RF = 0 -38 dB
fO = 100kHz CL = 20pF, AV = 1, RL = 10k
X-TALK Channel-to-Channel Crosstalk VS = ±2.5V, AV = +1, VIN = 1VP-P, -105 dB
ISL28291 fO = 100kHz RF = 0CL = 20pF, AV = 1, RL = 10k
PSRR Power Supply Rejection Ratio VS = ±2.5V, AV = +1, VSOURCE = 1VP-P, -70 dB
fO = 100kHz RF = 0CL = 20pF, AV = 1, RL = 10k
CMRR Common Mode Rejection Ratio VS = ±2.5V, AV = +1, VCM = 1VP-P, -65 dB
fO = 100kHz RF = 0CL = 20pF, AV = 1, RL = 10k
en Input Referred Voltage Noise fO = 1kHz 1.7 nV/√Hz
in Input Referred Current Noise fO = 1kHz 1.8 pA/√Hz
TRANSIENT RESPONSE
SR Slew Rate 12 17 V/µs
12
tr, tf, Small Rise Time, tr 10% to 90% AV = 1, VOUT = 0.1VP-P, RL = 10k, CL = 1.2pF 7 ns
Signal
Fall Time, tf 90% to 10% 12 ns
tr, tf Large Signal Rise Time, tr 10% to 90% AV = 2, VOUT = 1VP-P; RL = 10k 44 ns
RF /RG = 499499CL = 1.2pF
Fall Time, tf 90% to 10% 50 ns
Rise Time, tr 10% to 90% AV = 2, VOUT = 4.7VP-P; RL = 10k 190 ns
Fall Time, tf 90% to 10% RF /RG = 499499CL = 1.2pF 190 ns
tEN ENABLE to Output Turn-on Delay Time; AV = 1, VOUT = 1VDC, RL = 10k, CL = 1.2pF 330 ns
10% EN - 10% VOUT
ENABLE to Output Turn-off Delay Time; AV = 1, VOUT = 0VDC, RL = 10k, CL = 1.2pF 50 ns
10% EN - 10% VOUT
NOTE:
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

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ISL28191, ISL28291

Typical Performance Curves

3 10
RL = 100k CL = 110pF
2 8

1 6
CLOSED LOOP GAIN (dB)

CLOSED LOOP GAIN (dB)

CL = 57pF
0 4 CL = 57pF
-1 2
CL = 32pF
-2 RL = 10k 0

-3 -2 CL = 10pF
CL = 20pF
-4 V+ = 5V RL = 1k -4
V+ = 5V
-5 AV = +1 -6 AV = +1
CL = 10pF RL = 100 RL = 10k
-6 VOUT = 10mVP-P -8 VOUT = 10mVP-P
-7 -10
10k 100k 1M 10M 100M 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD

2 70
VOUT = 1mVP-P
1 AV = 1000, RF = 499k, RG = 499 V+ = 5V
VOUT = 10mVP-P 60 RL = 10k
0
CLOSED LOOP GAIN (dB)

50 VOUT = 100mVP-P
-1
-2 VOUT = 100mVP-P GAIN (dB) 40
AV = 100, RF = 49.9k,
-3 30
RG = 499
-4 VOUT = 1VP-P 20
-5 AV = 10, RF = 4.42k, RG = 499
V+ = 5V 10
-6 AV = +1
RL = 10k
-7 0
CL = 10pF AV = 1, RF = 0, RG = INF
-8 -10
10k 100k 1M 10M 100M 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 3. -3dB BANDWIDTH vs VOUT FIGURE 4. FREQUENCY RESPONSE vs CLOSED LOOP GAIN

1M 100k
OUTPUT IMPEDANCE ()
INPUT IMPEDANCE ()

100k
V+ = 5V, 3V 10k V+ = 5V, 3V
ENABLED AND
DISABLED VSOURCE = 1VP-P
10k
VSOURCE = 1VP-P

1k
1k

100 100
10k 100k 1M 10M 100M 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 5. INPUT IMPEDANCE vs FREQUENCY FIGURE 6. DISABLED OUTPUT IMPEDANCE vs FREQUENCY

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ISL28191, ISL28291

Typical Performance Curves (Continued)

100 10
V+ = 5V, 3V
0
-10
OUTPUT IMPEDANCE ()

VSOURCE = 1V -20
10
-30

CMRR (dB)
-40
-50
VSOURCE = 0.1V
1 -60 V+ = 5V
-70 AV = +1
RL = 10k
-80 CL = 10pF
-90 VOUT = 100mVP-P
0.10 -100
10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 7. ENABLED OUTPUT IMPEDANCE vs FREQUENCY FIGURE 8. CMRR vs FREQUENCY

10 0
V+ = 5V
0 AV = +1 -10 VP-P = 1V
-10 RL = 10k
CL = 10pF -20 VP-P = 10mV

OFF ISOLATION (dB)

-20 VOUT = 100mVP-P
-30 -30 VP-P = 100mV
PSRR (dB)

-40 PSRR+ -40

-50
-50
-60
PSRR+
PSRR-
-70 -60 V+ = 5V
AV = +1
-80 RL = 10k
-70
-90 CL = 10pF
-100 -80
1k 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 9. PSRR vs FREQUENCY FIGURE 10. OFF ISOLATION vs FREQUENCY

-30 0.1
V+ = 5V
-40
RL = 10k
-50 RF = 0, AV = 1
VOUT = 2VP-P
CROSSTALK (dB)

THD + NOISE (%)

-60 0.01
400Hz TO 22kHz FILTER
-70
VP-P = 1V
-80

-90 0.001

-100

-110

-120 0.0001
10k 100k 1M 10M 100M 1G 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k
FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 11. CHANNEL TO CHANNEL CROSSTALK vs FREQUENCY FIGURE 12. THD+N vs FREQUENCY

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ISL28191, ISL28291

Typical Performance Curves (Continued)

1 10
V+ = 5V

INPUT VOLTAGE NOISE (nV/ÖHz)

AV = +1
RL = 10k
0.1 FREQUENCY = 1kHz
FILTER = 400Hz TO 22kHz
THD +NOISE (%)

0.01

0.001

0.0001 1
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.1 1 10 100 1k 10k 100k
VOUT (VP-P) FREQUENCY (Hz)

FIGURE 13. THD+N @ 1kHz vs VOUT FIGURE 14. INPUT REFERRED NOISE VOLTAGE vs FREQUENCY

100 5
V+ = 5V
AV = +1
EN INPUT
CURRENT NOISE (pA/Hz)

4 RL = 10k
CL = 10pF
VIN = 1VDC
VOLTS (V)

3
10
2
ENABLE DISABLE ENABLE

OUTPUT
1 0
0.1 1 10 100 1k 10k 100k -1 0 1 2 3 4
FREQUENCY (Hz) TIME (µs)

FIGURE 15. INPUT REFERRED NOISE CURRENT vs FREQUENCY FIGURE 16. ENABLE/DISABLE TIMING

0.08 0.8

0.06 0.6 VOUT

0.04 VOUT
LARGE SIGNAL (V)

0.4
SMALL SIGNAL (V)

VIN
0.02 0.2
VIN
0 0

-0.02 -0.2
V+ = ±2.5V V+ = ±2.5V
-0.04 AV = +1 -0.4 AV = +2
RL = 10k RF = RG = 499
-0.06 VOUT = 100mVP-P -0.6 RL = 10k
VOUT = 1VP-P
-0.08 -0.8
0 20 40 60 80 100 120 140 160 180 200 0 100 200 300 400 500 600 700 800
TIME (ns) TIME (ns)

FIGURE 17. SMALL SIGNAL STEP RESPONSE FIGURE 18. LARGE SIGNAL (1V) STEP RESPONSE

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ISL28191, ISL28291

Typical Performance Curves (Continued)

3 3.5
VOUT n = 100
3.3 MAX
2
3.1 MEDIAN
VIN
LARGE SIGNAL (V)

2.9

CURRENT (mA)
1
2.7
0 2.5
2.3 MIN
-1 V+ = ±2.5V 2.1
AV = +2
RF = RG = 499 1.9
-2
RL = 10k 1.7
VOUT = 4.7VP-P
-3 1.5
0 400 800 1200 1600 2000 -40 -20 0 20 40 60 80 100 120
TIME (ns) TEMPERATURE (°C)
FIGURE 19. LARGE SIGNAL (4.7V) STEP RESPONSE FIGURE 20. SUPPLY CURRENT vs TEMPERATURE,
VS = ±2.5V ENABLED, RL = INF

800 -3.0
n = 100 n = 100
700 MAX -3.2
MAX
600
-3.4
500
-3.6
IBIAS+ (µA)
400 MEDIAN
VOS (µV)

MEDIAN
300 -3.8
200
-4.0
100 MIN
-4.2
0 MIN

-100 -4.4

-200 -4.6
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)

FIGURE 21. VOS vs TEMPERATURE, VS = ±2.5V FIGURE 22. IBIAS+ vs TEMPERATURE, VS = ±2.5V

-3.0 800
n = 100 n = 100
-3.2 MAX
600
-3.4
-3.6 MEDIAN
400 MEDIAN
IBIAS- (µA)

-3.8
IIO (nA)

-4.0 200
MIN
MAX
-4.2
-4.4 0

-4.6
-200
-4.8 MIN
-5.0 -400
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)

FIGURE 23. IBIAS- vs TEMPERATURE, VS = ±2.5V FIGURE 24. IIO vs TEMPERATURE, VS = ±2.5V

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ISL28191, ISL28291

Typical Performance Curves (Continued)

160 82
n = 100 n = 100
150 MAX
80 MAX
140
130 78
CMRR (dB)

PSRR (dB)
MEDIAN
120
76
110 MEDIAN
MIN
100 74
90
72
80 MIN
70 70
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)

FIGURE 25. CMRR vs TEMPERATURE, VCM = 3.8V, FIGURE 26. PSRR vs TEMPERATURE ±1.5V TO ±2.5V
VS = ±2.5V

4.990 60
n = 100 n = 100
55
4.985
MAX 50
45
4.980
VOUT (mV)

40
VOUT (V)

MEDIAN MAX
4.975 35
30
4.970 MEDIAN
25
20
4.965
MIN 15
MIN
4.960 10
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)

FIGURE 27. POSITIVE VOUT vs TEMPERATURE, RL = 1k VS = ±2.5V FIGURE 28. NEGATIVE VOUT vs TEMPERATURE, RL = 1k
VS = ±2.5V

1.2
VCM OVERHEAD TO SUPPLY RAILS (V)

1.0
0.8
INPUT VOLTAGE TO
0.6
THE POSITIVE RAIL (V+ - VCM)
0.4
0.2
0
-0.2
-0.4
INPUT VOLTAGE TO
-0.6
THE NEGATIVE RAIL (V- + VCM)
-0.8
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)

FIGURE 29. INPUT COMMON MODE VOLTAGE vs TEMPERATURE

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ISL28191, ISL28291

Applications Information Using Only One Channel

The ISL28291 is a dual channel op amp. If the application only
Product Description requires one channel when using the ISL28291, the user must
The ISL28191 and ISL28291 are voltage feedback operational configure the unused channel to prevent it from oscillating.
amplifiers designed for communication and imaging applications Oscillation can occur if the input and output pins are floating. This
requiring low distortion, very low voltage and current noise. Both will result in higher than expected supply currents and possible
parts feature high bandwidth while drawing moderately low supply noise injection into the channel being used. The proper way to
current. They use a classical voltage-feedback topology, which prevent this oscillation is to short the output to the negative input
allows them to be used in a variety of applications where and ground the positive input (as shown in Figure 31).
current-feedback amplifiers are not appropriate because of
restrictions placed upon the feedback element used with the
-
amplifier.
+
Enable/Power-Down
The ISL28191 and ISL28291 amplifiers are disabled by applying
a voltage greater than 2V to the EN pin, with respect to the V- pin. FIGURE 31. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
In this condition, the output(s) will be in a high impedance state
and the amplifier(s) current will be reduced to 13µA/Amp. By Power Supply Bypassing and Printed Circuit
disabling the part, multiple parts can be connected together as a Board Layout
MUX. The outputs are tied together in parallel and a channel can
As with any high frequency device, good printed circuit board
be selected by the EN pin. The EN pin also has an internal
layout is necessary for optimum performance. Low impedance
pull-down. If left open, the EN pin will pull to the negative rail and
ground plane construction is essential. Surface mount
the device will be enabled by default.
components are recommended, but if leaded components are
used, lead lengths should be as short as possible. The power
Input Protection supply pins must be well bypassed to reduce the risk of
All input terminals have internal ESD protection diodes to both oscillation. The combination of a 4.7µF tantalum capacitor in
positive and negative supply rails, limiting the input voltage to parallel with a 0.01µF capacitor has been shown to work well
within one diode beyond the supply rails. Both parts have when placed at each supply pin.
additional back-to-back diodes across the input terminals
(as shown in Figure 30). In pulse applications where the input Slew For good AC performance, parasitic capacitance should be kept
Rate exceeds the Slew Rate of the amplifier, the possibility exists to a minimum, especially at the inverting input. When ground
for the input protection diodes to become forward biased. This can plane construction is used, it should be removed from the area
cause excessive input current and distortion at the outputs. If near the inverting input to minimize any stray capacitance at that
overdriving the inputs is necessary, the external input current must node. Carbon or Metal-Film resistors are acceptable with the
never exceed 5mA. An external series resistor may be used to limit Metal-Film resistors giving slightly less peaking and bandwidth
the current, as shown in Figure 30. because of additional series inductance. Use of sockets,
particularly for the SOIC package, should be avoided if possible.
Sockets add parasitic inductance and capacitance, which will
- result in additional peaking and overshoot.
R
+
Current Limiting
The ISL28191 and ISL28291 have no internal current-limiting
circuitry. If the output is shorted, it is possible to exceed the
FIGURE 30. LIMITING THE INPUT CURRENT TO LESS THAN 5mA Absolute Maximum Rating for output current or power dissipation,
potentially resulting in the destruction of the device. This is why the
output short circuit current is specified and tested with RL = 10.

FN6156 Rev 10.00 Page 11 of 18

July 22, 2014
ISL28191, ISL28291

Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load and power-supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related in Equation 1:
T JMAX = T MAX +   JA xPD MAXTOTAL  (EQ. 1)

where:
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated in Equation 2:
V OUTMAX
PD MAX = 2*V S  I SMAX +  V S - V OUTMAX   ----------------------------
R L
(EQ. 2)

where:
• TMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Supply voltage
• IMAX = Maximum supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the application
• RL = Load resistance

FN6156 Rev 10.00 Page 12 of 18

July 22, 2014
ISL28191, ISL28291

Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.

DATE REVISION CHANGE

July 22, 2014 FN6156.10 Updated location of note references.

Updated Theta JA in the "Thermal Information" table on page 4 and added Theta JC to table.

January 18, 2012 FN6156.9 Page 1 - Ordering Information Update:

Added Eval Board ISL28191EVAL1Z
Changed micro TDFN and TQFN to Ultra matching POD Description
Added SOT-23 Note
Page 10 - Typical Performance Curves:
Added Figure 29 - INPUT COMMON MODE VOLTAGE vs TEMPERATURE

About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support

© Copyright Intersil Americas LLC 2006-2013. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

FN6156 Rev 10.00 Page 13 of 18

July 22, 2014
ISL28191, ISL28291

Package Outline Drawing

P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90

0-3°
0.95
D 0.08-0.20
A

6 5 4

PIN 1
INDEX AREA
2.80 3 1.60
3 5

0.15 C D
2x (0.60)
1 2 3 0.20 C
2x
SEE DETAIL X
B 0.40 ±0.05 3

0.20 M C A-B D
TOP VIEW END VIEW

10° TYP
5 0.15 C A-B (2 PLCS)
2.90
2x

1.14 ±0.15
1.45 MAX
C

(0.25) GAUGE
0.10 C SEATING PLANE PLANE
0.05-0.15
SIDE VIEW

DETAIL "X" 0.45±0.1 4

(0.60)

(1.20)

NOTES:
(2.40)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

3. Dimension is exclusive of mold flash, protrusions or gate burrs.

4. Foot length is measured at reference to guage plane.

5. This dimension is measured at Datum “H”.

6. Package conforms to JEDEC MO-178AA.
(0.95)

(1.90)

TYPICAL RECOMMENDED LAND PATTERN

FN6156 Rev 10.00 Page 14 of 18

July 22, 2014
ISL28191, ISL28291

Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)

A L6.1.6x1.6A
E A B 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
6 4
MILLIMETERS
SYMBOL MIN NOMINAL MAX NOTES
PIN 1 D
A 0.45 0.50 0.55 -
REFERENCE
2X 0.15 C A1 - - 0.05 -
1 3
2X 0.15 C A3 0.127 REF -
TOP VIEW A1 b 0.15 0.20 0.25 -

D 1.55 1.60 1.65 4

e
1.00 REF D2 0.40 0.45 0.50 -
4 6
L
E 1.55 1.60 1.65 4

E2 0.95 1.00 1.05 -

D2 CO.2
e 0.50 BSC -
DAP SIZE 1.30 x 0.76
L 0.25 0.30 0.35 -
3 1 b 6X
Rev. 1 6/06
E2 0.10 M C A B
NOTES:
BOTTOM VIEW 1. Dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
Coplanarity shall not exceed 0.08mm.
DETAIL A
0.10 C 3. Warpage shall not exceed 0.10mm.
4. Package length/package width are considered as special
6X 0.08 C characteristics.
5. JEDEC Reference MO-229.
A3 C 6. For additional information, to assist with the PCB Land Pattern
SEATING Design effort, see Intersil Technical Brief TB389.
SIDE VIEW
PLANE

0.127±0.008

0.127 +0.058
-0.008
TERMINAL THICKNESS

A1

DETAIL A

0.25
0.50

1.00 0.45 1.00

2.00
0.30

1.25

LAND PATTERN 6

FN6156 Rev 10.00 Page 15 of 18

July 22, 2014
ISL28191, ISL28291

Package Outline Drawing

M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09

4
4.90 ± 0.10 A
DETAIL "A" 0.22 ± 0.03

6.0 ± 0.20

3.90 ± 0.10

PIN NO.1
ID MARK

(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27

0.25 M C A B
SIDE VIEW “B”
TOP VIEW

1.75 MAX
1.45 ± 0.1

0.25
GAUGE PLANE
C
0.175 ± 0.075 SEATING PLANE
0.10 C
SIDE VIEW “A

0.63 ±0.23

DETAIL "A"
(1.27) (0.60)

NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

(5.40) 3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension does not include interlead flash or protrusions.

Interlead flash or protrusions shall not exceed 0.25mm per side.

5. The pin #1 identifier may be either a mold or mark feature.

6. Reference to JEDEC MS-012.

TYPICAL RECOMMENDED LAND PATTERN

FN6156 Rev 10.00 Page 16 of 18

July 22, 2014
ISL28191, ISL28291

Package Outline Drawing

L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 8/13

C0.10
1.80 A 6 IN #1 ID
B 9 X 0.40
1 1 2

3 10X 0.20 4
10
0.50 0.10 M C A B
6 PIN 1 0.05 M C
1.40

INDEX AREA

0.70
8
4X 0.30
0.10 5

2X 7 6
6X 0.40
TOP VIEW
BOTTOM VIEW

SEE DETAIL "X"

0.10 C
MAX. 0.55 C
2.20
SEATING PLANE
1 0.08 C
(10X 0.20)
3 10 (0.70) SIDE VIEW
1.80

8 0.127 REF
5 C

(9X 0.60) 6 7

(6X 0.40) PACKAGE OUTLINE

0-0.05

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Lead width dimension applies to the metallized terminal and is

measured between 0.15mm and 0.30mm from the terminal tip.

5. JEDEC reference MO-255.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

FN6156 Rev 10.00 Page 17 of 18

July 22, 2014
ISL28191, ISL28291

Package Outline Drawing

M10.118A (JEDEC MO-187-BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
A
3.0 ± 0.1

0.25 CAB DETAIL "X"

10

1.10 Max

SIDE VIEW 2 0.18 ± 0.05

4.9 ± 0.15
3.0 ± 0.1

PIN# 1 ID B

1 2
0.95 BSC
0.5 BSC

TOP VIEW

Gauge
Plane
H 0.86 ± 0.09 0.25

SEATING PLANE 3°±3°

0.55 ± 0.15
0.10 ± 0.05
0.23 +0.07/ -0.08 0.10 C
0.08 C A B DETAIL "X"

SIDE VIEW 1

5.80
4.40
NOTES:
3.00
1. Dimensions are in millimeters.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

0.50 3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.25mm max per side are not
0.30 included.
1.40 5. Dimensions “D” and “E1” are measured at Datum Plane “H”.

TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP0043 MSOP10L.

FN6156 Rev 10.00 Page 18 of 18

July 22, 2014
Mouser Electronics

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