/Ji,:ltu/ Circ11/ts (204 182)

Dnttnknla Group or Institution's

.4 Faculty of Engineering
Expt. No.
Department of E& TC Engineering
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- 1
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Design and implement single-d igit BCD add er using binary
Titk adder IC

i<: Study IC-74LS83 as a BCD add

er.
~
lC:.7 ALS.83.
,i rodesign and implement I digit BCD adder l!_S il}g_ 83.
1
) rodesign and implement a
4:0it binary Subtractor using IC-74LS
11

wires, IC 74LS83 , IC 74LS32, IC 74LS04.

J paratus: Digital Trainer Ki~ Connecting

J BCD adder

Theory:
uces a sum
single-digit BCD numbers and prod
BCD adder is a circuit that adds two are represented in
numbers use 10 digits, 0 to 9 which
which is also a BCD number. BCD number.
digit is represented as a 4-bit binary
binary from 0000 to I 00 I i.e. each BCD
marized as follows,
BCD addition procedures can be sum
addition.
1. Add 2 BCD numbers using binary lid. To correct
or if carry is generated, the sum is inva
2. If the 4-bit sum is greater than 9 to the next
is generated from this addition, add it
the sum , add O110 to the sum if carry
higher order BCD digit. form.
3. If the 4-bit sum is less than__9 or
equal to 9, the sum is in proper BCD

numbers , for example in the calculator.

BCD code is used to represent decimal

3
s G

D
0
D o 'll

() 0 0 0

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tp
IOo o l
1
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t bc4 1

Department of E& TC Engineering, DGO

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117
 pin Configuration of 7483 IC:

16 B3

IS S3

.A:2 r I
-,~ C4

B2 4 ,i] co
7483
Vee ., 12 GNO

S1 b ,, BO

Bl l 10 NJ

A'1 je 9 so

4-bit BCD Adder Circuit Diagram: l l ' P ~ J.- of.e4""& 2_ .

~
~
B3 8 2 8 1 Bo
-
~ Az A1 Ao v·
V
C1n
cout 4-blt Binary Adder

Output
Carry
__ .......,
S3 S2 S1 So

t'~~z...A, i,o fu ~,~ 1 15

Cout ----4 4-bit Binary Adder -
( Ignored)
--

Truth Table:
0\ f ~-

INPUT OUTPUT

1st Operand 2nd Operand MSD LSD

A3 AO B3
B2 Bl
BO
Cout
S3
S2 Sl
so
A2 Al (LSB) (MSB) (LSB)
(MSB) (LSB) (MSB)

l)eparimenl n.f £& TC Engineering, DGOI, FOE

 b) Binary Subtractor be carried out by taking the 2's complement of the n umber to be
. , subtraction can
e rnar)
Th b
nt ofB
subtrac... . we can perform the subtraction (A-B) by add ing 2's compleme
tedpie to A
&'. b' bt t· .
ore xa m , to pen onn mary su rac ,on.
F
Thu s we can use a binary add er

be summarized as follows
Binary subtraction procedures can
l 's
sub trac ted (B) is first pas sed through inverters to obtain its
I. The number to be
we obtain th .
compleme nt.
add ed to I's com ple me nt of B, by making Cin = I. Thus
2. Then I is e 2s
complement ofB- the subtraction.
The 4-b it add er then add s A and 2's complement of B to produce
J. Co tr
sub traction (A-B) and carry output " epresems
➔. S3S2SISo rep res ent the res ult of bin ary
the polarity of the resu It. 1
the result is in tru e bin ary for m but if A<B then Cout =
5. If A>B then Cout == 0 and and the
result is in 2's com ple me nt for m

ng IC 7483:
Design of Binary Subtractor usi
we require
To implement Binary subtraction
I. 4 NOT gates(IC 74LS04) to
obtain its l 's complement ofB.
I. ·
2. 4 bit binary adder with Cin ==

l Adder
4 Bit Subtractor using 4 Bit Paralle

1's co mplement of B

+Vee
83 B2 81 Bo

4 bit ~11&1 blna,y adder C,n a 1 +- Add 1 to 1's

\.7 'f 9Y complement of B
S3 5i S1 S0

'- -v -- '
Result of subtraction

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Enginee ring, DGO!, FOE
 /Jig/ta/ Circ11/1,v (204 JH2)

procedure:

t. Design BCD adder/4-bit binary subtractor.

2. Place the IC on IC Trainer Kit.
3. Connect Vcc and Gnd to respective pins of!C Trainer Kit.
4. Co nstruct the circuit as per the logic diagram.
5. Set the logic inputs.
6. Observe the outputs.

Truth Table:
- , INPUT OUTPUT
1st Operand 2nd Op~rand MSD LSD
A3
A2 Al
AO B3 BO S3
SI
so
(MSB) (LSB) (MSB) B2 Bl Coot S2
(LSB) (MSB) (LSB)

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Conclusion:

Questions:

I . Define BCD number.

2. What do you mean by packed and unpacked BCD?

3. IC 74LS83 is binary adder or BCD adder?

4. What do yo u mean by Full adder and Half adder?

S. What are the rules fo r BCD addition?

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