Lab 02
Lab 02
Lab 02
Objectives
After completing this lab, you will be able to:
Create a I/O Planning project
Enter the pin locations and IO standards via Device view, Package Pins tab, and Tcl commands
Create Period, Input Setup, and Output Setup delays
Perform timing analysis
Procedure
This lab is broken into steps that consist of general overview statements providing information on the
detailed instructions that follow. Follow these detailed instructions to progress through the lab.
Design Description
The design consists of a uart receiver receiving the input typed on a keyboard and displaying the ASCII
code on the LEDs. The block diagram is as shown in Figure 1.
ZedBoard: The eight on-board LEDs will display the pressed character ASCII code equivalent. When a
push button is pressed, the lower and upper nibbles are swapped.
Zybo: The four on-board LEDS will display least significant four bits of the pressed character ASCII code
equivalent. When a push button is pressed, the upper four bits are displayed.
General Flow
1-1-1. Open Vivado by selecting Start > All Programs > Xilinx Design Tools > Vivado 2015.2 >
Vivado 2015.2
1-1-2. Click Create New Project to start the wizard. You will see Create A New Vivado Project dialog
box. Click Next.
1-1-3. Click the Browse button of the Project location field of the New Project form, browse to
<2015_2_zynq_labs>, and click Select.
1-1-4. Enter lab2 in the Project name field. Make sure that the Create Project Subdirectory box is
checked. Click Next.
1-1-5. Select I/O Planning Project option in the Project Type form, and click Next.
1-1-6. Select Do not import I/O ports at this time, and click Next.
1-1-7. In the Default Part form, using the using the Boards specify option; either select the ZedBoard or
the Zybo entry. Click Next.
The device view window and package pins tab will be displayed.
Figure 2. I/O Planning project’s default windows and views for the ZedBoard
Figure 2. I/O Planning project’s default windows and views for the Zybo
2-1-1. Expand the I/O Design entry under the I/O Planning task of the Flow Manager and click on
Create I/O Ports.
2-1-2. Type clk_pin in the Name field, select Input for the Direction and select LVCMOS33 as the I/O
Standard, and click OK.
2-1-3. Similarly, create the btn_pin, rxd_pin and rst_pin input ports.
2-1-4. Move mouse over the Device view window and hover over it on the Y9 location.
2-1-6. In the Package Pins pane, click in the Ports column of Y9 pin’s row, click clk_pin.
2-1-8. Select Edit > Find or Ctrl-F to open the Find form. Select Package Pins in the Find drop-down
field, type *Y10 in the match criteria field, and click on OK.
Notice that the Y10 pin is highlighted in the Device view and the corresponding entry is displayed
in the Package Pins tab.
2-2. Assign output pins led_pins[7] to led_pins[0] to U14, U19, W22, V22, U21,
U22, T21, and T22 locations creating them as a vector and assigning them
using Tcl command set_property. They all will be LVCMOS33.
2-2-1. In the I/O Ports tab, click on the create I/O port button on the left vertical ribbon.
2-2-2. Type led_pins in the Name field, select Output direction, click on the check-box of Create bus,
set the msb to 7, and select LVCMOS33 I/O standard, and click OK.
The led_pins entries will be created and displayed in the I/O Ports tab. Notice that the I/O
standard and directions are already set, leaving only the pin locations to be assigned.
2-2-3. In the Tcl console, type or copy and paste the following commands to assign the pin locations:
2-2-5. Enter uart_led in the File name field, and click OK.
The uart_led.xdc file will be created and added to the Sources tab.
2-2-6. Expand the I/O Planning > I/O Design in the Flow Navigator pane.
2-2-7. Click on Report DRC and click OK. Notice the design rules checker is run and two warnings are
reported. Ignore these warnings.
2-2-8. Click on Report Noise and click OK. Notice the noise analysis is done on the output pins only
(led_pins) and the results are displayed.
The Migrate to RTL form will be displayed with Top RTL file field showing
<2015_2_zynq_labs>/lab2/io_1.v entry.
2-2-11. Select the Hierarchy tab and notice that the uart_led.v file has been added to the project with
top-level module name as ios. If you double-click the entry, you will see the module name with
the ports listing.
Figure 10. The top-level module content and the design hierarchy after migrating to RTL
2-3-2. In the Add Sources form, select Add or Create Design Sources, and click Next.
The Primary Clocks pane will be displayed, showing clk_pin having undefined period.
3-2-3. Click in the Name field and change the name to clk_pin_p.
The primary clock constraint in the table form and the command form will be as shown below.
The Generated Clocks pane will be displayed. Since there is no generated clock present in the
design, no clock source is listed.
The Forwarded Clocks pane will be displayed. Since there is no forwarded clock present in the
design, no clock source is listed.
The External Feedback Delays pane will be displayed. Since there is no feedback clock present
in the design, no clock source is listed.
The Input Delays pane will be displayed showing btn_pin, rst_pin, and rxd_pin interface pins
and undefined tcl_min, trce_dly_min, tco_max, trce_dly_max fields.
3-3-2. Click Apply to apply the constraints to btn_pin since that is what is selected.
3-3-3. Select the rst_pin and apply the same constraints to it.
3-3-4. Similarly, select the rxd_pin and apply the same constraints to it.
3-3-5. Click on the Tcl Command Preview tab to see the actual commands being written.
Figure 14. The Tcl Command Preview tab showing the commands for ZedBoard
The Output Delays pane will be displayed showing led_pins[*] interface pins and undefined tsu,
trce_dly_max, thd, trce_dly_min fields.
3-4-3. Click on the Tcl Command Preview tab to see the actual commands being written.
Figure 17. The Tcl Command Preview tab showing the commands for ZedBoard
3-4-4. Click Next, and the Combinational Delays pane will be displayed showing no combinational
path exists in the design.
3-4-5. Click Next, and the Physically Exclusive Clock Groups pane will be displayed.
3-5. Generate an estimated Timing Report showing both the setup and hold
paths in the design.
3-5-1. In the Flow Navigator, select Synthesized Design > Report Timing Summary.
3-5-2. In the Options tab, verify min_max is selected from the Path delay type drop-down list.
The Timing Results view opens at the bottom of the Vivado IDE.
The Design Timing Summary report provides a brief worst Setup and Hold slack information and
Number of failing endpoints to indicate whether the design has met timing or not.
Note that there are three timing failures under the hold check.
3-5-4. Click on the link next to Worst Hold Slack (WHS) to see the list of failing paths.
Figure 19. The list of paths showing hold violations for ZedBoard
You can see that the failing path is at the input of rst_pin. Similarly, Path 12 and Path 13 are of
btn_pin and rxd_pin.
4-1-2. Click Yes to run the synthesis first before running the implementation process.
When the implementation is completed, a dialog box will appear with three options.
4-1-3. Select the Open Implemented Design option and click OK.
4-1-4. Click Yes if you are prompted to close the synthesized design.
4-2-1. In the Flow Navigator pane, under Implementation > Implemented Design, click Report Timing
Summary.
The Design Timing Summary window opens at the bottom in the Timing tab.
4-2-4. Double-click on the 1st failing path and see the detailed analysis. Note that about 6.458 ns
(12.082-5.624) is the data path delay, clock path skew is 5.624 ns, and clock uncertainty of 0.035
ns, with the violation of about 2.118 (6.458+5.624+0.035-10.0) ns.
The output path delay can be reduced by placing the register in IOB.
4-2-5. Apply the constraint by typing the following command in the Tcl console.
4-2-6. Select File > Save Constraints, accepting the default choices.
4-2-8. Click Save and then Yes to reset the synthesis run, perform the synthesis, and run the
implementation.
4-2-9. Open the implemented design and observe that the number of failing paths in the Design Runs
tab reported is 0.
4-2-10. Click Report Timing Summary, and observe that there are no failing paths.
5-1-1. In the Flow Navigator, under Program and Debug, click Generate Bitstream.
5-1-2. The write_bitstream command will be executed (you can verify it by looking in the Tcl
console).
5-2. Plug-in the PmodUSBUart module into the top-row of the JA1 PMOD
connector. Connect the module to the host machine using a micro-USB
cable. Connect the board and power it ON. Open a hardware manager, and
program the FPGA.
5-2-1. Connect the micro-USB cable between the PmodUSBUart module and the host USB port.
5-2-2. Plug-in the PmodUSBUart module into the top-row of the JA1 PMOD connector (next to the slide-
switch 8).
5-2-3. Make sure that the Micro-USB cable is connected to the JTAG PROG connector (next to the
power supply connector). Connect the power jack and turn ON the power.
5-2-4. Select the Open Hardware Manager option and click OK.
5-2-7. The Hardware Session status changes from Unconnected to the server name and the device is
highlighted. Also notice that the Status indicates that it is not programmed.
Select the device in the Hardware Device Properties, and verify that the ios.bit is selected as the
programming file in the General tab.
5-2-8. Select the device and verify that the ios.bit is selected as the programming file in the General
tab.
5-3-2. Select an appropriate COM port (you can find the correct COM number using the Control Panel).
5-3-3. Set the COM port for 115200 baud rate communication.
5-3-4. Right-click on the FPGA entry in the Hardware window and select Program Device…
The programming bit file be downloaded and the DONE light will be turned ON indicating the
FPGA has been programmed.
5-3-6. Verify the functionality as you did in the previous lab, by typing some characters into the terminal,
and watching the corresponding values appear on the LEDs. Press the center button to reset or
upper button to swap the two nibbles.
5-3-7. When satisfied, Select File > Close Hardware Manager. Click OK to close it.
5-3-8. Close the terminal emulator program and power OFF the board.
5-3-9. When done, close the Vivado program by selecting File > Exit and click OK.
6-1-1. Expand the I/O Design entry under the I/O Planning task of the Flow Manager and click on
Create I/O Ports.
6-1-2. Type clk_pin in the Name field, select Input for the Direction and select LVCMOS33 as the I/O
Standard, and click OK.
6-1-3. Similarly, create the btn_pin, rxd_pin and rst_pin input ports.
6-1-4. Move mouse over the Device view window and hover over it on the L16 location.
6-1-6. In the Package Pins pane, click in the Ports column of L16 pin’s row, click clk_pin.
6-1-8. Select Edit > Find or Ctrl-F to open the Find form. Select Package Pins in the Find drop-down
field, type *J15 in the match criteria field, and click on OK.
Notice that the J15 pin is highlighted in the Device view and the corresponding entry is displayed
in the Package Pins tab.
6-2. Assign output pins led_pins[3] to led_pins[0] to D18, G14, M15, and M14
locations creating them as a vector and assigning them using Tcl
command set_property. They all will be LVCMOS33.
6-2-1. In the I/O Ports tab, click on the create I/O port button on the left vertical ribbon.
6-2-2. Type led_pins in the Name field, select Output direction, click on the check-box of Create bus,
set the msb to 3, and select LVCMOS33 I/O standard, and click OK.
The led_pins entries will be created and displayed in the I/O Ports tab. Notice that the I/O
standard and directions are already set, leaving only the pin locations to be assigned.
6-2-3. In the Tcl console, type the following commands to assign the pin locations:
6-2-5. Enter uart_led in the File name field, and click OK.
The uart_led.xdc file will be created and added to the Sources tab.
6-2-6. Expand the I/O Planning > I/O Design in the Flow Navigator pane.
6-2-7. Click on Report DRC and click OK. Notice the design rules checker is run and two warnings are
reported. Ignore these warnings.
6-2-8. Click on Report Noise and click OK. Notice the noise analysis is done on the output pins only
(led_pins) and the results are displayed.
The Migrate to RTL form will be displayed with Top RTL file field showing
<2015_2_zynq_labs>/lab2/io_1.v entry.
6-2-11. Select the Hierarchy tab and notice that the uart_led.v file has been added to the project with
top-level module name as ios. If you double-click the entry, you will see the module name with
the ports listing.
Figure 10. The top-level module content and the design hierarchy after migrating to RTL
6-3-2. In the Add Sources form, select Add or Create Design Sources, and click Next.
The Primary Clocks pane will be displayed, showing clk_pin having undefined period.
7-2-3. Click in the Name field and change the name to clk_pin_p.
The primary clock constraint in the table form and the command form will be as shown below.
The Generated Clocks pane will be displayed. Since there is no generated clock is present in the
design, no clock source is listed.
The Forwarded Clocks pane will be displayed. Since there is no forwarded clock is present in the
design, no clock source is listed.
The External Feedback Delays pane will be displayed. Since there is no feedback clock is
present in the design, no clock source is listed.
The Input Delays pane will be displayed showing btn_pin, rst_pin, and rxd_pin interface pins
and undefined tcl_min, trce_dly_min, tco_max, trce_dly_max fields.
7-3-2. Click Apply to apply the constraints to btn_pin since that is what is selected.
7-3-3. Select the rst_pin and apply the same constraints to it.
7-3-4. Similarly, select the rxd_pin and apply the same constraints to it.
7-3-5. Click on the Tcl Command Preview tab to see the actual commands being written.
Figure 14. The Tcl Command Preview tab showing the commands for Zybo
The Output Delays pane will be displayed showing led_pins[*] interface pins and undefined tsu,
trce_dly_max, thd, trce_dly_min fields.
7-4-3. Click on the Tcl Command Preview tab to see the actual commands being written.
Figure 17. The Tcl Command Preview tab showing the commands for Zybo
7-4-4. Click Next, and the Combinational Delays pane will be displayed showing no combinational
path exists in the design.
7-4-5. Click Next, and the Physically Exclusive Clock Groups pane will be displayed.
7-5. Generate an estimated Timing Report showing both the setup and hold
paths in the design.
7-5-1. In the Flow Navigator, select Synthesized Design > Report Timing Summary.
7-5-2. In the Options tab, select min_max from the Path delay type drop-down list.
The Timing Results view opens at the bottom of the Vivado IDE.
The Design Timing Summary report provides a brief worst Setup and Hold slack information and
Number of failing endpoints to indicate whether the design has met timing or not.
Note that there are four timing failures under the setup check and three timing failures under the
hold check.
7-5-4. Click on the link next to Worst Hold Slack (WHS) to see the list of failing paths.
You can see that the failing path is at the input of rst_pin. Similarly, Path 12 and Path 13 are of
btn_pin and rxd_pin.
7-5-7. Click on the Setup under the Intra-Clock Paths in the left pane, to see ten paths.
7-5-8. Double-click on Path 1 to see the detailed path analysis in the table form.
7-5-9. Select the Path 1, right-click and select the schematic to see it in the schematic view.
8-1-2. Click Yes to run the synthesis first before running the implementation process.
When the implementation is completed, a dialog box will appear with three options. Ignore the
critical warnings.
8-1-3. Select the Open Implemented Design option and click OK.
8-1-4. Click Yes if you are prompted to close the synthesized design.
8-2-1. In the Flow Navigator pane, under Implementation > Implemented Design, click Report Timing
Summary.
The Design Timing Summary window opens at the bottom in the Timing tab.
8-2-4. Double-click on the 1st failing path and see the detailed analysis. Note that about 5.764 ns is the
data path delay, clock path skew is 5.192 ns, and clock uncertainty of 0.035 ns, with the violation
of about 2.991 (5.764+5.192+0.035-8.0) ns.
The output path delay can be reduced by placing the register in IOB.
8-2-5. Apply the constraint by typing the following command in the Tcl console.
8-2-6. Select File > Save Constraints. Click OK and then Yes to save.
8-2-8. Click Yes to reset the synthesis run, perform the synthesis, and run the implementation.
8-2-10. Click Report Timing Summary, and observe that the failing paths are at the LED output pins.
9-1-1. In the Flow Navigator, under Program and Debug, click Generate Bitstream.
9-1-2. The write_bitstream command will be executed (you can verify it by looking in the Tcl
console).
9-2. Plug-in the PmodUSBUart module into the top-row of the JE PMOD
connector. Connect the module to the host machine using a micro-USB
cable. Connect the board and power it ON. Open a hardware manager, and
program the FPGA.
9-2-1. Connect the micro-USB cable between the PmodUSBUart module and the host USB port.
9-2-2. Plug-in the PmodUSBUart module into the top-row of the JE PMOD connector (next to the slide-
switch 8).
9-2-3. Make sure that the Micro-USB cable is connected to the JTAG PROG connector (next to the
power supply connector). Connect the power jack and turn ON the power.
9-2-4. Select the Open Hardware Manager option and click OK.
You can also click on the Open Recent Hardware Target link if the board was already targeted
before. In this case skip to step 9-2-10.
9-2-6. Click Next to see the Vivado CSE Server Name form.
The JTAG cable which uses the digilent_plugin should be detected and identified as a hardware
target. It will also show the hardware devices detected in the chain.
9-2-9. The Hardware Manager status changes from Unconnected to the server name and the device is
highlighted. Also notice that the Status indicates that it is not programmed.
9-2-10. Select the device and verify that the ios.bit is selected as the programming file in the General
tab.
9-3-2. Select an appropriate COM port (you can find the correct COM number using the Control Panel).
9-3-3. Set the COM port for 115200 baud rate communication.
9-3-4. Right-click on the FPGA entry in the Hardware window and select Programming Device…
The programming bit file be downloaded and the DONE light will be turned ON indicating the
FPGA has been programmed.
9-3-6. Verify the functionality as you did in the previous lab, by typing some characters in the terminal
emulator window and see the corresponding ASCII equivalent bit pattern (least significant 4-bits)
displayed on the LEDs.
9-3-7. Press and hold BTN0 and see the the upper four bits of the character. Press and hold BTN1 to
reset the output.
9-3-8. When satisfied, select File > Close Hardware Manager. Click OK to close it.
9-3-9. Close the terminal emulator program and power OFF the board.
9-3-10. When done, close the Vivado program by selecting File > Exit and click OK.
Conclusion
In this lab, you learned how to create an I/O Planning project and assign the pins via the Device view,
Package Pins tab, and the Tcl commands. You then exported to the rtl project where you added the
provided source files. Next you created timing constraints and performed post-synthesis and post-
implementation timing analysis.
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