Tutorial 1

Using Vivado
In this lab, we are going to implement a simple combinational circuit given in Fig. 1.1 on our FPGA. For this
purpose, we will learn about assigning I/O pins of our modules for synthesizing the designs on the FPGA.
After that, we are going to use Vivado to burn our System Verilog code on the FPGA.

Overview of Vivado Design Suite

Vivado design suite software developed by Xilinx for the synthesis and implementation of System Verilog
designs. For this lab we will use the web-pack edition of Vivado.

a a.b
b a1

c o1 y = a.b + c

Fig. 1.1: Simple logic circuit implementing y = a.b + c

Creating a new project in Vivado

1. From Quick Start click on Create Project. A new project dialog box will appear. Click on Next.
(Fig. 1.2)

Fig. 1.2: Project Dialog Box

2. Write the project name. Click on Next.

3. A Project Type dialog box will appear. Select RTL Project and check the Do not specify sources at the
time box. Click Next to continue. (Fig. 1.3.)

The instruction manual is for the exclusive use of the students and trainees of University of Engineering and Technology,

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Lahore.
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 Fig. 1.3: Project Type Dialog Box

4. A Default Part dialog box will appear. Select the same family, package and speed of the board. Then,
from the parts shown select xc7a100tcsg324-1. (Fig. 1.4.) Or select the Boards tab and it will display
a list of boards. Select the board Nexys A7 100T and Click Next to Continue.

Fig. 1.4: Default Board Dialog Box

5. Then the Project Summary will appear. Click on Finish. After this, the project will be initialized
and window will appear (Fig. 1.5). Project Summary will contain information about the project
settings, the board used along with the number of errors and warnings that encountered when synthesis,
implementation and bit-stream generation have been completed. Clicking on these will show their
details in the Logs, Messages window.

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The instruction manual is for the exclusive use of the students of University of Engineering and Technology, Lahore.
2024 UET Lahore.
 Fig. 1.5: Vivado Design Suite Window

Creating a new RTL File on Vivado

1. Click on Add sources from the project manager bar. (Fig. 1.5). A dialog box will appear. Select Add
or create design sources and click Next.

2. Add sources dialog box will appear from there click on Create File. When prompted, select a File type,
File name, and File location. Make sure to pick System Verilog and Local to project for the type and
location. Give your file a name ending in .sv. Click on Ok and then on Finish. When Define Module
dialog box appears, inputs and outputs can be defined. Otherwise they will be defined in the System
Verilog file.

3. From the Sources, open the file from Design Sources and write the code provided in Listing. 1.

1 module Lab3(output y,
2 input a,b,c
3 );
4

5 assign y = a & b | c;
6

7 endmodule

Listing 1: System Verilog Code.

4. Click on Schematic to check your gate level design (Fig. 1.6).

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The instruction manual is for the exclusive use of the students of University of Engineering and Technology, Lahore.
2024 UET Lahore.
 Fig. 1.6: Vivado Gate Level Schematic

Assigning Package Pins

There are two methods for assigning package pins which are given as follows:

Using I/O Planning

1. In the project manager bar, click on Open Elaborated Design. A dialog box will appear, click on Ok.
The I/O ports window will open (Fig. 1.7), (if the I/O ports box does not appear then go to Layout
and select I/O planning). Open theI/O ports tab and assign your input output pin connections under
Package Pin according to Fig. 1.7
2. In the I/O Std choose your required voltage level (LVCMOS33.) then press ctrl S and save the
constraints file as XDC file.

Fig. 1.7: Assigning Package pins on Vivado

Using Constraints File When we save the constraints in the above Section 1, we are indirectly creating
a constraint file. But we can directly create that file using the following method:
1. Click on Sources in the project manager and then select add or create constraints and then select
Create File. The constraints file will be created.
2. Type the following code as shown in the Listing 1.1 and then save that file. The pins will be assigned
in the same manner as done in Section 1.

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The instruction manual is for the exclusive use of the students of University of Engineering and Technology, Lahore.
2024 UET Lahore.
 set property =d i c t { PACKAGE PIN H17 IOSTANDARD LVCMOS33 } [ get ports { y }];
set property =d i c t { PACKAGE PIN J15 IOSTANDARD LVCMOS33 } [ get ports { a }];
set property =d i c t { PACKAGE PIN L16 IOSTANDARD LVCMOS33 } [ get ports { b }];
set property =d i c t { PACKAGE PIN M13 IOSTANDARD LVCMOS33 } [ get ports { c }];
Listing 1.1: Assigning Package pins using constraints file.

Synthesizing and Implementing the Design

Under the Project Manager bar click on Run Synthesis. A dialog box will appear click on Ok. After the
synthesis is complete click on Run Implementation and then repeat the same process as before.

Fig. 1.8: Synthesis, Implementation, Generate BitStream

Generating the bit file and Programming the FPGA

1. Under the Program and Debug, click on Generate Bitstream. When the bitstream is generated, connect
the FPGA to your computer with the cable. And under the Open Hardware Manger right click on
Open Target and the click on Auto Connect (Fig. 1.9).

Fig. 1.9: Connecting FPGA to the computer.

2. Vivado will take a few seconds connect to the FPGA. Once done, click on Program device from there
a dialog box appears and click on Program to program your FPGA (Fig. 1.10). The RTL written in

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The instruction manual is for the exclusive use of the students of University of Engineering and Technology, Lahore.
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 System Verilog will be implemented on the FPGA. To check the behavior of the LED, make the truth
table of a.b+c and check for all the possible combinations of inputs.

Fig. 1.10: Programming the Bitstream on the FPGA.

Maximum Combinational Delay

Click on Open Synthesized Design. Click on Report timing Summary. A dialog box will appear, click on Ok.
A timing box will open (Fig. 1.11).

Fig. 1.11: Timing box at the bottom of the screen.

Scroll down the box, click on Datasheet and then Combinational Delays. The window will show the
maximum path along with the name of path in this example it gives maximum delay for c to y with the
delay of 3.5 ns (Fig. 1.12).

Fig. 1.12: Maximum delay for a[0] to c[1] with the delay of 6.778ns.

Device Utilization Summary

Click on Reports in the console tab. Select the synth report utilization. This will give you the device
utilization report.

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The instruction manual is for the exclusive use of the students of University of Engineering and Technology, Lahore.
2024 UET Lahore.
 Fig. 1.13: Device Utilization Summary.

Tasks
Implement the circuit shown in Fig. 1.14 on the FPGA and develop it’s truth table.

x
a
b

Fig. 1.14: Circuit to be implemented.

Deliverables
1. Prepare the report containing following items:

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The instruction manual is for the exclusive use of the students of University of Engineering and Technology, Lahore.
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 (a) Truth table of the circuit.
(b) Maximum combinational delay in Synthesis: Read the report of your circuit and describe which
path has the maximum combinational delay?
(c) Resource Utilization: Read the synthesis report and identify how many resources in the FPGA
such as lookup tables (LUTs), input/output (IOs), etc., has been utilized.

2. System Verilog code for the circuit using structural modeling (using assign statements).
3. Synthesize the circuit for the starter kit available in the lab. Tie inputs to the switches and outputs
to the LEDs available on the board.

The collaboration between students is encouraged, but blind code sharing/copying is not allowed. If you
are unable to explain anything in your code, it will be assumed you have copied it. So make sure you know
every thing you have written in your code. We are least concerned about how you have learnt something as
long as you have learnt it well. Copied assignments will get ZERO marks.

Acknowledgments
The manual has been written by Mr. Ali Imran and Ms. Shehzeen Malik.

©
The instruction manual is for the exclusive use of the students of University of Engineering and Technology, Lahore.
2024 UET Lahore.