Testability of VLSI

Lecture 2: Fault Modelling

By Dr. Sanjay Vidhyadharan

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 Defects, Errors, and Faults
Defect. A defect in an electronic system is the unintended difference between
the implemented hardware and its intended design.
Example : unwanted wire (short to ground)
1. Process Defects – missing contact windows, parasitic transistors, oxide breakdown,
etc.
2. Material Defects – bulk defects (cracks, crystal imperfections), surface impurities,
etc.
3. Package Defects – contact degradation, seal leaks, etc
4. Age Defects – dielectric breakdown, electromigration, etc.
Fault. A representation of a “defect” at the abstracted function level is called a fault
Example: Stuck to Zero Fault
Error. A wrong output signal produced by a defective system is called an error. An
error is an “effect” whose cause is some “defect.
Example: output = 0, when a=b=1 for a AND gate

Failure : Deviation from expected behavior Example: computer crash

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 Fabrication Faults

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 Fabrication Faults

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 Fault Models
Why Fault Modelling?

1. Defects are hard to handle

How many possible defects in a circuit ? Way too many
Number of faults can be easily calculated in a circuit

2. Fault models makes test automation possible

Automatic test pattern generation (ATPG) generate test patterns
Fault simulation
Evaluate test quality
Automatic diagnosis
Locate defects

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 Fault Models

1. Assertion Fault: An assertion expresses a property of a high-level function in the form:

“antecedent consequent,” where antecedent and consequent can be simple predicates like
“line L takes symbolic value v” or conjunctions of simple predicates.

2. Behavioural Faults (Functional or High level): When the behavior of an electronic

system is described in computer-readable form, it is generally written in a programming
language (such as C) or some other hardware description language that resembles a
programming language.

3. Structural Faults: The structure of a circuit may refer to its topology or to physical
geometry. Examples of structural faults are single stuck-at faults and bridging faults.
Focus is on manufacturing defects not functional aspect of DUT.

➢ Please refer to other types of faults in the textbook

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 Functional Versus Structural Testing

𝐹𝑢𝑛𝑐𝑡𝑖𝑜𝑛𝑎𝑙 𝑇𝑒𝑠𝑡 𝑉𝑒𝑐𝑡𝑜𝑡𝑠 2129 = 6.8 ∗ 1038

𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑡𝑖𝑚𝑒 𝑤𝑖𝑡ℎ 𝐶𝑙𝑜𝑐𝑘 𝑜𝑓 1 𝐺𝐻𝑧 ≈ 22 𝑦𝑒𝑎𝑟𝑠

𝑀𝑎𝑥 𝑆𝑡𝑟𝑢𝑐𝑡𝑢𝑟𝑎𝑙 𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 64 ∗ (10 + 17)

𝐴𝑐𝑡𝑎𝑢𝑙 𝑆𝑡𝑟𝑢𝑐𝑡𝑢𝑟𝑎𝑙 𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑐𝑜𝑢𝑙𝑑 𝑏𝑒 𝑠𝑚𝑢𝑐ℎ 𝑙𝑒𝑠𝑠𝑒𝑟𝑎𝑠 𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑒 𝑠𝑎

𝑓𝑎𝑢𝑙𝑡𝑠 𝑔𝑒𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑒𝑑 𝑤𝑖𝑡ℎ 𝑠𝑖𝑛𝑔𝑙𝑒 𝑣𝑒𝑐𝑡𝑜𝑟
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 Common Structural Fault Models

➢ Single stuck-at faults

➢ Transistor open and short faults
➢ Bridging Faults
➢ Delay faults (transition, path)
➢ Analog faults

➢ Please refer to other types of faults in the textbook

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 Single Stuck-at faults

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 Single Stuck-at faults

How many Fault Sites ? 3

How many Fault ?

Minimum test length for 100% SSF fault coverage ? 3

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 Single Stuck-at faults

Properties of single stuck-at fault

⚫ Only one line is faulty
⚫ The faulty line is permanently set to 0 or 1
⚫ The fault can be at an input or output of a gate

XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

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 Single Stuck-at faults
SSF on fanout wires not equivalent to SSF on fanout branches
Faults on stems and faults on branches are counted separately
Example: E is fanout stem; L,F are fanout branches

𝐾 = 𝐴ҧ𝐵𝐶 ҧ 𝐶ҧ + 𝐴𝐵𝐶
ത + 𝐴𝐵 ҧ

𝐾 = 𝐴(ҧ 𝐵𝐶 ҧ
ത + 𝐵 𝐶+𝐵𝐶)
ҧ + 𝐶)
𝐾 = 𝐴(𝐵

𝐾 = 𝐴 + (𝐵 + 𝐶)

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 Multiple Stuck-at faults

𝐼𝑓 𝑡ℎ𝑒𝑟𝑒 𝑎𝑟𝑒 𝑁 𝑝𝑜𝑠𝑠𝑖𝑏𝑙𝑒 𝑓𝑎𝑢𝑙𝑡 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛𝑠 𝑖𝑛 𝑎 𝑐𝑖𝑟𝑐𝑢𝑖𝑡

𝑇𝑜𝑡𝑎𝑙 𝑝𝑜𝑠𝑠𝑖𝑏𝑖𝑙𝑖𝑡𝑖𝑒𝑠 𝑖𝑠 3𝑁 𝑎𝑠 𝑎 𝑙𝑖𝑛𝑒 𝑏𝑒 𝑏𝑒 𝑠𝑎0 , 𝑠𝑎1 𝑜𝑟 𝑔𝑜𝑜𝑑
𝑂𝑛𝑒 𝑝𝑜𝑠𝑠𝑖𝑏𝑖𝑙𝑖𝑡𝑦 𝑜𝑓 𝑐𝑖𝑟𝑐𝑢𝑖𝑡 𝑏𝑒𝑖𝑛𝑔 𝑔𝑜𝑜𝑑
2𝑁 𝑝𝑜𝑠𝑠𝑖𝑏𝑖𝑙𝑖𝑡𝑖𝑒𝑠 of single fault
Possibilities of multiple fault 3𝑁 - 1- 2N

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 Multiple Stuck-at faults

Different
Algorithms

Hughes, J.L.A., and E.J. McCluskey, “An Analysis of the Multiple Fault Detection Capabilities of
Single Stuck-at Fault Test Sets,” Proc. of Int’l Test Conf, Philadelphia, PA, Oct. 1984, pp. 52–58.
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 Multiple Stuck-at faults

1
0(1)

0(1)

SA0

What should be the test vector ? 011

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 Multiple Stuck-at faults

SA1

1(0)
1

0(1)

SA0

What should be the test vector ? 011 SA1 is Masking SA0

What should be the test vector ? 010 detects the MSF {c SA0, a SA1}.
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 Bridging faults

Input to Output Short Input to Input Short Output to Output Short

➢ Improper masking or etching

➢ Loose or excess bare wires
➢ Defective printed circuit boards
➢ Shorting of pins of a chip

Test Vectors for Input and Output Stuck-at Faults cover Input-to-Output Shorts

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 Bridging faults
Input to Output Short

1. Can cause oscillations

2. Creates Memory

Test Vectors for Input and Output Stuck-at Faults cover Input-to-Output Shorts

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 Bridging faults
Short is Modeled as Low Resistance

Original Wired-OR Wired-AND F-dominant

Fault-free FG Faulty FG Faulty FG Faulty FG
00 00 00 00
01 11 00 00
10 11 00 11
11 11 11 11

If F,G = 0,0 can be detected as F s-a-0

If F,G = 1,1 can be detected as G s-a-1

High Resistance Bridges do not affect the logic value, and hence are undetectable by a
static logic test.
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 Bridging faults
Different Models Need Different Patterns

Inputs Fault-free Wired Wired A

ABC Output OR AND dominant
000 0 0 0 0
001 1 1 1 1
010 1 0 0 0
011 1 0 0 1
100 0 0 0 0
101 0 0 0 0
110 0 0 0 0
111 0 0 0 0
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 Bridging faults

[Millman 88] S.D. Millman, McCluskey, “Detecting bridging faults with stuck-at test sets,”
ITC 1988.
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 Delay faults

Delay Fault

Slow to rise, slow to fall

Slow to rise (STR), slow to fall Transition (STF), faults due to Vt Variation, Doing
Variation, Improper contacts etc
No fault detected at static and low frequency operation but glitches can be there at
high operating frequencies and cause errors in sequential circuits
Delay Faults requires two test vectors 22

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 Delay faults
Delay Fault

Can be modelled a RC delay but can be because of poor MOSFET being fabricated
or nay other fab defects .

Delay Faults requires two test vectors

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 Delay faults

Path Delay Fault

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 Delay faults

How Many Paths ? 5 paths: {AHK, BELHK, BEFJK, CELHK, CEFJK}

How Many set of test vectors ? 10 sets

Test vector to detect STF fault at F ? 001-000

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 Delay faults

(101,111) : Non-robust test for path

STR at E

(101,100) : Robust test for path STR

at E

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 Delay faults
Robust Testing may note possible always

AND1 Check : B=1 , C= 0 AND2 Check : A=0 , C= 1

AND3 Check : A=0 , Will render Both AND1 and AND 3 to Low
A=1, B=0 will activate AND2 and B=0 will activate AND 14
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 Experimental Results

[2]/ Video lectures by Professor James Chien-Mo Li

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 Fault Models

in0 in1 Ctrl Out Detected SSF

0 1 0 0 In0 (Sa1), Out (Sa1), Cntrl (Sa1)
1 0 0 1 In0 (Sa0), Out (Sa0),
1 0 1 0 In1 (Sa1), Cntrl (Sa0)
1 1 1 1 In1 (Sa0)

Note: only four vectors for 3 inputs

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 Transistor faults

OS
Two types of Transistor Faults

➢ Stuck-open -- a single transistor is permanently stuck in the open state

irrespective of its gate voltage. Single Stuck-open detection requires two test
patterns

➢ Stuck-short -- a single transistor is permanently shorted irrespective of its

gate voltage. Detection by quiescent IDD

http://ece-research.unm.edu/jimp/vlsi_test/slides/html/faults2.html
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 Transistor faults
Stuck-open

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 Transistor faults

Two-pattern Tests for Stuck-open Faults

Automation available to optimize Stuck-at and Stuk-open Fault

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 Transistor faults
Stuck-on fault

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 Transistor faults
SOP  TDF

[2]. Video lectures by Professor James Chien-Mo Li

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 Cell Aware Fault Model

3X1 Mux

Hapke, Friedrich & Redemund, Wilfried & Glowatz, Andreas & Rajski, Janusz & Reese, M. & Hustava, Marek
& Keim, Martin & Schlöffel, Jürgen & Fast, Anja. (2014). Cell-Aware Test. Computer-Aided Design of
Integrated Circuits and Systems, IEEE Transactions on. 33. 1396-1409. 10.1109/TCAD.2014.2323216.
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 Cell Aware Fault Model

3X1 Mux

PPM reduction AMD 32 nm notebook processor.

Hapke, Friedrich & Redemund, Wilfried & Glowatz, Andreas & Rajski, Janusz & Reese, M. & Hustava, Marek
& Keim, Martin & Schlöffel, Jürgen & Fast, Anja. (2014). Cell-Aware Test. Computer-Aided Design of
Integrated Circuits and Systems, IEEE Transactions on. 33. 1396-1409. 10.1109/TCAD.2014.2323216.
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 Cell Aware Fault Model

in0 in1 Ctrl Out Detected SSF

0 1 0 0 In0 (Sa1), Out (Sa1), Cntrl (Sa1)
1 0 0 1 In0 (Sa0), Out (Sa0),
1 0 1 0 In1 (Sa1), Cntrl (Sa0)
1 1 1 1 In1 (Sa0)
0 0 1 0 Bridging w and in0

Hapke, Friedrich & Redemund, Wilfried & Glowatz, Andreas & Rajski, Janusz & Reese, M. & Hustava, Marek
& Keim, Martin & Schlöffel, Jürgen & Fast, Anja. (2014). Cell-Aware Test. Computer-Aided Design of
Integrated Circuits and Systems, IEEE Transactions on. 33. 1396-1409. 10.1109/TCAD.2014.2323216.
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 References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

Lab. of Dependable Systems Graduate Institute of Electronics Engineering
National Taiwan University
https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-
SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1

3. http://ece-research.unm.edu/jimp/vlsi_test/slides/html/faults2.html

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 Thankyou

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