Two-Stage H-Bridge Transformer Coupled DC-DC Converter with Zero Voltage Switching

R. Samuel Rajesh Babu

Research scholar, EEE Department, Sathyabama University, Chennai, India. samuel.rajeshbabu@gmail.com
AbstractThis paper portrays the analysis and simulation of a Two Stage H-Bridge Transformer coupled DCDC converter with Zero Voltage Switching (ZVS). The principle of H-bridge control is that each phase leg is switched with a 50% duty cycle and the active power flow through the converter is controlled by varying the phase shift between the two phase leg square waves. This approach is known as phase-shifted square wave modulation. The proposed converter achieves zero-voltage switching (ZVS) at high frequency using IGBTs, and overcomes issues relate to the selection of the ZVS capacitors, the transformer turns ratio and the series resonant inductor. This converter provides high power density, low switching loss, less EMI and high efficiency.

International Journal of Computer Information Systems, Vol. 3, No. 3, 2011

Dr. Joseph Henry

Professor, EEE Department, Veltech University, Chennai, India.

Keywords- Zero Voltage Switching (ZVS); H-Bridge; DC to DC converter; Phase Shifted Square Wave Modulation I. INTRODUCTION H-BRIDGE system used in high power DC-DC conversion is a popular and well-received method in many applications. The basic H-bridge converter can be modified easily by introducing soft-switching to the converters [1], [2]. There are many types of soft-switching converters including load-resonant, square-wave resonant and zerovoltage and zero-current resonant [3]. The phase-shifted series resonant converter based on an H-bridge has the advantage of inherent short circuit protection characteristic and high conversion efficiency [4][6]. Unbalanced switching signal will not cause saturation to the transformer due to the presence of a series resonant capacitor [7]. The two switching devices (Q1 and Q2 ,Q3 and Q4) in each leg of the H-bridge are switched alternatively with almost 50% duty ratio. The switching pulses to the two legs have a phase angle in order to change the voltage applied to the resonant tank [8]-[10]. The general design rule is that the switching frequency is always chosen to be close to the resonant frequency , defined by the resonant inductor and resonant capacitor to make the resonant current waveform be quite sinusoidal[11]-[12]. Of course, to reduce the size of energy storage components such as inductor, capacitor and transformer, the switching frequency is very high [13]. The resonant current is regulated by changing the phase angle and rectified as the input power signal of the output filter

[14]. Thus the output voltage is controlled. Normally the value of the load resistance and the input dc voltage are variable within a specific range, the voltage feedback and certain closed-loop control law should be employed to keep the output voltage at the desired values. In Ac link dc-dc converter, DC is first converted to AC by an inverter and then ac is stepped up or stepped down by a transformer which is then converted back to dc by diode rectifier[15]-[16]. As the conversion has two stages, dc to ac and then ac to dc. This type of chopper is called as AC link chopper. The high output voltage and high output current characteristic of this two stage dc-dc converter makes it desirable for high power applications. They are typically employed to provide a range of functions, including DC to AC inversion to generate the AC supplies for instrument panels, cabin lights, etc., and also for high-current battery chargers. Increasingly, high-frequency DC-DC converters are being employed in battery charging and electrolyser applications, with their advantages of reduced size and weight. II. THE PROPOSED H-BRIDGE TRANSFORMER COUPLED DC-DC CONVERTER

The proposed H-Bridge Transformer coupled DCDC converter with Zero Voltage Switching (ZVS) is widely used for the high frequency and high power applications. The proposed converter DC-DC converter with IGBT switches employs phase shift modulation which incorporates the leakage inductance of the transformer to achieve zerovoltage switching, but only achieves it near the full load condition. Low component count and zero full load switching losses enable this topology to achieve low cost, high power density, high efficiency, and low EMI, which makes it a good choice for medium to high power DC-DC applications. Several techniques for high frequency DC-DC conversion exist to reduce component stresses and switching losses while achieving high power density and improved performance. Among them, the H-bridge zero-voltageswitched (ZVS) converter is one of the most attractive alternative techniques which is widely used for softswitched circuit in high-power applications. This constantfrequency converter employs phase-shift (PS) control and

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features ZVS of the primary switches with relatively small circulating energy. However, full ZVS operation can only be achieved with a limited load and input-voltage range, unless a relatively large inductance is provided in series with the primary winding of the transformer either by an increased leakage inductance of the transformer and/or by an additional external inductor. This increased inductance has a detrimental effect on the performance of the converter since it causes an increased loss of the duty cycle on the secondary side, as well as severe voltage ringing across the secondary-side output rectifiers due to the resonance between the inductance and the junction capacitance of the rectifier. The secondary-side ringing can be suppressed by an active snubber circuit. For implementations with an external primary inductor, the ringing can also be effectively controlled by employing primary-side clamp diodes D1and D2. While the snubber approaches to the secondary-side ringing problem, they do not offer any improvement of the secondary-side duty-cycle loss. Generally, these circuits utilize energy stored in the inductive components of an auxiliary circuit to achieve ZVS for all primary switches in an extended load and input voltage range. Ideally, the auxiliary circuit needs to provide very little energy, if any, at full load because the full-load current stores enough energy in the converters inductive components to achieve complete ZVS for all switches. As the load current decreases, the energy provided by the auxiliary circuit must increase to maintain ZVS, with the maximum energy required at no load. The energy stored for ZVS is independent of load. However, these converters have to use large inductors so, high circulating energy that is needed1 to achieve no-load ZVS and that is due to a relatively large inductor employed to assist ZVS. The zero-voltage transition approach, as well as the active-clamp snubber approach, leads to zero-voltage switching of the transistors and zero-current switching of the diodes. These approaches have been successful in substantially improving the efficiency of transformer coupled converters. Soft-switching strategies offer an attractive alternative, but converter design using these strategies is still quite challenging. Fig.1 shows the topology of H-Bridge Transformer coupled DC-DC converter with Zero Voltage Switching .The converter is fed from a three phase AC supply, and so the complete system includes a diode rectifier, a high-voltage IGBT based H-Bridge, a high-frequency center-tapped- output transformer, associated full wave rectifier and an LC output filter. The Hbridge control principle is simply that each phase leg is switched with a 50% duty cycle, and the active power flow through the converter is controlled by varying the phase shift between the two phase leg square waves. This approach is known as phase-shifted square wave modulation.

International Journal of Computer Information Systems, Vol. 3, No. 3, 2011

Figure 1. Circuit diagram of H-Bridge Transformer coupled DC-DC converter

III.

MODES OF OPERATION

There are six modes of operation. A. Mode 1. Switch conduction Q1 and Q2 are conducting during time interval (t0-tl), and the converter transfers input power to the secondary side. If output voltage (V0) assumes as a constant voltage source, then the primary transformer current is increased with the slope of

Vin / NVo
Lf .N 2

(1)

Figure 2. Q1, Q2 conduction

B. Mode2. Left Leg Transition When Q1 is turned off at time tl, the primary current (IP) which is the sum of the reflected output Current (I0) and the circulating current stored in the primary transformer leakage inductance charges the capacitance (Cp) of Q1 and discharges the capacitance (Cp) of Q3. The capacitance voltage of Q1 reaches VIN when the capacitance voltage of Q3 is zero. This mode ends when body diode (D3) of Q3 is turned-on. After time T, if Q3 is turned on, ZVS is easily achieved due to the reflected output current (Io) during the interval of the left leg transition (tl-t2).

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International Journal of Computer Information Systems, Vol. 3, No. 3, 2011 to secondary side and linearly decreased as circulating current because the load current is shorted through output rectifier diodes.

Figure 3. Left Leg Transition

C. Mode3. Primary free wheeling After D3 starts conducting, Q3 can be turned on with zero voltage condition. The primary voltage decreased to zero. The primary current during this mode (t2-t3) is freewheeling through Q 2 and D3, and output current (I0) is also freewheeling through the secondary rectifier.

Figure 6. Linear current ramping

F. Mode6. Power Tranfer Mode Q 4 and Q3 are conducted during the time interval (t4-t5) and input power is transferred to the load.

Figure 4. Primary free wheeling

D. Mode4. Right Leg Transition When Q2 is turned off at time t3, free wheeling state is ended. During this mode (t3-t4) the transformer secondary is short circuit through rectifier diode, so output current (Io) is not reflected to primary current (Ip). Therefore, the leakage inductance by only a low circulating current stored in the primary transformer resonates with the capacitor (Cp) If the resonant peak voltage of V2 is larger than input voltage (Vin) or D2 is conducting after voltage of V4 reaches zero, the appropriate ZVS is achieved during right leg transition

Figure 7. Power Transfer

Figure 5. Right Leg Transition

Figure 8. Theoretical Waveforms of H-Bridge Transformer coupled DCDC converter

IV. E. Mode5. Linear current ramping When Q4 is turned on at time t5, this mode starts. Though Q4 and Q3 is conducting, the primary current is not applied

ANALYSIS AND DESIGN OF H-BRIDGE DC-DC CONVERTER

To reduce the parasitic ringing and voltage stress in the hard switching H-Bridge DC-DC converter, the proposed HBridge DC-DC gate signals for Q2 and Q4 are delayed (phase

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shifted) with respect to those of Q1 and Q3, so that during the time interval (t1-t2 or t5 - t6) where the secondary voltage is zero, one of the primary switches is always left on. This provides a low-impedance path for the current of the leakage inductance to circulate, thus solving the problem of the parasitic ringing associated with the hard switching HBridge DC-DC converter. A. Analysis of ZVS Operation The active power transfer period, which occurs from t0 to t1 where devices Q1,Q2 and DS1 conduct and also from t4 to t5,where devices Q3,Q4 and DS2 conduct. The null period, which occurs from t1 to t2 , where devices Q1, D4 and DS1 conduct, and also from T5to T6 , where devices Q3, D2and DS2 conduct. The duty cycle loss period is from T6 to T0 and T2 to T4. This last period of operation occurs when the primary current changes polarity. During this time, output diodes DS1 and DS2 must simultaneously conduct to maintain both transformer MMF balance and output current continuity. This clamps the secondary voltage to zero until the primary current fully reverses, even though the H-Bridge output voltage is nonzero. B. Duty Cycle Relationships Increasing the primary side inductance to increase the ZVS range reduces the primary current slew rate and increases this duty loss period. This duty loss, must be added to the effective duty cycle (phase shift) (this determines the actual voltage transfer ratio) to determine the total H-bridge duty cycle D, which is load current dependent. The effect must be taken into account at the design stage to ensure that the converter can achieve the target output across the entire input voltage and power throughput range. The expressions for these three duty cycle elements can be derived as follows. Assuming continuous conduction in the output filter, the filter current increases linearly during the active power transfer period according to

International Journal of Computer Information Systems, Vol. 3, No. 3, 2011 Now, the duty cycle loss is directly related to the primary inductor, the required change in primary current, and the applied DC link voltage, as D =

Equations can now be combined to derive an expression for the actual duty cycle that the H- Bridge must apply, which after some algebra can be shown to D = Deff + D (6) This well-known expression identifies the increase in duty cycle required for a given output as a function of the resonant inductor and transformer turns ratio. C. Design of Converter Components The design of a ZVS FB converter involves a tradeoff between critical issues turnoff losses caused by the IGBT tail current at high load, and the minimization of the duty cycle loss. These issues essentially determine the design selection of the ZVS capacitors, the series inductance, the transformer turns ratio to be used, which will now be discussed. D. ZVS Capacitor Selection The IGBTs have high turn- off switching loss due to longer fall time and tail current characteristics. To reduce turn-off switching loss, additional capacitors are needed in parallel with the IGBTs to reduce the rate of rise of switch voltage. However, it results in a reduction of the ZVS range for the converters. However this must be balanced against the limitation that at light load the primary side inductor cannot store sufficient energy to fully slew the phase leg voltage from one DC rail to the other at the phase leg transition. E. Transformer Turns Ratio and Resonant Inductor Selection The transformer turns ratio and the resonant inductor are designed by trading off between the objectives of maximizing the ZVS range and minimizing the duty cycle loss. IZVS = 2C SNUBVDC / LLK
2

2 f s Llk ( Ip1 Ip3 ) Vdc

(5)

{[ Ns / Np]Vdc Vo}Deff Ir = 2 fsLf

(2)

where fs is the converter switching frequency During the null and duty cycle loss periods, the output current will decrease linearly according to

Vo (1 Deff ) If= 2 fsLf

(7)

(3)

Since Ir = -a , If=a the effective duty cycle can be defined by combining above two equation Deff =

NpVo NsVdc

(4)

The above equation shows that a wide ZVS range can only be achieved if the resonant inductor is made large enough for the inductive energy to dominate over the stored snubber capacitance energy throughout the load range of interest. However, if the inductance is too large, the duty cycle loss becomes excessive. Since the maximum achievable duty cycle is fixed, this duty cycle loss leads to an increase in the

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transformer turns ratio (NS/NP), which increases the primary current, and, hence, the conduction & tail losses. V. SIMULATION RESULTS H-Bridge Transformer coupled DC-DC converter is simulated using PSIM and the results are presented in this section. The simulated results are based on PSIM at rated input voltage under rated load condition. Q2 and Q3 are synchronized with Q1 at the rising edging of Q1, in the middle of the turn-on period of Q1, and at the falling edging of Q1. Fig.9 shows the Simulation circuit for H-Bridge Transformer coupled DC-DC converter. Fig.10 shows the control circuit for H-Bridge Transformer coupled DC-DC converter. Fig.11 shows Vp, Ip, Vs & Is waveforms. Fig 12 shows Id1 waveforms. Fig.13 shows Id2 waveforms. Fig.14 shows Q2 and Q3 are synchronized with Q1 at the rising edge of Q1. Fig.15 shows Q2 and Q3 are synchronized with Q1 in the middle of the turn-on period of Q1. Fig.16 shows Q2 and Q3 synchronized with Q1 at the falling edge of Q1. Fig.17 shows Simulated voltage ripple of Vb at input voltage under the rated load on condition that Q2 and Q3 are synchronized with Q1 at the rising edge of Q1.Fig.18 shows Simulated voltage ripple of Vb at input voltage under the rated load on condition that Q2 and Q3 are synchronized with Q1 in the middle of the turn-on period of Q1. Fig.19 shows simulated voltage ripple of Vb at input voltage under the rated load on condition that Q2 and Q3 are synchronized with Q1 at the falling edge of Q1. Fig.20 shows simulated voltage ripple of Vo at input voltage under rated load on condition that Q2 and Q3 are synchronized with Q1 at the rising edge of Q1. Fig. 21 shows Simulated voltage ripple of Vo at input voltage under rated load on condition that Q2 and Q3 are synchronized with Q1 in the middle of the turn-on period of Q1. Fig. 22 shows Simulated voltage ripple of Vo at input voltage under rated load on condition that Q2 and Q3 are synchronized with Q1 at the falling edge of Q1 .

International Journal of Computer Information Systems, Vol. 3, No. 3, 2011

Fig 10. Control circuit for H-Bridge Transformer coupled DC-DC converter .

Fig 11. Vp,Ip,Vs & Is waveforms

Fig 12. Id1 waveforms

Fig .9 .Simulation circuit for H-Bridge Transformer coupled DC-DC converter. Fig 13. Id2 waveforms

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International Journal of Computer Information Systems, Vol. 3, No. 3, 2011

Fig. 14. Q2 and Q3 are synchronized with Q1 at the rising edge of Q1.

Fig. 18. Simulated voltage ripple of Vb at input voltage under the rated load on condition that Q2 and Q3 are synchronized with Q1 in the middle of the turn-on period of Q1

Fig. 15. Q2 and Q3 are synchronized with Q1 in the middle of the turn-on period of Q1.

Fig. 19. Simulated voltage ripple of Vb at input voltage under the rated load on condition that Q2 and Q3 are synchronized with Q1 at the falling edge of Q1.

Fig. 16. Q 2 and Q3 synchronized with Q1 at the falling edge of Q1.

Fig. 20. Simulated voltage ripple of Vo at input voltage under rated load on condition that Q2 and Q3 are synchronized with Q1 at the rising edge of Q1.

Fig. 17. Simulated voltage ripple of Vb at input voltage under the rated load on condition that Q2 and Q3 are synchronized with Q1 at the rising edge of Q1.

Fig. 21. Simulated voltage ripple of Vo at input voltage under rated load on condition that Q2 and Q3 are synchronized with Q1 in the middle of the turn-on period of Q1.

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International Journal of Computer Information Systems, Vol. 3, No. 3, 2011 [6] W. Chen, F. C. Lee, M. M. Jovanovic, and J. A. Sabat, A comparative study of a class of full bridge zero-voltageswitched PWM converters, in Proc. IEEE Applied PowerElectronicsConf.,1995,pp.89399. [7] S. Pendharkar and K. Shenai, Zero voltage switching behaviour ofpunch-through and non-punch-through insulated gate bipolar transistors (IGBTs), IEEE Trans. Electron Devices, vol. 45, no. 8, pp.18261835, Aug.1998. Fig. 22. Simulated voltage ripple of Vo at input voltage under rated load on condition that Q2 and Q3 are synchronized with Q1 at the falling edge of Q1 V. CONCLUSION Two-Stage H-Bridge Transformer coupled DC-DC converter is simulated using PSIM. Input DC is first converted to AC by an inverter and then ac is stepped down by a transformer which is then converted back to dc by diode rectifier. As the conversion has two stages, dc to ac and then ac to dc. The converter is controlled by phaseshifted square-wave modulation. Switching losses are reduced using by zero voltage switching. Switching stresses are reduced by using resonant inductor and capacitor This converter has advantages like higher output current, smaller transformer and reduced filter size. This converter can be used for battery charging and Electrolyser application. REFERENCES [1] Brendan Peter McGrath, Donald Grahame Holmes, Patrick John McGoldrick, Andrew Douglas McIver, Design of soft switched 6-KW Battery charger for traction application IEEE Trans on Power Electronics, VOL. 22, NO.4, July 2007. [2] J. A. Sabat, V. Vlatkovic, F. C. Lee, and B. H. Cho, Design considerations for high-voltage high-power fullbridge zerovoltage switched PWM converter, in Proc. IEEE Applied PowerElectronics Conf., 1998, pp. 275284. [3] J. M. Zhang, X. G. Xie, X. K. Wu, and Z. Qian, Comparison study of phase-shifted full bridge ZVS converters, in Proc. IEEE Power Electronics Specialists Conf., 2004, pp. 533539. [4] J. G. Cho, IGBT based zero voltage transition full bridge PWM onverter for high power applications, in Proc. IEE Elect. PowerAppl., Nov. 1996, vol. 143, no. 6, pp. 475 480. [5] J. G. Cho, J. A. Sabat, and F. C. Lee, Novel full bridge zerovoltage- transition PWM DC/DC converter for high power applications, in Proc. IEEE Applied Power Electronics Conf., 1994, pp. 143149. [8] A. Jangwanitlert, J. C. Balda, Phase-shifted PWM fullbridge DC/DC converters for automotive applications reduction of ringing voltages, IEEE Trans. Ind. Electron., vol. 52, no. 7, pp. 111-115, 2004. [9] A. Gorgerino, A. Guerra, D. Kinzer and J. Marcinkowski, Comparison of high voltage switches in automotive DC-DC converter, IEEEPCCON07, pp. 360367, 2007. [10] E. Hiraki, K. Yamamoto, T. Tanaka, T. Mishima and M. Nakaoka, An isolated bidirectional DC-DC converter based super-capacitor interface for automobile electric power systems, IEEE EPEPEMC06, pp. 722- 727, 2006. [11] Xuesong Jiang, Xuhui Wen and Haiping Xu, Study on isolated boost full bridge converter in FCEV, IEEE IPEC05, vol. 52, pp. 827-830, 2005. [12] G. Franceschini, E. Lorenzani, M. Cavatorta and A. Bellini, 3boost: A high power three phase step up full bridge converter for automotive applications, IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 173-183,2008. [13] Lee-Hun Kim, Kwang-Su Chun, Chung-Yuen Won, Soo-Seok Kim and Se-Wan Choi, An improved scheme for high-efficiency push-pull converter using single winding self-driven synchronous rectification, IEEE IECON04, vol. 2, pp. 999-1003, 2004. [14] G. R. Walker and P. C. Sernia, Cascaded DC/DC converter connection of photovoltaic modules, IEEE Trans. Ind. Electron., vol. 19, no. 4, pp. 1130-1139, 2004. [15] J. A. Morales-Saldana, E. E. C. Gutierrez and J. LeyvaRanos, Modeling of switch-mode dc-dc cascade converters, IEEE Trans. Ind. Electron., vol. 38, no. 1, pp. 295-299, 2002. [16] G. R. Walker and J. C. Pierce, Photovoltaic DC-DC module integrated converter for novel cascaded and bypass grid connection topologies design and optimization, IEEE PESC06, pp. 1-7, 2006.

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BIOGRAPHIES

R. Samuel Rajesh Babu has obtained his B.E degree from Madras University in 2003. He has obtained his M.E degree from Anna University in 2005. Presently he is doing his research at Sathyabama University. His area of interests is DC - DC converters. Dr. Joseph Henry has obtained his B.E Degree from Madras University in 1960.He obtained his M.E degree from IIT-Bombay in 1964. He obtained his Ph.D degree from IIT Delhi in 1978. Presently he is a professor in Vel Tech University. His areas of interest are Power Electronics and Digital Protection

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