Aerospace and Defense Symposium 2005

Amplifier Design in ADS for Radar

Applications

Presented by: HeeSoo LEE

 Aerospace and Defense Symposium 2005

Objectives
• Overview of a systematic medium power amplifier
design flow in ADS
• Overview of available tools and utilities in ADS for
amplifier design
• Demonstrate ADS co-simulation capability
• Demonstrate ADS layout for amplifier design

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Typical Block Diagram of a Radar System

Pulse
Transmitter Generator TIMING SYNC

PA

Local
Oscillator
RECEIVER
PROTECTOR

To
Display ADC and SYNCHRONOUS
Signal I/Q DETECTOR LNA
Processor
Receiver

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Power Amplifier in Radar System

• In this presentation, design
‰ 3 Watts medium output power two stage
power amplifier
‰ 20+dB gain at 1.95GHz frequency
‰ Overall, good input and output match
‰ Two separate amplifiers without inter-
stage matching

14.8 dBm 26.8 dBm 34.8 dBm

12 dB 8 dB

NE651R479A NE6510179A

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Power Stage Amplifier

Deliver 3 Watts

14.8 dBm 26.8 dBm 34.8 dBm

12 dB 8 dB

NE651R479A NE6510179A

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3 Watts HJ-FET NE6510179A

• NEC L&S band medium power HJ-FET
• Good for power stage transistor because of
– Typical 35dBm output power @5V
– Typical 10dB Gain at 1.9GHz
• Also ADS design kit is available with nonlinear models
– http://www.cel.com/prod/prod_ads_update.asp

Source: NEC

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Graphical Method of Determining Ropt*

• Ropt, the load impedance at drain terminal that
gives the maximum output power for devices* in
Class A operation Ids

(VBias-VKnee)2 Imax

Ropt =
2 x POut

• Easy to calculate
VKnee VBias Vmax Vds
• Reasonably accurate
• 2.67Ω Ropt with NE6510179A at 5V, 1.2A bias point
*
: Steve C. Cripps, RF Power Amplifier for Wireless communications
Artech House Publishers

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Modeling of FET Ground Pad Inductance

• Substrate on RT Duroid 5870, 31mil thick and ½ oz
• Model ground pad in preparation for determining the
optimal load impedance from a load-pull simulation
– Momentum EM Simulation to get S-parameters
– Calculation of Leff from Z-parameters: 0.163nH at 2GHz
Substrate
½ oz AIR
31 mil RT Duroid 5870

GND

Imaginary (Z11)
Leff =
Recommended ω
PCB Layout ADS Layout
for ground

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DesignGuides in ADS – Bridging the Gap

DesignGuides

Passive Linearization Amplifier

RF System Bluetooth Mixer Oscillator
Filter PLL
Simulation Applications
Technology
Amplifier, Filters
Linear, Nonlinear Mixers, Oscillator
Circuit Envelope Passives, System
Time Domain Mod/Demods
Agilent Ptolemy Packaging
Electromagnetic Others
Others

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What and Where to use DesignGuides

UWB

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Determine Optimum Load Impedance -

Load-Pull* Menu
1-Tone Nonlinear Simulations /
• Use Amplifier DesignGuides Load-Pull Load-Pull – PAE, Output Power
– Pre-configured simulation setup Contours

– Pre-configured data post-processing Complex Load Impedance

Simply replace it with

your own device!

Ground pad is
attached to the device!

*Also available in load-pull application guides

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Load-Pull Simulation Result

• Simulation maps complex load impedances to
power and PAE contours
• Pre-configured data display for gain
compression, PAE, harmonics and more
• Load reflection coefficient that gives maximum
power is at 0.924/-169.396

Load impedances is
mapped to Power
36dBm and PAE contours
35.5dBm

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Comparison of Graphical and Load-Pull Methods

A: 2.67 Ω B: 2.0 + j4.65 Ω
• Graphical Method
¾ DC only calculation
¾ 2.67 Ω
• Load-Pull Method
¾ Complete non-linear AC/RF simulation
¾ ΓRopt = 0.924/-169.396
¾ ZRopt = 2.0 + j*4.65 Ω
• Reasonable agreement but slightly different due to
– Where to look into the impedance
• Graphical method, at A plane: Drain terminal of intrinsic transistor
• Load-Pull method, at B plane: Drain terminal of extrinsic or packaged
transistor
– Package parasitic

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Determine Optimum Source Impedance –

Linear method Optimum transistor output
• No information on output power match for maximum power

but small signal gain Mapped input gain circle for

• Choice 1 : Conjugate match transistor’s output impedance

– Good for maximum gain

– Good for Input match
– Output match is question
• Choice 2: Mismatched input for
optimum output match
– Better output match with a little
loss of gain
– As an example, 0.936/-156.351
gives 1.4dB mismatch loss but
better match for output

Max Gain = 9.978dB at 1.95GHz

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Determine Optimum Source Impedance –

Source-Pull
Menu
• Use Amplifier DesignGuides Source-Pull
1-Tone Nonlinear Simulations /
– Pre-configured simulation setup Source-Pull – PAE, Output
– Pre-configured data post-processing Power Contours

– Brute-force solution for finding optimum source impedance

– Full understanding on output power with varying source
impedance
0.778/-159.090

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Stability
• NE6510179A is stable at 1.95GHz design frequency
with the addition of pad ground inductance
• Mu factor is over 1

Output Stability Circle

Input Stability Circle

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Matching Network Design

? ?

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Smith Chart Utility

• User interactive matching network design
• View frequency response
• View matching network topology
• Define Q of the circuit
• Build ADS schematic
• Easy to use

Source and Load Terminations

Series Components
Shunt Components
Transmission Line and Transformers

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Matching Utility
• Available network topologies
– Lowpass
– Highpass
– Bandpass
• Source/Load impedance can be
defined over wide frequency
range
• Matching element
transformation utility

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Output Matching Network Design

• Design with Smith Chart Utility
• Design for reflection coefficient from load-pull, ΓRopt 0.924/-169.396
• Ideal lumped passive and transmission line elements Display of Smith
Chart Utility

ΓRopt 0.924/-169.396
0.627 pF 59.85 deg Reflection Trajectory

50 Ohm

Enter conjugate of ΓRopt

5.6 pF for load termination

Q circle

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Input Matching Network Design

• Design with Smith Chart Utility
• Design for reflection coefficient from source-pull, ΓIN opt 0.778/-159.090
• Ideal lumped passive and transmission line elements

ΓIN opt 0.778/-159.090

1.37 pF 46 deg

50 Ohm

Conjugate of ΓINopt
3.3 pF for load termination

Input Match

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Impedance Loci with Different Width and

Length of Transmission Line
• Discrete SMT capacitance Input matching

value limits flexibility of design

• Parameter sweep simulation
capability allows designers to
understand Output matching

– Impedance loci of network

with varying physical
dimension
• Consider bandwidth of
network with each
combination
Output matching with different
capacitance Blue: 0.5pF, Red: 1.0pF

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Realization of Input and Output Networks

• Replace ideal capacitors with discrete vendor SMT capacitors
• SMT capacitors from Taiyo-Yuden
• ADS model library is available (Download from Web)
– http://66.40.41.39//simtools/index.cfm
59.85 deg 0.627 pF
1.37 pF 46 deg

50 Ohm 50 Ohm

3.3 pF
5.6 pF

1.2pF 1 pF

Physical Realization

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Linear Simulation With ADS Models

• Transmission lines in input and output matching networks
were chosen to be close to 50 Ω lines
• 7.81 dB small signal gain at 1.95GHz
• Excellent match for input and reasonable match for output

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Non-Linear Simulation with ADS Models

Menu
1-Tone Nonlinear Simulations /
• Use Amplifier DesignGuides’ pre-configured Spectrum,Gain,Harmonic
power simulation setup Distortion vs Power (w/PAE)

• Gain compression at 37.07dBm

• 38.24% PAE
• 7.81 dB small signal gain

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Linear Simulation with Momentum Component

• Layout look alike Momentum Component for physical layout
– Nested EM simulation for physical layout
– Accurate simulation for layout parasitics
– Overcome limitation of valid model range for circuit models
• Frequency response is shifted
Comparison with ADS model simulation

Shifted

Momentum Component

Solid = Layout Simulation

Faint Solid = ADS Models

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Detuned Matching Network

• Input and output impedances are detuned from desired
impedances due to physical layout parasitics Sprobe Component
• Very convenient SProbe simulation component

ΓIN opt ΓRopt

0.778/-159.090 0.924/-169.396

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Advanced Model Composer (AMC)

• component : tee_s : symmetrical tee
Momentum calculates S-data
model is function of : W3 W3
substrate
W12 frequency range freq freq

W3 layout parameters W12 & W3 W12 W12

single frequency continuous frequency
single W12, W3 single W12, W3

ADS Model Composer builds parameterized models for passive components

continuous frequency range & discrete and/or continuously varying layout parameters

W3 W3 W3

freq freq freq

W12 W12 W12

continuous frequency continuous frequency

continuous frequency
continuous W12
discrete W12 discrete W12
continuous W3
discrete W3 continuous W3

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AMC Model for In/Output Matching Network

Line Width
• Two perturbed parameters
Line Length
– Line width and length
• Once the model is developed,
AMC provides very fast
simulation speed without a
loss of accuracy Parameter Sweep
Simulation with AMC Input
Parameter Sweep
Simulation with AMC Output
Matching Network Model Matching Network Model

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Tuned Matching Network

• Input and output matching networks
are tuned for desired impedances
• Linear and Non-linear simulations are
performed
– Swept input power –20 to 30dBm

Gain Compression
36dBm, 4W

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Bias Circuit Design

• Transistor Bias Utility for biasing circuit for transistors
– Unregulated bias network for BJT and FET
– OPAMP based active biasing network up to 4 devices
– OPAMP based regulated biasing network up to 4 devices
• LineCalc Utility for synthesizing transmission lines
50 Ohm - 91 mil

31 mil RT Duroid 5870

Resistive bias network

Opamp based active bias
Opamp based regulated bias

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Linear Simulation with Bias Lines

• Bias lines for source and drain terminals are attached
• 8.179dB small signal gain at 1.95GHz
• Very good input and output return loss
Due to λ /4 lines

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Final Non-Linear Simulation

• 8.179dB gain at small signal
• 35.48dBm 1dB gain compression
• 35% PAE at 35.5dBm Pout

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Driver Stage Amplifier

Deliver 480 mW

14.8 dBm 26.8 dBm 34.8 dBm

12 dB 8 dB

NE651R479A NE6510179A

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1 Watt HJ-FET NE651R479A

• NEC L&S band medium power HJ-FET
• Good for driver stage transistor because of
– Typical 29.5dBm output power
– Typical 12dB Gain at 1.95GHz
• ADS design kit is available with nonlinear models
– http://www.cel.com/prod/prod_ads_update.asp

Source: NEC

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Load and Source Matching Network

• HJ-FET NE651R479A is biased at 5V, 250mA
• Optimum source and load impedances were
extracted from Load-Pull and Source-Pull Simulation

ΓIN opt 0.846/-153.444 ΓRopt 0.707/-169.644

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Linear Performance of Driver Amplifier

• 13.1dB small signal gain at 1.95GHz
• Good input and output return loss characteristic
Due to λ /4 bias lines

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Non-Linear Performance
• 1dB gain compression at 30.57dBm
• 41% PAE at 30.56dBm Pout
• 13.1 dB small signal gain

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Final Integration and Layout

Deliver 3 Watts

14.8 dBm 26.8 dBm 34.8 dBm

12 dB 8 dB

NE651R479A NE6510179A

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Linear Performance of Two Stage Amplifier

• Total 21.37dB small signal gain
• Good match for input and reasonable match for output
• Hierarchical design is employed with a sub-network

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Non-Linear Power Simulation Setup

• Use Amplifier DesignGuides’ pre-configured power simulation
setup
• Hierarchical design is employed with a sub-network

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Non-Linear Performance (1) Pre-configured data presentation

from Amplifier DesignGuides

Gain Compression
at 35.33 dBm

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Non-Linear Performance (2) - PAE

Pre-configured data presentation
• Overall 39.55% PAE from Amplifier DesignGuides

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Non-Linear Performance (3) - AM-to-PM

Pre-configured data presentation
from Amplifier DesignGuides

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ADS Layout for Two Stage Amplifier

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Co-Simulation of Power
Amplifier in Radar System

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Power of Co-Simulation in ADS Concept – Block Diagram

Top Level Radar System Using ADS Ptolemy

Transmitter System Using ADS Circuit Envelope

Baseband Float/Fixed Point

HDL(Verilog & VHDL), MatLab®
C++.System-C

Power Amp Circuit Using ADS EM-Circuit Co-simulation

Connected
Behavior RF/Analog Subsystem, Solution
Circuit, Transistor Level Models

Physical, EM Models, Circuit Models

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Transmitter Response with 2-Stage Power AMP

• 70 dB System Gain
• Double Conversion
• Simulated with Circuit Envelope

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Top Level Radar System Performance

with 2-Stage Power AMP

Target Distance & RCS

Top Level Radar System Design Using ADS Ptolemy

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Co-Simulation Result
LFM Chirp Source Spectrum

Transmitter Output Spectrum

Output to Dynamic
VSA Software

Click the graph to animate in slide show mode…

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Summary
• ADS provides an integrated and seamless design
environment for designing medium power amplifier
• ADS DesignGuides and Application Guides bridge
the gap between complex simulation technologies
and advanced applications
• ADS Momentum and Momentum Component
provide both accuracy and convenience for taking
into account physical layout parasitics
• ADS Co-Simulation capability allows “single click”
simulation for multiple simulation technologies and
various abstract level models

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