Digital V LSI Design

AJAY KUMAR SINGH

Senior Lecturer
Faculty of Engineering and Technology
Multimedia University (MMU), Malaysia

New Delhi-110001
2011
DIGITAL VLSI DESIGN
Ajay Kumar Singh

© 2011 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be
reproduced in any form, by mimeograph or any other means, without permission in writing from the
publisher.

ISBN-978-81-203-4187-6

The export rights of this book are vested solely with the publisher.

Published by Asoke K. Ghosh, PHI Learning Private Limited, M-97, Connaught Circus,
New Delhi-110001 and Printed by V.K. Batra at Pearl Offset Press Private Limited,
New Delhi-110015.
 Contents

Preface ix

1. A Review of Microelectronics 1–21

1.1 Introduction 1
1.2 CMOS Scaling Trends 3
1.2.1 Limitations of Scaling 5
1.3 Short Channel Effects (SCEs) 6
1.3.1 Drain-Induced Barrier Lowering (DIBL) 7
1.3.2 Gate Oxide Tunneling 7
1.3.3 Scaling of Gate Controlled Depletion Width (WD) 8
1.3.4 Gate Length 10
1.3.5 Effects of Random Dopant Distribution 10
1.3.6 Subthreshold Slope 11
1.4 Low Power Requirements 13
1.4.1 Sources of Power Dissipation 13
1.5 Leakage Current 16
1.5.1 Subthreshold Leakage 17
1.5.2 Gate Oxide Tunneling 19
Summary 20
Review Questions 20
Unsolved Numerical Problems 21
References 21

2. MOS Structure and Operation 22–64

2.1 Introduction 22
2.2 Structure of a MOSFET 23
2.3 Operation of MOSFET 26

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iv Contents

2.4 Threshold Voltage of MOSFET 27

2.4.1 Body Effect 29
2.4.2 Temperature Dependence of Threshold Voltage 31
2.5 A Qualitative Discussion for Inversion Region of MOS Device 31
2.6 MOSFET Current-voltage Characteristics 34
2.6.1 Long Channel MOS Device 34
2.6.2 Short Channel MOSFET 42
2.6.3 Effect of Channel Length Modulation on Drain Current 45
2.6.4 Subthreshold Characteristics 47
2.6.5 Effective Mobility of Carrier 48
2.7 CMOS Technology 52
2.7.1 Leakage Reduction 53
2.8 Needs for Low–Power Chips 54
2.9 MOS Capacitances 54
2.9.1 Bulk-drain Depletion Capacitor and Bulk-source Depletion
Capacitor 55
2.9.2 Gate Capacitances 58
Summary 60
Review Questions 61
Unsolved Numerical Problems 62
References 64

3. CMOS Fabrication Process 65–106

3.1 Introduction 65
3.2 Technological Advancement in MOSFET Fabrication Process 66
3.3 Silicon Crystal Manufacture 67
3.3.1 Czochralski (CZ) Growth Process 67
3.3.2 Wafer Preparation 69
3.3.3 Wafer Processing 72
3.3.4 Poly-silicon Gate Technology 81
3.3.5 Fabrication Process Flow for n-type MOSFET—Basic Steps 82
3.3.6 Short Channel MOS Design Concerns 85
3.4 CMOS 86
3.4.1 CMOS Fabrication Process 86
3.4.2 n-well Fabrication Process 87
3.4.3 Advanced CMOS Fabrication Technology 89
3.5 Layout and Design Rule 90
3.5.1 Micron Rules (Absolute Dimension) 92
3.5.2 Lambda Based Rules (Scalable Design Rules SCMOS) 92
3.5.3 Stick Diagram 95
Summary 101
Review Questions 103
Unsolved Numerical Problems 104
 Contents v
4. MOS Inverter and Its Characteristics 107–164
4.1 Introduction 107
4.2 Inverter 107
4.2.1 Resistive Load Inverter 112
4.2.2 Inverter with Active Load 118
4.3 Static CMOS Inverter 126
4.3.1 Static Behaviour of CMOS Inverter 129
4.3.2 Qualitative Discussion on Dynamic Behaviour of CMOS Inverter 138
4.4 Definition of Propagation Delay of Inverter 139
4.4.1 Calculation of Propagation Delay 140
4.4.2 Ring Oscillator Circuit 146
4.5 CMOS Inverter Power Dissipation 149
4.5.1 Power Delay Product (PDP) 152
4.5.2 Energy Delay Product 152
Summary 153
Review Questions 154
Unsolved Numerical Problems 157

5. Parasitic Capacitances and Resistances 165–192

5.1 Introduction 165
5.2 Input Capacitance 165
5.3 Interconnect Line/Wire 168
5.3.1 Interconnect Capacitance 170
5.3.2 Clock Signals 173
5.3.3 Clock Distribution 174
5.4 Parasitic Resistance 178
5.4.1 Interconnect Resistance 178
5.4.2 Channel Resistance 179
5.4.3 Contact Resistance 180
5.5 Impact of Resistance 181
5.5.1 Other Methods for Reducing IR Drop 182
5.5.2 Electromigration 182
5.6 RC Delay Model 185
5.6.1 Gate Delay 185
5.6.2 Interconnect Delay 185
5.6.3 Elmore Delay 186
5.6.4 Inductive Effects 188
Summary 189
Review Questions 190
Unsolved Numerical Problems 191

6. Combinational Static Logic Circuits 193–230

6.1 Introduction 193
6.2 MOS Logic 193
6.2.1 MOS Logic Circuits with Depletion Load 195
vi Contents

6.3 Complementary Logic 202

6.3.1 Two Input NOR Gate 203
6.3.2 Two Input NAND Gate 204
6.4 AOI and OAI Gates 207
6.5 Pseudo-nMOS Logic 208
6.6 Differential Voltage Logic Styles 212
6.7 Pass Transistor Logic (PTL) 214
6.8 Complementary Pass Transistor Logic (CPL) 219
6.9 Double Pass-Transistor Logic 222
6.9.1 Design Techniques for Large Fan-In 223
Summary 225
Review Questions 226
Unsolved Numerical Problems 227

7. Sequential Logic Circuits 231–261

7.1 Introduction 231
7.2 Sequential Logic Circuit 231
7.2.1 Difference between Sequential and Combinational Circuits 233
7.2.2 Multivibrator 233
7.3 Latch 235
7.3.1 SR Latch 236
7.3.2 Gated or Clocked SR Latch 238
7.3.3 D Latch 241
7.4 Flip-Flop 244
7.4.1 D Flip-Flop 244
7.4.2 D Flip-Flop with Enable 245
7.4.3 JK Flip-Flop 247
7.4.4 Master-Slave JK Flip-Flop 249
7.4.5 T-Flip-Flop 249
7.4.6 Flip-Flop with Clear and Preset Inputs 250
7.5 Registers and Counters 251
7.5.1 Counters 254
7.5.2 Binary Ripple Counter (Asynchronous Counter) 255
7.5.3 Synchronous Counter 256
7.5.4 Counters Based on Shift Register 256
Summary 258
Review Questions 258
Unsolved Explanation Problems 259

8. Dynamic Logic Gates 262–285

8.1 Introduction 262
8.2 Basic Principle of Dynamic Logic 262
8.2.1 Properties of Dynamic Gates 264
 Contents vii
8.3 Cascading Concern 267
8.3.1 Domino Logic 268
8.3.2 np Logic (NORA (NO RACE) Technique) 272
8.3.3 True Single Phase Clock (TSPC) Dynamic Logic 274
8.4 Dynamic Latches and Registers 276
8.4.1 Dynamic Transmission-Gate-Edge Triggered Registers 276
8.4.2 2
C MOS Register 278
8.4.3 True Single-Phase Clocked Register (TSPCR) 280
8.5 NORA CMOS Pipelined Circuit 282
Review Questions 284
Unsolved Numerical Problems 285

9. Semiconductor Memory 286–320

9.1 Introduction 286
9.2 Random Access Memory (RAM) 286
9.2.1 Dynamic RAM (DRAM) 287
9.2.2 Three-Transistor Dynamic Memory Cell (3-T DRAM Cell) 289
9.2.3 Other DRAM Cells 290
9.2.4 DRAM Architecture 292
9.2.5 Advantages and Disadvantages of DRAM Cell 294
9.3 Static Random Access Memory (SRAM) 294
9.3.1 Basics of SRAM 295
9.3.2 Conventional 6-T CMOS SRAM Cell 297
9.3.3 Design Methodology of SRAM Cell 300
9.3.4 Signal-to-Noise Margins (SNM) 302
9.3.5 Peripheral Devices of the SRAM Cell 304
9.3.6 Capacitance in Conventional SRAM 306
9.3.7 Sources of SRAM Power Consumption 306
9.4 Non-volatile Memory 309
9.4.1 ROM (Read Only Memory) 309
9.4.2 Floating-Gate Transistor 313
Summary 316
Review Questions 317
Unsolved Numerical Problems 320

10. Adder and Multiplier Circuits 321–343

10.1 Introduction 321
10.2 Adder Circuits 321
10.2.1 Half Adder (HA) Circuit 321
10.2.2 Full Adder (FA) Circuits 322
10.3 CMOS Adder’s Architectures 326
10.3.1 Ripple Carry Adder (RCA) 326
10.3.2 Carry Look-Ahead Adder (CLA) 327
10.3.3 Carry Select Adders (CSL) 329
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10.3.4 Carry Save Adder 330

10.3.5 Manchester Carry-Chain Adder 331
10.3.6 Carry Skip Adder 333
10.4 Subtractor 334
10.5 Multiplier 334
10.5.1 Carry Save Arithmetic Multiplier (CSM) 335
10.5.2 Braun Multiplier 335
10.5.3 Baugh-Wooley Multiplier 336
10.6 Arithmetic Logic Unit (ALU) 338
10.6.1 General Operation in ALU 339
10.6.2 1-bit ALU 340
Summary 343
Review Questions 343

Index 345–348
 Preface

The book provides a complete and comprehensive understanding of VLSI design engineering,
which ranges from CMOS (complementary MOS) logic to physical design automation.
It gives to the undergraduate students of engineering (Electrical and Electronics Engineering)
a sound foundation enabling them to know important questions such as what is VLSI and its
importance in digital integrated design, constraints for digital integrated design, various trade-
offs in design, etc. This book explains every term related to VLSI in great depth. To explain
the concepts clearly, many solved examples are included in every chapter. Besides solved
examples, each chapter contains many unsolved numerical questions. The important concepts
are highlighted in each chapter.
The book is organized into 10 chapters. A review of microelectronics in presented in
Chapter 1, which includes Moore’s Law, CMOS scaling and its limitations, short channel
effects, etc. Due to demand of portable devices in the market, low power VLSI design has
received a special attention by the designer. Due to design demand, low power design is also
discussed briefly in this chapter.
As we know, MOSFET (metal oxide semiconductor field effect transistor) is the basic
building block for any VLSI design and its knowledge is essential for the designer.
Chapter 2 discusses in detail the structure and operation of MOSFET MOS.
Chapter 3 deals with the fabrication of the MOSFET and CMOS. This chapter also discusses
the advancement in the fabrication areas and various fabrication steps involved. The silicon
crystal growth technique is included to explain how one gets wafer from silicon crystal.
Various processing steps in wafer preparation are described. To clear the concept of mask
preparation, layout and design rules are explained in great detail in this chapter. At the end
of this chapter, stick diagram is presented.
An inverter is the main building block for all digital circuit designs. The electrical properties
of complex circuits (like multipliers, adders, and microprocessor) can be easily explained
if one has a good understanding of inverter circuit. Chapter 4 focusses on MOS inverter and
its characteristics. It explains the various design techniques to implement the inverter circuit
like resistive load inverter, MOS inverter, CMOS inverter and pseudo-nMOS inverter.

ix
 Digital VLSI Design

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