Signed Binary Numbers When a fixed-point binary number is positive, the sign is represented by 0 and the snitude by a positive binary number. ‘When the number is negative, the sign is represented by 1 and the rest of the number may be represented in any one of three different ways. These are: 1. Sign-magnitude. 2. Sign-l’s complement. 3, Sign-2's complement. In the sign-magnitude representation, the magnitude is represented by a positive binary number. In the other two representations, the number is in either 1’s or 2’s complement. If the number is positive, the three representations are the same. ‘As an example, the binary number 9 is written below in the three representa- tions. It is assumed that a 7-bit register is available to store the sign and the magnitude of the number. +9 <9 Sign-magnitude 0 co1001. «1001001 Sign-I's complement 0 001001 t:‘110110 Sign-2's complement 0 001001 1 110111 A positive number in any representation has a 0 in the leftmost bit for a plus, followed by a positive binary number. A negative number always has a'1 in the leftmost bit for a minus, but the magnitude bits are represented differently. In the sign-magnitude representation, these bits are the positive number; in the V’s-com- plement representation, these bits are the complement of the binary number; and in the 2’s-complement representation, the number is in its 2’s-complement form. ‘The sign-magnitude representation of —9 is obtained from +9 (0 001001) by complementing oniy the sign bit. The sign-1’s-complement representation of —9 is obtained by complementing all the bits of 0 001001 (+9), including the sign bit. The sign-2’s-complement representation is obtained by taking the 2’s complement of the positive number, including its sign bit. Arithmetic Addition The reason for using the sign-complement representation for negative numbers will become apparent after we consider the steps involved in forming the sum of two signed numbers. The sign-magnitude representation is the one used in everyday calculations. For example, +23 and —35 are represented with a sign, followed by the magnitude of the number. To add these two numbers, it is necessary to 323ee ee 324 REGISTER-TRANSFER LOGIC CH.8 subtract the smaller magnitude from the larger magnitude and to use the sign of the larger number for the sign of the result, ic., (+23) + (—35) = — (35-23) = — 12. The process of adding two signed numbers when negative numbers are Tepresented in sign-magnitude’ form requires that. we compare their signs. If the two signs are the same, we aad tle tvo magnitudes. If the signs are not the same, we compare the relative magnitudes of the numbers and then subtract the smaller from the larger. It is necessary also to determine the sign of the result, This is a process that, when implemented with digital hardware, requires a sequence of control decisions as well as circuits that can compare, add, and subtract numbers. Now compare the above procedure with the procedure that forms the sum of two signed binary numbers when negative numbers are in 1’s- or 2's-complement representation. These procedures are very simple and can be stated as follows: Addition with sign-2’s-complement representation. The addition of two signed binary numbers with negative numbers represented by: their 2’s comple- ment is obtained from the addition of the two numbers including their : sign bits. A carry in the most significant (sign) bit is discarded. Addition with sign-I’s-complement representation. The addition of two signed binary numbers with negative numbers represented by their | s comple- ment is obtained from the addition of the two numbers, including their sign bits. If there is a carry out of the most significant (sign) bit, the result is incremented by | and its carry is discarded. Numerical examples for addition with negative numbers represented by their 2’s complement are shown below. Note that negative numbers must be initially in 2's-complement representation and that the sum obtained after addition is always in the required representation. se a - + 6 .. 0 000110 ~- 6 1111010 + + + 9 0 001001 + 9 0 001001 +15 0 001111 + 3 0 000011 + 6 0 000110 - 9 Tn - 1 110111 - 1 11011! = 3. 14101 - 18.1 101110 The two numbers in the four examples are added, including their sign bits. Any carry out of the sign bit is discarded, and negative results are automatically in their 2’s-complement form. ant a A | ' ~ ¢SEC. 8-5 FIXED-POINT BINARY DATA 325 The four examples are tepeated below with negative numbers Tepresented by their 1’s complement. The carry out of the sign bit is returned and added to the least significant bit (end-around carry), + 6 0 000110 eo 16 1 111001 + + 9 0001001 +9 0 001001 +15 0001111 10 000010 Cor 1 Aad 0 000011 + 6 0 000110" - 9 1 110110 + + me) 1 NOU - 9 1 10110 eu3 6 2A STON 11 101100 Cae ; : - 18 1 101101 The advantage of the sign-2’s-complement 1epresentation over the sign-1’s- complement form (and the sign-magnitude form) is that it contains only one type of zero. The other two representations have both a positive zero and a negative zero. For example, adding +9 to —9 in the 1I’s-complement representation, one obtains: +9 0 001001 9 1 110110 =, LV and the result is a negative zero, i.€., the complement of 0 000000 (positive zero), A zero with an associated sign bit will appear in a register in one of the following forms, depending on the representation used for negative numbers: +0 -0 In sign-magnitude 0 0000000 1 0000000 “In sign-1’s complement © 0000000. band In agn-2's complement 0 0000000 none — E22SEC. 8-6 OVERFLOW. 327 Because of the simple procedure for adding and subtracting binary numbers when. negative numbers are in sign-2's-complement form, most computers adopt this representation over the more familiar sign-magnitude form. The reason 2’s complement is usually chosen over the l’s complement is to avoid the end-around carry and the occurrence of a negative zero. 8-6 OVERFLOW When two numbers of n digits each are added and the sum occupies n + | digits, we say that an overflow occurs. This is true for binary numbers or decimal numbers whether signed or unsigned. When one performs the addition with paper and pencil, an overflow is not a problem, since we are not limited by the width of the page to write down the sum. An overflow is a problem in a digital computer because the lengths of all registers, including memory registers, are of finite length. A result of n + 1 bits cannot be accommodated in a register of standard length n. For this reason, many computers check for the occurrence of an overflow, and when it occurs, they set an overflow flip-flop for the user to check. An overflow cannot occur after an addition if one number is Positive and the other is negative, since adding a positive number to a negative number produces a result (positive or negative) which is smaller than the larger of the two original numbers. An overflow may occur if the two numbers are added and both are Positive or both are negative. When two numbers in sign-magnitude representation are added, an overflow can be easily detected from the carry out of the number bits. When two numbers in sign-2’s-complement representation are added, the sign bit is treated as part of the number and the end carry does not necessarily indicate an overflow. The algorithm for adding two numbers in sign-2's-complement representa- tion, as previously stated, gives an incorrect result when an overflow occurs. This arises because an overflow of the number bits always changes the sign of the result and gives an erroneous n-bit answer. To see how this happens, consider the following example. Two signed binary numbers, 35 and 40, are stored in two 7-bit Tegisters. The maximum capacity of the register is (2° — 1) = 63 and the minimum capacity is —2° = — 64, Since-the sum of the numbers is 75, it exceeds the capacity of the register. This is true if the numbers are both positive or both negative. The operations in binary are shown below together with the last two carries of the addition: carries: O 1 carries; 1 0 +35 0 100011 5 1 011101 +40 0101000 -40 1 011000 I> 1 001011 —S: 0 110101928 REGISTER-TRANSFER Logic CH.8 In either case, we See that the 7-bit result that should have been Positive is negative, and vice versa. Obviously, the binary answer is incorrect and the algorithm for adding binary numbers Tepresented in 2’s complement as stated Previously fails to Bive correct results when an overflow Occurs. Note that if the carry out of the sign-bit position is taken as the sign for the result, then the 8-bit answer so obtained will be correct. An overflow Condition can be detected by Observing the carry into the sign-bit position and the carry out of the sign-bit position. If these two carries are by means of an n-bit parallel adder. ‘The full-adder (FA) circuit in stage n (the sign bits) is shown explicitly. The carry Boing into this full-adder is C,,. The carry out Of the'Tulliadder is C, .,. The exclusive OR of these two carries is applied to an overflow flip-flop V. Tf, after the addition, = 0, then the sum loaded into A is Secet: TEV <1, there'is:an covertiow and the abit sum is incorrect. The circuit shown in Fig. 8-10 can be specified by the following statement: PACA BR VEC@ Ce The variables in the Statement are defined in Fig. 8-10. Note that variables C, and G,+1 do not represent registers; they represent Output carries from a parallel adder, aie Ay Load Register 4 Figure 810 Addition of sign-?s-complement numbersSEC. 8-11 INSTRUCTION CODES —339 An instruction code is a group of bits that tell the specifi ie i340 REGISTER-TRANSFER LOGIC cHe When the operation code 10010 is detected by the control unit, a command signal is applied to an adder Cireuit to add two numbers. The operation Part of an instruction code Specifies the operation to be Performed. This Operation must be executed on some data, usually stored in computer registers. An instruction code, therefore, must specify not only the operation but also the registers where the operands are to be found as well as the Tegister where the result is to be stored. These registers may be specified in an instruction code in two ways. A register is said to be specified explicitly if the instruction code contains special bits for its identification. For example, an instruc- register in the processor unit. It can be used to specify operations such as “clear a Processor register,” or “complement a register,” or “transfer the contents of one register to a second tegister.” The instruction format in (b) has an operation code followed by an operand. This is called an immediate operand instruction because the operand follows immediately after the operation-code part of the instruction. It eis peration-code (b) Immediate operand Operationcode’ ‘| Address of operand (c) Direct address Figure 8-12 Three possible instruction formatsEg A annem esac, SEC. 8-11 INSTRUCTION CODES 341 can be used to specify operations such as “add the operand to the present contents of a register” or “transfer the operand to a processor register,” or it can specify any other operation to be done between the contents of a register and the given operand. The instruction format specified in Fig. 8-12(c) is similar to the one in (b) except that the operand must be extracted from memory at the location specified by the address part of the instruction. In other words, the operation specified by the operation code is done between a Processor register and an operand which can be stored in memory anywhere. The address of this operand in memory is included in the instruction. Let_us assume that we have a memory unit with 8 bits per word and that an operation code contains 8 bits. The Placement of the three instruction codes in memory is depicted in Fig. 8-13. At address 25, we have an implied instruction that specifies an operation: “transfer the contents of processor register R into Processor register A.” This operation can be symbolized by the statement: AcR In memory addresses 35 and 36, we have an immediate operand instruction that occupies two words. The first word at address 35 is the operation code for the instruction, “transfer the operand to register 4,” symbolized as: A < operand The operand itself is stored immediately after the operation code at address 36. Address = Memory Operation 25 | 00000001 | op-code = 1 ASR 35 | 00000010 | op-code = 2 ‘A> Operand 36 | 00101100 | operand = 44 45 | 00000011 | op-code = 3 Ao MlAddress] 46 | 01000110 | address = 70 70 | 00011100 | operand = 28 Figure 813 Memory representation of instructionslm : Processor Logic Design i 9-1 INTRODUCTION OA prosesor unit is that part of a digital system or a digital computer that plements the operations in the system. It is comprised of a number of registers i and the digital functions that implement arithmetic, logic, shift, and transfer microoperations. The processor unit, when combined with a contfol unit that sup the sequence of microoperations, is called a central processor unit or ' PUT chapter is concerned with the organization and design of the processor unit. The next chapter deals with the logic design of the control unit. In Chapter it 11, we demonstrate the organization and design of a computer CPU. Some older computers came with only one processor register. In some cases a special-purpose digital system may employ a single processor register. However, since registers and other digital functions are inexpensive when constructed with integrated circuits, all recent computers employ a large number of processor registers and route the information among them through common buses. eration may be implemented in a processor unit either with a single microoperation or with a sequence of microoperations. For example, the multi- plication of two binary numbers stored in two registers may be implemented with a combinational circuit that performs the operation by means of gates. As soon as the signals propagate through the gates, the product is available and can be transferred to a destination register with a single clock pulse. Alternatively, the multiplication operation may be performed with a:sequence of add and shift microoperations. The method chosen for implementation dictates the amount and type of hardware in the processor tn ‘All computers. except the very Ja d fast ones, implement the involved operations by means of a sequence of microoperations. Ta this way, the processor 358960 PROCESSOR LOGIC DESIGN CHO 8-16 showed the various data paths for a particular, very limited processor. The gating of the data paths is achieved through the decoders and combinational circuit aa comprise the control section of the unit. ‘The control gates that formulate the given path are essentially multiplexers and decoders whose selection lines specify the required path The Processing of information is done by one common digital function wi data path can be specified with a set of common selection variables. A Processor unit that has a well-structured organization can be used in a wide variety of applications. If constructed within an integrated circuit, it becomes available to many users, each of which may have a different application. In this section, we investigate a few alternatives for organizing a general-pur- Pose processor unit. . The differences in organizations are mostly manifested in. the organization of the registers and their common path to the ALU. Bus Organization “We a large numberof registers are included in a Processor unit, it is most icient to connect them through common buses or arrange them as a small memoty having very fast access time. The registers communicate with each other not only for direct data transfers, but also while performing various microopera- tions. A bus organization for four processor registers is shown in Fig. 9-1. Each register is connected to two multiplexers (MUX) to form input buses A and B. The selection lines of each multiplexer select one register for the particular bus. The A “and B buses are applied to a common arithmetic logic unit. The function selected in the ALU determines the particular operation that is to be performed. The shift microoperations are implemented in the shifter. The result of the microoperation goes through the output bus S into the inputs of all registers. The destination register that receives the information from the output bus is selected by a decoder. When enabled, this decoder activates one of the register load inputs to provide a transfer path between the data on the S bus and the inputs of the selected destination register. The output bus S provides the terminals for transferring data to an external destination. One input of multiplexer A or B can receive data from the outsid environment when it is necessary to transfer external data into the processor sit The operation of the multiplexers, the buses, and the destination decoder explained in Section 8-2 in conjunction with Fig. 8-6. The ALU and shifter are discussed later in this chapter. A processor unit may have more than four registers. The construction of a bus-organized processor with more registers requires larger multiplexers and de- coder; otherwise, it is similar to the organization depicted in Fig. 9-1.Enable A select Destination select Arithmetic-logic unit (ALU) Output data Figure 9-1, Processor registers and ALU connected through common buses Input data Bselect Function select Shift select 361oe ee a ee 362 PROCESSOR LOGIC DESIGN cus ” : The control unit that supervises the Processor bus system directs the informa- tion flow through the ALU by selecting the various components in the unit. For example, to perform the microoperation: Rl= R2+ R3 the control must provide binary selection variables to the following selector inputs: 1. MUX A selector: to place the contents of R2 onto bus A. 2. MUX B selector: to place the contents of R3 onto bus B. 3. ALU function selector: to provide the arithmetic operation A + B. 4. . Shift selector: for direct transfer from the output of the ALU onto output bus S (no shift), 5. Decoder destination selector: to transfer the contents of bus S into RI. me five control selection variables must be generated simultaneously and must be available during one common clock pulse interval. The binary informa- tion from the two source registers propagates through the combinational gates in the multiplexers, the ALU, and the shifter, to the output bus, and into the inputs of the destination register, all during one clock pulse interval. Then, when the next clock pulse arrives, the binary information on the output bus is transferred into RI. To achieve a fast response time, the ALU is constructed wi arty look-ahead circuits and the shifter is implemented with combinational an ; hen enclosed in an IC package, a processor unit is sometimes called a register and arithmetic logic unit or RALU. It is also called by some vendors a bit-slice microprocessor. The prefix micro refers to the small physical size of the integrated circuit in which the processor is enclosed. Bit-slice refers to the fact that the processor can be expanded to a processor unit with a larger number of bits by using a number of ICs. For example, a 4-bit-slice microprocessor contains registers and ALU for manipulating 4-bit data. Two such ICs can be combined to construct an 8-bit processor unit. For a 16-bit processor, it is necessary to use four ICs and connect them in cascade. The output carry from one ALU is connected to the input carry of the next higher-order ALU, and the serial output and input lines of the shifters are also connected in cascade. A bit-slice microprocessor should be distinguished from another type of IC called a microprocessor. The former is a processor unit, whereas a microprocessor refers to an entire computer CPU enclosed in one IC package, Microprocessors and associated equipment are dis- cussed in Chapter 12. Scratchpad Memory The registers in a processor unit can be enclosed within a small memory unit. When included in a processor unit, a small memory is sometimes called a scratchpad memory. The use of a small memory is a cheaper alternative toSEC. 9-2 PROCESSOR ORGANIZATION 363 connecting processor registers through a bus system. The difference between the two systems is the manner in which information is selected for transfer into the ALU. Ina bus system, the information transfer is selected by the multiplexers that : form the buses. On the other hand, a single register in a group of registers organized as a small memory must be selected by means of an address to the memory unit. A memory register can function just as any other processor register as long as its only function is to hold binary information to be processed in the ALU. gh gorhoad memory should be distinguished from the main memory of the col 1. Contrary to the main memory which stores instructions and data, a small memory in a processor unit is merely an alternative to connecting a number ; of processor registers through a common transfer path. The information stored in : the scratchpad memory would normally come from the main memory by means of instructions in the program. Consider, for example, a processor unit that employs eight registers of 16 bits each. The registers can be enclosed within a small memory of eight words of 16 bits each, or an 8 X 16 RAM. The eight memory words can be designated RO through R7, corresponding to addresses 0 through 7, and constitute the registers for the processor Processor unit that uses a scratchpad memory is shown in Fig. 9-2. A source register is selected from memory and loaded into register A. A second source register is selected from memory and loaded into register B. The selection is done by specifying the corresponding word address and activating the memory- read input. The information in A and B is manipulated in the ALU and shifter. The result of the operation is transferred to a memory register by specifying its word address and activating the memory-write input control. The multiplexer in the input of the memory can select input data from an external source. Assume that the memory has eight words, so that an address must be specified with three bits: To perform: the operation: RIR24+ R3 the control must provide binary selection variables to perform the following ag microoperations: 2 T,: A M010} . _ fead R2 into register A T, B—M{O\} read R3 into register B T;, M[OOl)— 4+ B perform operation in ALU and transfer result to R Control function 7, must supply an address of 010 to the memory and activate the read and load A inputs. Control function T, must supply an address O}1 to the memory and activate the read and load B inputs. Control function T, must supply the function code to the ALU and shifter to perform an add operation (with noInput data Scratchpad Output data Load Load | Function select Shift select Figure 9-2. Processor unit employing a scratchpad memory shift), apply an address 001 to the memory, select the output of the shifter for the MUX, and activate the memory write input. The symbol M[xxx] designates a memory word (or register) specified by the address given in the binary number XXX. De Teason for a sequence of three microoperations, instead of just one as in a bus-organized processor, is due to the limitation of the memory unit. Since the memory unit has only one set of address terminals but two source registers are to be accessed, two accesses to memory are needed to read the source information. | The third microoperation ‘is needed to address the destination register. If the destination register is the same as the second source register, the control could activate the read input to extract the second-source information, followed by a write signal to activate the destination transfer, without having to change the address rae Some processors employ a 2-port memory in order to overcome the delay caused when reading two source registers. A 2-port memory has two separate address lines to select two words of memory simultaneously. In this way, the two source registers can be read at the same tim 364A address Scratchpad ALU and shifter Figure 9-3 Processor unit with a 2-port memory 1 organization of a processor unit with a 2-port scratchpad memory is shown in Fig. 9-3.* The memory has two sets of addresses, one for port A and the other for port B. Data from any word in memory are read into the A register by specifying an A address. Likewise, data from any word in memory are read into the B register by specifying a B address. The same address can be applied to the 4 address and the B address, in which case the identical word will appear in both A and B registers. When enabled by the memory enable (ME) input, new data can be written into the word specified by the B address. Thus the A and B addresses specify two source registers simultaneously, and the B address always specifies the destination register. Figure 9-3 does not show a path for external input and output data, but they can be included as in previous organizations. The A and B registers are, in effect, latches that accept new information as ~ long as the clock pulse, CP, is in the I-state. When CP goes to 0, the latches are disabled, and they hold the information that was stored when CP was a 1. This eliminates any possible race conditions that could occur while new information is being written into memory. The clock input controls the memory read and write operations through the write enable (WE) input. It also controls the transfers into the A and B latches. The waveform of one clock pulse interval is shown in the diagram. When the clock input is 1, the-A and B latches are open and accept the information coming from memory. The WE input is also in the I-state. This *This organization is similar to the 4-bit-slice microprocessor, type 2901.366 PROCESSOR Loci DESIGN CH.g RI-R1+ R2 can be done within one clock pulse Period. Memo with the B address, and R2 with the 4 addr Accumulator Register erations as well. In fact, the gates Associated with an accumulator Tegister provide all the digital functions found in an ALU. igure 9-4 shows the block diagram of a Processor unit that employs an to the A register and teplaces its previous content. The output from the 4 register may go to an external imation or into the Iput terminals of other Processor “nese un To form the sum of two numbers stored in Processor registers, it is necessaryInput data Processor registers or memory unit Select B source Aci register (4) Output data Figure 9-4 Processor with an accumulator register to add them in the A register using the following sequence of microoperations: Ty AO clear A THEA SRI transfer Rl to A T,;; AcA+R2 add R2to A Register A is first cleared. The first number in Rl is transferred into the A register by adding it to the present zero content of A. The second number in R2 is then added to the present value of A. The sum formed in A may be used for other computations or may be transferred to a required destination. 9-3 ARITHMETIC LOGIC UNIT An arithmetic logic unit (ALU) is a multioperation,.combinational-logic, digital function, It can perform a set of basic arithmetic operations and a set of logic operations. The ALU. has a number of selection lines to select a particular operation in the unit. The selection lines are decoded within the ALU so that k selection variables can specify up to 2‘ distinct operations. Figure 9-5 shows. the block diagram of a.4-bit ALU. The four data inputs from A are combined with the four inputs from B to generate an operation at the E 367