SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

D Quadruple Circuits Capable of Driving D OR N PACKAGE

High-Capacitance Loads at High Speeds (TOP VIEW)

D Output Supply Voltage Range From 5 V

VCC2 1 16 VCC1
to 24 V
1Y 2 15 4Y
D Low Standby Power Dissipation
1A 3 14 4A
D VCC3 Supply Maximizes Output Source 1E1 4 13 2E2
Voltage 1E2 5 12 2E1
2A 6 11 3A
description/ordering information 2Y 7 10 3Y
The SN75374 is a quadruple NAND interface GND 8 9 VCC3
circuit designed to drive power MOSFETs from
TTL inputs. It provides the high current and
voltage necessary to drive large capacitive loads
at high speeds.
The outputs can be switched very close to the VCC2 supply rail when VCC3 is about 3 V higher than VCC2. VCC3
also can be tied directly to VCC2 when the source voltage requirements are lower.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP (N) Tube of 25 SN75374N SN75374N
0°C
0 70°C
C to 70 C Tube of 40 SN75374D
SOIC (D) SN75374
Reel of 2500 SN75374DR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

logic diagram (positive logic)

4
1E1
5
1E2
12
2E1
13
2E2 2
3
1A
7
6
2A

10
11
3A
15
14
4A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

     !"   #!$% &"' Copyright  2004, Texas Instruments Incorporated
&!   #" #" (" "  ") !"
&& *+' &! #", &"  ""%+ %!&"
",  %% #""'

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1



   
 
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

schematic (each driver)

VCC1 VCC3 VCC2

To Other Drivers

Input A
Enable E1
Output Y
Enable E2

GND

To Other Drivers

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range (see Note 1): VCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 25 V
VCC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 30 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Peak output current, II (tw < 10 ms, duty cycle < 50%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Package thermal impedance, θJA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN NOM MAX UNIT
VCC1 Supply voltage 4.75 5 5.25 V
VCC2 Supply voltage 4.75 20 24 V
VCC3 Supply voltage VCC2 24 28 V
VCC3 − VCC2 Voltage difference between supply voltages 0 4 10 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −10 mA
IOL Low-level output current 40 mA
TA Operating free-air temperature 0 70 °C

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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

electrical characteristics over recommended ranges of VCC1, VCC2, VCC3, and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK Input clamp voltage II = − 12 mA −1.5 V
VCC3 = VCC2 + 3 V, VIL = 0.8 V, IOH = − 100 µA VCC2 − 0.3 VCC2 − 0.1
VCC3 = VCC2 + 3 V, VIL = 0.8 V, IOH = − 10 mA VCC2 − 1.3 VCC2 − 0.9
VOH High-level output voltage V
VCC3 = VCC2, VIL = 0.8 V, IOH = − 50 µA VCC2 − 1 VCC2 − 0.7
VCC3 = VCC2, VIL = 0.8 V, IOH = − 10 mA VCC2 − 2.5 VCC2 − 1.8
VIH = 2 V, IOL = 10 mA 0.15 0.3
VOL Low-level output voltage V
VCC2 = 15 V to 28 V, VIH = 2 V, IOL = 40 mA 0.25 0.5
Output clamp-diode
VF VI = 0, IF = 20 mA 1.5 V
forward voltage
Input current at
II VI = 5.5 V 1 mA
maximum input voltage
High-level Any A 40
IIH VI = 2.4 V µA
A
input current Any E 80
Low-level Any A −1 −1.6
IIL VI = 0.4 V mA
input current Any E −2 −3.2
Supply current from
ICC1(H) 4 8
VCC1, all outputs high
Supply current from VCC1 = 5.25 V, VCC2 = 24 V, VCC3 = 28 V,
ICC2(H) −2.2 0.25 mA
VCC2, all outputs high All inputs at 0 V, No load
Supply current from
ICC3(H) 2.2 3.5
VCC3, all outputs high
Supply current from
ICC1(L) 31 47
VCC1, all outputs low
Supply current from VCC1 = 5.25 V, VCC2 = 24 V, VCC3 = 28 V,
ICC2(L) 2 mA
VCC2, all outputs low All inputs at 5 V, No load
Supply current from
ICC3(L) 16 27
VCC1, all outputs low
Supply current from
ICC2(H) 0.25
VCC2, all outputs high VCC1 = 5.25 V, VCC2 = 24 V, VCC3 = 24 V,
mA
ICC3(H) Supply current from All inputs at 0 V, No load
0.5
VCC3, all outputs high
Supply current from
ICC2(S) 0.25
VCC2, standby condition VCC1 = 0, VCC2 = 24 V, VCC3 = 24 V,
mA
Supply current from All inputs at 0 V, No load
ICC3(S) 0.5
VCC3, standby condition
† All typical values are at VCC1 = 5 V, VCC2 = 20 V, VCC3 = 24 V, and TA = 25°C, except for VOH for which VCC2 and VCC3 are as stated under test
conditions.

switching characteristics, VCC1 = 5 V, VCC2 = 20 V, VCC3 = 24 V, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDLH Delay time, low- to high-level output 20 30 ns
tDHL Delay time, high- to low-level output 10 20 ns
tPLH Propagation delay time, low- to high-level output CL = 200 pF, 10 40 60 ns
RD = 24 Ω,
tPHL Propagation delay time, high- to low-level output See Figure 1 10 30 50 ns
tTLH Transition time, low- to high-level output 20 30 ns
tTHL Transition time, high- to low-level output 20 30 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3



   
 
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

PARAMETER MEASUREMENT INFORMATION

24 V
5V 20 V

Input VCC1 VCC2

VCC3
RD
Pulse
Output
Generator
(see Note A) CL = 200 pF
GND (see Note B)
2.4 V

TEST CIRCUIT

≤10 ns ≤10 ns

3V
90% 90%

Input
1.5 V 1.5 V
0.5 µs
10% t PHL 10% 0V
t DHL t PLH
t THL t TLH
VOH
VCC2 − 2 V VCC2 − 2 V
t DLH

Output

2V 2V
VOL

VOLTAGE WAVEFORMS

NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO ≈ 50 Ω .
B. CL includes probe and jig capacitance.

Figure 1. Test Circuit and Voltage Waveforms, Each Driver

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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
vs vs
HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
VCC2 VCC2
VCC1 = 5 V
VCC2 = VCC3 = 20 V
VOH − High-Level Output Voltage − V

VOH − High-Level Output Voltage − V

V1 = 0.8 V
− 0.5 −0.5
TA = 70°C

−1 −1
TA = 0°C TA = 25°C
− 1.5 −1.5 TA = 70°C

TA = 0°C
−2 −2

ÁÁ ÁÁ
ÁÁ ÁÁ
VCC1 = 5 V
VOH

VOH
− 2.5 VCC2 = 20 V −2.5
VCC3 = 24 V
VI = 0.8 V
−3 −3
− 0.01 − 0.1 −1 − 10 − 100 −0.01 −0.1 −1 −10 −100
IOH − High-Level Output Current − mA IOH − High-Level Output Current − mA

Figure 2 Figure 3

LOW-LEVEL OUTPUT VOLTAGE

vs
LOW-LEVEL OUTPUT CURRENT VOLTAGE TRANSFER CHARACTERISTICS
0.5 24
VCC1 = 5 V
VCC2 = 20 V
VOL − Low-Level Output Voltage − V

VCC3 = 24 V 20
0.4
VI = 2 V
− Output Voltage − V

TA = 70°C
16
0.3
TA = 0°C
12

ÁÁ
0.2

ÁÁ ÁÁ
8
VVO
O

ÁÁ
VCC1 = 5 V
VOL

VCC2 = 20 V
0.1

ÁÁ
4 VCC3 = 24 V
TA = 25°C
No Load
0 0
0 20 40 60 80 100 0 0.5 1 1.5 2 2.5
IOL − Low-Level Output Current − mA VI − Input Voltage − V

Figure 4 Figure 5

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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME PROPAGATION DELAY TIME
LOW- TO HIGH-LEVEL OUTPUT HIGH- TO LOW-LEVEL OUTPUT
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
250 250

225 CL = 4000 pF 225

VCC1 = 5 V CL = 4000 pF
VCC2 = 20 V

High− to Low−Level Output − ns

PLH − Propagation Delay Time,

PHL − Propagation Delay Time,

Low- to High−Level Output − ns

200 200
VCC3 = 24 V
RD = 24 Ω VCC1 = 5V
175 175 VCC2 = 20V
See Figure 1
VCC3 = 24V
150 CL = 2000 pF 150 RD = 24 Ω
See Figure 1 CL = 2000 pF
125 125

100 CL = 1000 pF 100

CL = 1000 pF
75 75
ttPLH

ttPLH
50 50
CL = 200 pF CL = 200 pF
25 25
CL = 50 pF
CL = 50 pF
0 0
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 6 Figure 7

PROPAGATION DELAY TIME PROPAGATION DELAY TIME

LOW-TO HIGH-LEVEL OUTPUT HIGH- TO LOW-LEVEL OUTPUT
vs vs
VCC2 SUPPLY VOLTAGE VCC2 SUPPLY VOLTAGE
250 250
VCC1 = 5 V VCC1 = 5 V
225 VCC3 = VCC2 + 4 V 225 VCC3 = VCC2 + 4 V
RD = 24 Ω CL = 4000 pF
PLH − Propagation Delay Time,

RD = 24 Ω CL = 4000 pF
Low- to High−Level Output − ns

High− to Low−Level Output − ns

PHL − Propagation Delay Time,

200 TA = 25°C 200

TA = 25°C
See Figure 1
175 175 See Figure 1

150 150
CL = 2000 pF CL = 2000 pF
125 125

100 100
CL = 1000 pF CL = 1000 pF
ttPLH

75 75
ttPLH

50 50
CL = 50 pF CL = 200 pF CL = 50 pF CL = 200 pF
25 25

0 0
0 5 10 15 20 25 0 5 10 15 20 25
VCC2 − Supply Voltage − V VCC2 − Supply Voltage − V

Figure 8 Figure 9

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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME PROPAGATION DELAY TIME
LOW- TO HIGH-LEVEL OUTPUT HIGH- TO LOW-LEVEL OUTPUT
vs vs
LOAD CAPACITANCE LOAD CAPACITANCE
250 250
VCC1 = 5 V VCC1 = 5 V
225 VCC2 = 20 V 225 VCC2 = 20 V
VCC3 = 24 V VCC3 = 24 V
PLH − Propagation Delay Time,

200 TA = 25°C 200 TA = 25°C

High− to Low−Level Output − ns

Low- to High−Level Output − ns

PHL − Propagation Delay Time,

See Figure 1 See Figure 1
175 175
RD = 24 Ω RD = 24 Ω
150 150
RD = 10 Ω RD = 10 Ω
125 125
RD = 0 RD = 0
100 100

75 75
ttPLH

ttPLH
50 50

25 25

0 0
0 1000 2000 3000 4000 0 1000 2000 3000 4000
CL − Load Capacitance − pF CL − Load Capacitance − pF

Figure 10 Figure 11

POWER DISSIPATION (ALL DRIVERS)

vs
FREQUENCY

VCC1 = 5 V
VCC2 = 20 V
VCC3 = 24 V
2000 Input: 3-V Square Wave
PD − Power Dissipation − mW

(50% duty cycle)

1800 TA = 25°C
1600
1400 CL = 600 pF
CL = 1000 pF
1200
1000 CL = 2000 pF

800
CL = 4000 pF
600
PT

400
CL = 400 pF
200
0
10 20 40 70 100 200 400 1000
f − Frequency − kHz

Figure 12
NOTE: For RD = 0, operation with CL > 2000 pF violates absolute maximum current rating.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7



   
 
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

THERMAL INFORMATION

power-dissipation precautions
Significant power may be dissipated in the SN75374 driver when charging and discharging high-capacitance
loads over a wide voltage range at high frequencies. Figure 12 shows the power dissipated in a typical SN75374
as a function of frequency and load capacitance. Average power dissipated by this driver is derived from the
equation:
PT(AV) = PDC(AV) + PC(AV) + PS(AV)

where PDC(AV) is the steady-state power dissipation with the output high or low, PC(AV) is the power level during
charging or discharging of the load capacitance, and PS(AV) is the power dissipation during switching between
the low and high levels. None of these include energy transferred to the load, and all are averaged over a full
cycle.
The power components per driver channel are:

( P H t H ) P Lt L)
P DC(AV) +
T
f
P C(AV) [ CV 2c

(P LHt LH ) P HLt HL)

P S(AV) +
T
where the times are as defined in Figure 15.
t LH t HL

tH

tL
T = 1/f

Figure 13. Output-Voltage Waveform

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265



   
 
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

THERMAL INFORMATION

power-dissipation precautions (continued)

PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, and C is the load capacitance.
VC is the voltage across the load capacitance during the charge cycle shown by the equation:
VC = VOH − VOL
PS(AV) may be ignored for power calculations at low frequencies.
In the following power calculation, all four channels are operating under identical conditions: f = 0.2 MHz,
VOH = 19.9 V and VOL = 0.15 V with VCC1 = 5 V, VCC2 = 20 V, VCC3 = 24 V, VC = 19.75 V, C = 1000 pF, and the
duty cycle = 60%. At 0.2 MHz for CL < 2000 pF, PS(AV) is negligible and can be ignored. When the output voltage
is low, ICC2 is negligible and can be ignored.
On a per-channel basis using data-sheet values,

P DC(AV) + ƪ5 Vǒ4 mA
4
Ǔ ) 20 Vǒ−2.24 mAǓ ) 24 Vǒ2.24mAǓƫ 0.6 )

ƪ5 Vǒ314mAǓ ) 20 Vǒ0 mA
4
Ǔ ) 24 Vǒ16 4mAǓƫ 0.4
PDC(AV) = 58.2 mW per channel
Power during the charging time of the load capacitance is
PC(AV) = (1000 pF)(19.75 V)2(0.2 MHz) = 78 mW per channel
Total power for each driver is:
PT(AV) = 58.2 mW + 78 mW = 136.2 mW
The total package power is:
PT(AV) = (136.2)(4) = 544.8 mW

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9



   
 
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

driving power MOSFETs

The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The
input impedance of an FET consists of a reverse-biased PN junction that can be described as a large
capacitance in parallel with a very high resistance. For this reason, the commonly used open-collector driver
with a pullup resistor is not satisfactory for high-speed applications. In Figure 14a, an IRF151 power MOSFET
switching an inductive load is driven by an open-collector transistor driver with a 470-Ω pullup resistor. The input
capacitance (CISS) specification for an IRF151 is 4000 pF maximum. The resulting long turn-on time, due to the
product of input capacitance and the pullup resistor, is shown in Figure 14b.
48 V

5V M 4

VOH − VOL − Gate Voltage − V

470 Ω
3

4 8 2
IRF151
7
3
TLC555 1
6 5

2 1 1/2 SN75447
0
0 0.5 1 1.5 2 2.5 3
t − Time − µs
(a) (b)

Figure 14. Power MOSFET Drive Using SN75447

A faster, more efficient drive circuit uses an active pullup, as well as an active pulldown output configuration,
referred to as a totem-pole output. The SN75374 driver provides the high-speed totem-pole drive desired in an
application of this type (see Figure 15a). The resulting faster switching speeds are shown in Figure 15b.
48 V

5V
M
4
VOH − VOL − Gate Voltage − V

3
4 8
7 2
3
TLC555 IRF151
6 5
1/4 SN75374
1
2 1

0
0 0.5 1 1.5 2 2.5 3
t − Time − µs
(a) (b)

Figure 15. Power MOSFET Drive Using SN75374

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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

driving power MOSFETs (continued)

Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as
shown by the equation:

I PK + VC
tr

where C is the capacitive load and tr is the desired rise time. V is the voltage that the capacitance is charged
to. In the circuit shown in Figure 14a, V is found by the equation:
V = VOH − VOL

Peak current required to maintain a rise time of 100 ns in the circuit of Figure 14a is:
(3 * 0)4(10 −9)
I PK + + 120 mA
100(10 −9)

Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151.
With a VCC of 5 V and assuming worst-case conditions, the gate drive voltage is 3 V.
For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, VCC3 should be at least
3 V higher than VCC2.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN75374D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75374 Samples

SN75374DE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75374 Samples

SN75374DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75374 Samples

SN75374DRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75374 Samples

SN75374N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75374N Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75374DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75374DR SOIC D 16 2500 340.5 336.1 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN75374D D SOIC 16 40 507 8 3940 4.32
SN75374DE4 D SOIC 16 40 507 8 3940 4.32
SN75374N N PDIP 16 25 506 13.97 11230 4.32

Pack Materials-Page 3
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