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Lecture 1

1) The document defines key concepts in CMOS logic gates including voltage transfer characteristics, noise margins, propagation delay, and power dissipation. 2) It summarizes that static power dissipation in CMOS gates is zero, while dynamic power is proportional to switching frequency and load capacitance. 3) Delay is proportional to the load capacitance divided by the drive strength of the transistors as determined by their dimensions. Matching transistor sizes optimizes switching behavior.

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124 views17 pages

Lecture 1

1) The document defines key concepts in CMOS logic gates including voltage transfer characteristics, noise margins, propagation delay, and power dissipation. 2) It summarizes that static power dissipation in CMOS gates is zero, while dynamic power is proportional to switching frequency and load capacitance. 3) Delay is proportional to the load capacitance divided by the drive strength of the transistors as determined by their dimensions. Matching transistor sizes optimizes switching behavior.

Uploaded by

amrsalah40820
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DC Operation

Voltage Transfer Characteristic VTC

VO

Slope=-1
V
OH
VO=VI

VM Switching Threshold
Slope=-1
V OL

V OL VIL VIH V VI
OH

Nominal Voltage Levels


V
V
out
“ 1” OH
V Slope = -1
V OH
IH

Undefined
Region

V
IL
Slope = -1

“ 0”
V
V
OL
OL
V V V
IL IH in
Definition of Noise Margins
NMH=VOH-VIH NML=VIL-VOL Ideal inverter
NMH=NML=VDD/2
"1" VM=VDD/2
V
OH
NM H Noise margin high
V
IH
Undefined
Region
NM L V
V
OL
IL Noise margin low

"0"

Gate Output Gate Input


Delay Definitions (Propagation Delay)

V in
tP=1/2(tPLH+tPHL)

½(VOL+VOH) 50%

tpHL tpLH
V out
90%

50%

10% t
tf tr
Power Dissipation

Static: In the absence of switching (power supply to ground)

Dynamic: driving a load capacitance

PD = f C VDD2

Delay Power product

Figure of merit DP = PD tP
The MOS Transistor
CMOS Inverter

V DD

RDSP RDSP =1 / [k’p(W/L)p(VDD-Vt)]

V out

RDSN =1 / [k’n(W/L)n(VDD-Vt)]
RDSN
Static Operation

When vI = 0 vO = VOH = VDD


vI = VDD vO = VOL = 0
Static current and static power dissipation = 0
Output voltage swing 0 to VDD ( Maximum)

CMOS inverter can be made to switch at the midpoint of the


Logic swing, 0 to VDD, that is VDD/2 by approximately sizing
The transistors

Vth= VDD - |Vtp| + (kn/kp)1/2 Vtn


1+ (kn/kp)1/2

kn = k’n(W/L)n kp = k’p(W/L)p

When Vtn = |Vtp| , Vth = VDD for kn = kp


Matching k’n(W/L)n = k’p(W/L)p

µn is 2 to 3 times larger than µp

Matching is achieved by making (W/L)p 2 to 3 times (W/L)n

(W/L)p = µn/ µp (W/L)n The two devices have same L

Minimum width of the NMOS is 1.5 to 2 times L


Minimum width of the PMOS is 2 to 3 times L
Ex: for a 1.2 µm process (µn/ µp) = 3
L = 1.2 µm (W/L)n = 1.8/1.2 (W/L)p = 5.4/1.2

Inverter area WnLn +WpLp = (Wn+Wp) L


Fan-in and Fan-out

M
N

Fan-out N Fan-in M
Dynamic Behavior of MOS Transistor
G

C gs C gd

S D

C sb Cg C db

B
The Gate Capacitance
Polysilicon gate

Source Drain
W
n+ xd xd n+

Gate-bulk
Ld
overlap
Top view

Gate oxide
tox
n+ L n+

Cross section
VDD
Q2 Cdb2 Q4
Cgd2

Q3
Q1
Cgd1 Cw
Cdb1
Equivalent load capacitance
1. Gate drain overlap capacitance of Q1
equivalent cap. Between output and ground 2Cgd1
Q2 -------- 2Cgd2
2. Drain body Cdb1 and Cdb2

3. Cg3 and Cg4 Cg3 + Cg4 = (WL)3 Cox +(WL)4Cox

4. Wiring capacitance Cw

C = 2Cgd1+2Cgd2+Cdb1+Cdb2+Cg3+Cg4+Cw
iDN
VDD VDD
vI
C
Q1 VDD/2
0 t
tpHL t
(a)

VDD
VDD Q2 VDD
vI
VDD/2
0 t C
tpLH t
(b)
(a) QN discharges C from VDD to 0
initially QN will be in saturation and when Vo falls below
VDD-Vt will go into triode mode.

Approximate expression of tpHL

tpHL = (1.6 C)/ [k’n (W/L)n VDD]

Vt ≈ 0.2 VDD
Alternative method
iDN at t = 0 to t = tpHL
t = 0 QN saturation iDN(0) = ½ k’n (W/L)n (VDD-Vt)2
t = tpHL QN in triode mode
iDN(tpHL) = k’n(W/L)n [(VDD-Vt) VDD/2 -1/2 (VDD/2)2]

iDN|avg = ½ [iDN(0) + iDN(tpHL)]


tpHL = C ∆v/ iDN|avg = (C VDD/2) / iDN|avg

for Vt ≈ 0.2VDD tpHL = (1.7 C) / [k’n(W/L)n VDD]

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