25-10-2023

Switching Power Dissipation of CMOS Inverters

• CMOS Inverter static power dissipation is zero (negligible) since the CMOS
inverter does not draw any significant current from the power source in
both of its steady-state operating points (i.e when Vout = VOH= VDD : PMOS
–ON ,NMOS-OFF and for Vout = VOL= VSS or Gnd: PMOS-OFF, NMOS-ON)

• During switching (dynamic)events when the output voltage changes from a

low to high state, or from a high to low state (i.e. when the output load
capacitance is charged up or charged down) , the CMOS inverter inevitably
dissipates power.

Typical input and output voltage waveforms and the capacitor

current waveform during switching of the CMOS inverter.

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 25-10-2023

• When the input voltage switches from low to high, the pMOS
transistor in the circuit is turned off, and the nMOS transistor starts
conducting. During this phase, the output load capacitance Cload is
being discharged through the nMOS transistor. Thus, the capacitor
current equals the instantaneous drain current of the nMOS
transistor.
• When the input voltage switches from high to low, the nMOS
transistor in the circuit is turned off, and the pMOS transistor starts
conducting. During this phase, the output load capacitance Cload is
being charged up through the pMOS transistor; therefore, the
capacitor current equals the instantaneous drain current of the pMOS
transistor.

• Assuming periodic input and output waveforms, the average power

dissipated by any device over one period can be found as follows:

• Since during switching, the nMOS transistor and the pMOS transistor in a
CMOS inverter conduct current for one-half period each, the average
power dissipation of the CMOS inverter can be calculated as the power
required to charge up and charge down the output load capacitance.

Using ∫ x dx = x2/2 + C

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 25-10-2023

• The average power dissipation of the CMOS inverter is proportional to the

switching frequency, f. Therefore, the low-power advantage of CMOS circuits
becomes less prominent in high-speed operation (!!), where the switching
frequency is high.
• The average power dissipation is independent of all transistor characteristics and
transistor sizes.
• Pavg α VDD2

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 27-10-2023

DC Transfer
Characteristics of
static CMOS
Inverter

Static CMOS Inverter : DC Transfer Characteristic

 DC Transfer characteristic: Plot of Vout vs. Vin (i.e Voltage Transfer

Curve [VTC]) for a gate
 CMOS Inverter
– When Vin = 0 -> Vout = VDD
VDD
– When Vin = VDD -> Vout = 0
Idsp
Vin Vout
– For input between 0 and VDD , Idsn
Vout depends on the region of operation
of NMOS and PMOS devices. CMOS Inverter

CMOS VLSI Design 4th Ed. 2

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 27-10-2023

Transistor Operation in CMOS Inverter

 By KCL, Idsn = |Idsp|

 Current depends on region of transistor operation
 For what value of Vin nMOS and pMOS operates in VDD
– Cutoff?
Idsp
– Linear? Vin Vout
– Saturation? Idsn

CMOS Inverter

CMOS VLSI Design 4th Ed. 3

Graphical derivation of CMOS inverter DC characteristic

Vgsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

The plot shows Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and
Vgsp.

CMOS VLSI Design 4th Ed. 4

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 27-10-2023

Plot of Idsn and | Idsp| in terms of Vout for various values of Vin.

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

CMOS VLSI Design 4th Ed. 5

Mark with dots, the values of Vout where Idsn = | Idsp| for a given value
of Vin

Vin0 Vin5

Vin1 Vin4

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

CMOS VLSI Design 4th Ed. 6

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 27-10-2023

DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot to obtain the inverter DC
characteristic.

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 7

Operating Regions of MOSFETs in CMOS Inverter

VDD

Vin Vout

CMOS Inverter DC Transfer

Curve

CMOS VLSI Design 4th Ed. 8

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 27-10-2023

Current IDD (= Idsn = | Idsp|) versus Vin in CMOS inverter !!!!

The plot indicates

that both transistors
are momentarily ON
as Vin passes
through voltages
between GND and
VDD, resulting in
a pulse of current
drawn from the
power supply.

CMOS VLSI Design 4th Ed. 9

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 01-11-2023

CMOS Inverter Input threshold voltage, Vinv

• Vinv or mid-point voltage: It is the input voltage at which

output changes from one state to another.
• It corresponds to region C on the DC characteristics at which
Vin= Vout = Vinv
• Intersection of DC characteristic with Vin= Vout
characteristic represented as a line with slope of 450 ,
through the origin).

• In region C, both PMOSFET and NMOSFET are in Saturation

CMOS VLSI Design 4th Ed. 1

CMOS Inverter Input threshold voltage contd.

 KCL at the inverter output node, Idsn + Idsp = 0

i.e. Idsn = - Idsp ------(1)
VDD
 In the circuit,
Vgsn=Vin and Vgsp=Vin-VDD Idsp
Vin Vout
and Vin = Vinv I dsn

Substitute in eqn (1) and solve for Vinv.

CMOS VLSI Design 4th Ed. 2

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CMOS Inverter Input threshold voltage contd.

VDD+Vtp+Vtn 𝛽𝑛
𝛽𝑝 VDD+Vtp+Vtn 1

 Vinv = 𝛽𝑛
 Vinv = 1
𝑟

1+ 1+
𝑟
𝛽𝑝

𝛽𝑝 kp’ (W/L)𝑝
Where r = =
𝛽𝑛 kn’ (W/L)𝑛

𝛽𝑝 kp’ (W/L)𝑝
 Vinv depends on =
𝛽𝑛 kn’ (W/L)𝑛
i.e. Vinv depends on ratios of aspect ratios.(Aspect ratio->W/L ratio)
𝛽𝑝
 With Vtn= -Vtp and = 1, Vinv= VDD/2 -- Symmetric VTC i.e
𝛽𝑛
Logic LOW input range: From 0 to VDD/2 and,
Logic HIGH input range: From VDD/2 to VDD
CMOS VLSI Design 4th Ed. 3

Inverter device sizes for Symmetric VTC

𝛽
 For symmetric VTC, 𝛽𝑝 = 1
𝑛

kp’ (W/L)𝑝 µp Cox (W/L)P

i.e =1  =1
kn’ (W/L)𝑛 µn Cox (W/L)𝑛
 µn Cox (W/L)n = µp Cox (W/L)P
 µn (W/L)n = µp (W/L)P
≈> 3 µp (W/L)n = µp (W/L)P
 (W/L)p = 3( W/L)n
i.e. For symmetric VTC, PMOSFET should be 3 times
bigger in size than NMOSFET => Keep Lp=Ln=L and
Wp=3 Wn

CMOS VLSI Design 4th Ed. 4

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Dependence of inverter threshold voltage on Beta Ratio

 If bp / bn  1, switching point Vinv will move away from VDD/2

βp > βn  PMOS bigger than NMOS
Vinv>VDD/2

βp = βn  PMOS is 3 times (approx.) bigger

than NMOS Vinv=VDD/2

βp < βn PMOS smaller than NMOS

Vinv<VDD/2

CMOS VLSI Design 4th Ed. 5

Solving Numerical on inverter threshold voltage

Calculate the mid-point voltage of inverter with power supply

of 3.3 V,(W/L)n =10,(W/L)p = 14, kn’ =100 µA/V2, kp’ =42 µA/V2,
Vtn = 0.7 V, Vtp = - 0.8 V.

Calculate βn/βp
βn/βp = 1.7
Calculate VM
VM= 1.48 V

CMOS VLSI Design 4th Ed. 6

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 06-11-2023

Noise Margin
 Noise margin is closely related to the DC voltage characteristics (VTC).
 Noise margin (noise immunity) indicate the allowable noise voltage on
the input of a gate so that the output will not be corrupted : How much
noise at the input, a gate can tolerate.
 Noise margin is expressed as
NML : Noise margin for LOW
NMH : Noise margin for HIGH

DC and Transient Response CMOS VLSI Design 4th Ed. 1

Noise Margin for LOW : NML

• NML = VIL - VOL ,

where VIL = Maximum value of input voltage considered
as LOW
VOL = Maximum value of output voltage
considered as LOW.
NML is defined as the difference between
maximum LOW input voltage recognized by the
receiving gate (In figure, inverter 2) and the
maximum LOW output voltage produced by the
driving gate (In figure, inverter 1) .

DC and Transient Response CMOS VLSI Design 4th Ed. 2

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Noise Margin for HIGH : NMH

• NMH = VOH - VIH ,

where VOH = Minimum value of output voltage
considered as HIGH
VIH = Minimum value of input voltage
considered as HIGH

NMH is defined as the difference in minimum HIGH

output voltage of the driving gate and the minimum
HIGH input voltage recognized by the receiving
gate

DC and Transient Response CMOS VLSI Design 4th Ed. 3

Noise Margin (Contd.)

 Inputs between VIL and VIH are said to be in the indeterminate region or
forbidden zone and do not represent legal digital logic levels. Therefore,
it is generally desirable to have VIH as close as possible to VIL.

 If either NML or NMH for a gate are too

small, the gate may be disturbed by
noise that occurs on the inputs.
Hence it is desirable to have high
noise margins.

DC and Transient Response CMOS VLSI Design 4th Ed. 4

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 06-11-2023

Noise Margin (Contd.)

DC and Transient Response CMOS VLSI Design 4th Ed. 5

3
 10-11-2023

RC Delay Model
• IC : Working Chip – perform intended function
• Making working chip “work well”:
• Performance metrics: Speed (delay), Power,
Area
• MOSFETs exhibits non-linear I- V characteristics.
(Recall ID expressions for long-channel device),
analysis is complex and tedious.
• Solution: Develop linear model of the MOSFET (This
approximation works remarkably well for delay
estimation)
10-11-2023 VLSI Design 1

RC Model of NMOSFET: The RC delay model

treats a MOSFET as a switch in series with a resistor.

10-11-2023 VLSI Design 2

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RC Model of NMOSFET contd.

where βn = µn Cox (W/L)n
• The value of R depends on the
device aspect ratio, (W/L):
Increase in W decrease Rn

Rn is typically on the order

• The resistance of two
transistors in series is the
of 10 kΩ
sum of the resistances of
each transistor. If width of channel, Wn is
• A pMOS transistor has
increased by k ,
greater resistance, 2R, • Rn decrease by k
because of its lower • Capacitance increase by k
mobility.

Gate and Diffusion Capacitance

• Each transistor has gate and diffusion capacitance.
• A transistor of k times unit width has capacitance
kC.
• Diffusion capacitance depends on the size of the
source/drain region.
• Wider transistors have proportionally greater diffusion
capacitance.
• Increasing channel length increases gate
capacitance proportionally but does not affect
diffusion capacitance.
• C for a minimum length transistor is 1fF/µm of
width.
• In a 65 nm process with a transistor being 0.1 µm wide, C is
thus about 0.1 fF

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 10-11-2023

Equivalent RC circuit models for nMOS and pMOS

transistors of width ‘k’

Scaled
Scaled
NMOS
PMOS

10-11-2023 VLSI Design 5

Unit Inverter (Reference Inverter)

With Vtn = | Vtp| , Rp = Rn if

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 10-11-2023

Reference Inverter

Reference Inverter with Rp = Rn

To make resistance of PMOS equal to that of NMOS, PMOS width is made

twice that of NMOS width

10-11-2023 VLSI Design 7

Capacitance load to first inverter X1 (node B) in a

cascade of 2- inverters (X1 in cascade with X2)

Refer next page for desription

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 10-11-2023

Load Capacitance of an inverter, X1 driving another inverter,

X2
• There are diffusion capacitances between the drain and body
of each transistor and between the source and body of each
transistor: Cdb and Csb .
• The gate capacitance Cgs of the transistors in X2 are part of
the load.
• The wire capacitance is also part of the load.
• The gate capacitance of the transistors in X1 and the diffusion
capacitance of the transistors in X2 do not matter because
they do not connect to node B.
• The source-to-body capacitors Csbn1 and Csbp1 have both
terminals tied to constant voltages and thus do not contribute
to the switching capacitance.
• For all ac purposes(with DC grounded), all the capacitances are
lumped into a single capacitance, Cout.
10-11-2023 VLSI Design 9

Equivalent Circuit for inverter output (Y) fall transition: NMOS-

ON, PMOS-OFF

Equivalent Circuit
To make resistance of
PMOS equal to that of
NMOS, PMOS width is
made twice that of
NMOS width

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 10-11-2023

.
Example 4.2:Draw the schematic a 3-input NAND gate with
transistor widths chosen to achieve effective rise and fall
resistance equal to that of a unit inverter (R). Annotate the gate
with its gate and diffusion capacitances. Draw the equivalent
circuits for the falling output transition and for the worst-case
rising output transition.

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A
A

B
B
C C
(i)NAND3
Schematic
A
(ii)NAND3 Schematic with
capacitances
B
C These capacitances do not
contribute to delay, hence
(iii)
ignored

Equivalent RC-Circuits for a 3-input NAND gate

output fall and rise transitions

B
C

3-input NAND equivalent

circuit
A=B=C=‘1’ Let A =1,B=1,C=0

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 10-11-2023

Transient Response ( Transient Delay)

• Every real circuit has some capacitance.
• In an integrated circuit, it typically consists of the load
capacitance (CL) along with the diffusion capacitance of the
driver’s own transistors(CFET).
• Wires that connect transistors together often contribute the
majority of the capacitance(C wire ).
• The circuit output takes time (delay) to switch because the
capacitance cannot change its voltage instantaneously
• The transistor current depends on the input (gate)
and output (source/drain) voltages.

10-11-2023 VLSI Design 1

Rise Time, Fall Time, Propagation delay

• Rise time, tr = Time for a waveform to rise from 20%

to 80% of its steady-state value

• Fall time, tf = Time for a waveform to fall from 80%

to 20% of its steady-state value

• Propagation delay time, tpd = maximum time from

the input crossing 50% to the output crossing 50%

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Elmore Delay Model

• In general, most circuits of interest can be
represented as an RC tree.
• The root of the tree is the voltage source and the leaves
are the capacitors at the ends of the branches.
• The Elmore delay model estimates the delay from a
source switching to one of the leaf nodes as the sum
over each node i, of the capacitance Ci on the node,
multiplied by the effective resistance Ris on the
shared path from the source to the node and the
leaf.

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 10-11-2023

Estimate tpdf and tpdr for the unloaded 3-input NAND gate :Use
Elmore delay model

Capacitances in a 3-input NAND

gate

Estimation of tpdf in a unloaded 3-input NAND gate

using Elmore delay model

• tpdf :Consider RC equivalent circuit of NMOS

network : worst case delay

• Node Y has capacitance 9C and resistance (R/3 +

R/3 + R/3) to ground.
• Node n2 has capacitance 3C and resistance (R/3
+ R/3) to ground.
• Node n1 has capacitance 3C and resistance of R/3
to ground.

• The Elmore delay for the falling output is the sum

of these RC products,

tpdf = [(3C)(R/3) + (3C)(R/3 + R/3) +(9C)(R/3 + R/3 + R/3)]

tpdf = 12RC.

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• tpdr : Consider PMOSFET network

Estimation of tpdr in a unloaded 3-input
NAND gate using Elmore delay model • In NAND3, in the worst case, two inputs are
1 and one input is at 0.
• Y is pulled up to VDD through a single pMOS
transistor(whose gate input is ‘0’).

• The ON NMOS transistors contribute

parasitic capacitance that slowdown the
transition.

• Node Y has capacitance 9C and resistance R

to the VDD supply.
• Node n2 has capacitance 3C. The relevant
resistance is only R [ not (R + R/3), because
the output is being charged only through
R. This is what is meant by the resistance
on the shared path from the source (VDD)
to the node (n2) and the leaf ( Y)].

• Node n1 has capacitance 3C and resistance

R.
• The Elmore delay for the rising output is, tpdr = 9RC+3 RC+3RC=15 RC.

Estimate tpdf and tpdr for the 3-input NAND gate if the output is loaded
with h identical NAND gates

Capacitances in an unloaded 3-input Capacitances in a loaded 3-input

NAND gate NAND gate

• Each NAND gate load presents 5 units of capacitance on a given input.

• Hence ‘h’ number of NAND gates together contribute 5hC capacitances.

• Total capacitance at node Y = 9C+5hC = (9+5h) C

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Estimation pdf in a 3-input NAND gate with the output loaded with h
identical NAND gates
• tpdf :Consider RC equivalent circuit of
NMOS network : worst case delay

• Node Y has capacitance (9 + 5h)C and

resistance (R/3 + R/3 + R/3) to ground.

• Node n2 has capacitance 3C and

resistance (R/3 + R/3) to ground.
• Node n1 has capacitance 3C and
resistance of R/3 to ground.

• The Elmore delay for the falling output

is the sum of these RC products,

tpdf = (3C)(R/3) + (3C)(R/3 + R/3) + ((9 + 5h)C)(R/3 + R/3 + R/3)

tpdf = (12 + 5h)RC.

Estimation of tpdr for the 3-input NAND gate with the output
loaded with h identical NAND gates
• tpdr : Consider RC equivalent circuit of PMOS
network : worst case delay

• In NAND3, in the worst case, two inputs are 1 and

one input is at 0.
• Y is pulled up to VDD through a single pMOS
transistor (whose gate input is ‘0’).

• The ON nMOS transistors contribute parasitic

capacitance that slows the transition.

• Node Y has capacitance (9 + 5h)C and resistance R

to the VDD supply.

• Node n2 has capacitance 3C. The relevant

resistance is only R [ not (R + R/3), because the
output is being charged only through R. This is
what is meant by the resistance on the shared
path from the source (VDD) to the node (n2) and
the leaf ( Y)].
• Node n1 has capacitance 3C and resistance R.
• The Elmore delay for the rising output,
tpdr = (9+5h)RC+3RC+3RC=(15 + 5h)RC

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 10-11-2023

Example:4.4: Estimate tpd for a unit inverter

driving ‘m’ identical unit inverters.

Solution: Unit inverter driving another one unit inverter

• The output node Y

sees a capacitance of 3C
from the drain diffusions of
the driving inverter.
• One load inverter presents
3C units of gate capacitance
Hence ‘m’ number of load inverters presents a total capacitive load of m*(3C)
=3mC.

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 10-11-2023

Solution (contd.): tpd for a unit inverter driving ‘m’ identical

unit inverters.

• The total capacitance

is (3 + 3m)C.

• The resistance is R

The Elmore delay,

tpd = (3 + 3m)RC.

Example 4.6: If a unit transistor has R = 10 kΩ and C = 0.1 fF in a 65 nm process, compute the delay, in
picoseconds, of the inverter with a fan-out of h = 4 (FO4). Use Elmore delay model.

• For h = 4, the delay is (3 + 3h)RC

• The RC product in the 65 nm process is
(10 k Ω)(0.1 fF) = 1 ps.
• Delay = (3+3X4)(1 ps) = 15 ps.

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 15-11-2023

Combinational Circuit Design:

Pseudo-NMOS logic, CVSL
(T1:Neil H. E. Weste and David Money Harris, “CMOS VLSI Design- A
Circuits and Systems Perspective”, 4th Edition, Pearson Education
India, 2011 : Chapter 9.2.2, 9.2.3).

15-11-2023 1

Pseudo-NMOS logic

15-11-2023 2

1
 15-11-2023

15-11-2023 3

Pseudo-NMOS Logic

Input

15-11-2023 4

2
 15-11-2023

Pseudo-NMOS logic: Ratioed Logic

Consider pseudo-NMOS inverter with Vin =VDD

15-11-2023 5

VOL in pseudo NMOS inverter

15-11-2023 6

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 15-11-2023

15-11-2023 7

• Advantages
• Small MOSFET count->small silicon area
• Simple, compact layout
• Small parasitic
• Disadvantages
• Selection of ratio of aspect ratios is critical for valid output LOW voltage level.
• DC power dissipation in the circuit when pull down network is ON.

15-11-2023 8

4
 15-11-2023

CVSL: Cascode Voltage Switch Logic

15-11-2023 9

CVSL
• CVSL uses both true and complementary input signals and computes both true and
complementary outputs using a pair of nMOS pulldown networks, as shown in Figure.

• For any given input pattern, one of the pulldown networks will be ON and the other OFF.
• The pulldown network that is ON will pull that output LOW. This low output turns ON the
pMOS transistor to pull the opposite output HIGH. When the opposite output rises, the other
pMOS transistor turns OFF so no static power dissipation occurs.

5
 15-11-2023

CVSL AND/NAND gate

6
 16-11-2023

Sequential Circuit Design: Latches and Flip-Flops

(T1:Neil H. E. Weste and David Money Harris, “CMOS VLSI Design- A Circuits and
Systems Perspective”, 4th Edition, Pearson Education India, 2011 : Chapter : 10.3.1,
10.3.2, 10.3.4 ).

Sequential Circuit Design :Introduction

• In combinational circuit, the output is a function of the current
inputs. In sequential circuits the output depends on previous as
well as current inputs, such circuits are said to have state.
• Finite State Machines (FSM) of sequential circuits. and pipelines are two
important examples

• Sequential circuits are usually designed with flip-flops or

latches, which are sometimes called memory elements

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 16-11-2023

Conventional CMOS Latches • In Figure 1., When the clock ɸ is 1,

the input transmission gate is ON,
the feedback tristate is OFF, and the
latch is transparent, Q=D.
• When the clock ɸ is 0, the input
transmission gate turns OFF.
However, the feedback tristate
inverter turns ON, holding node X at
the correct level.
• Figure 2. An inverter is used at the
input, so that input D is at MOSFET
gate (of the inverter) rather than
unbuffered diffusion of TG.
Latches with feedback

Note: latches shown are transparent while ɸ is high. They can be converted to active-low latches by
swapping ɸ and ɸ’.

Conventional CMOS Flip-flops : Positive Edge triggered F/F

The flip flop is built by

cascading active low
latch with active high
latch, with feedback.

• For ɸ =0, TG1-ON TG2-OFF

X=D’, Q=Old Q => Load Master
• For ɸ =1, TG1-OFF TG2-ON
X= recent D’, Q= D => Transfer to load

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 16-11-2023

Resettable & Settable Latches and Flip-Flops

Latches and Flip-Flops with reset input

• Most practical circuits require a reset signal to enter a

known initial state on start-up and ensure deterministic
behaviour.
• There are two types of reset: Synchronous reset and
Asynchronous reset.
• Asynchronous reset forces the output Q low immediately,
while synchronous reset waits for the clock.

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 16-11-2023

Latches and Flip-Flops with synchronous reset

In a 2-input NAND gate , if one of the input is at LOW, output is HIGH.

In a 2-input NAND gate , if one of the input is at HIGH, output is inversion of the other input(acts as an
inverter)

If reset = 1, NAND gate output =1 and hence Q = 0

Latches and Flip-Flops with Asynchronous reset

In a 2-input NAND gate , if one of the input is at LOW, output is HIGH.

In a 2-input NAND gate , if one of the input is at HIGH, output is inversion of the other input(acts as an
inverter)

• Reset = 1 => Reset’ = 0 =>Q=0

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 16-11-2023

Flip-flop with asynchronous set and reset.

Conventional Flip-flop
In a 2-input NAND gate , if one of
the input is at LOW, output is HIGH. Only one control input i.e. either set or reset is kept HIGH at a time.
In a 2-input NAND gate , if one of For reset = 1, set =0, irrespective of D-input, Q =0
the input is at HIGH, output is For reset =0, set =1, , irrespective of D-input, Q=1
inversion of the other input(acts as
an inverter)