LM358S, LM2904S

Single Supply Dual

Operational Amplifiers
Utilizing the circuit designs perfected for Quad Operational
Amplifiers, these dual operational amplifiers feature low power drain,
a common mode input voltage range extending to ground/VEE, and
single supply or split supply operation. The LM358S and LM2904S http://onsemi.com
are half of the LM324S and LM2902S, respectively.
MARKING
These amplifiers have several distinct advantages over standard
DIAGRAMS
operational amplifier types in single supply applications. The common
mode input range includes the negative supply, thereby eliminating the
necessity for external biasing components in many applications. The LM358SN
output voltage range also includes the negative power supply voltage. AWL
YYWWG
Features
• Short Circuit Protected Outputs
• True Differential Input Stage PDIP−8
N SUFFIX LM2904SN
• Single Supply Operation: 3.0 V to 32 V CASE 626 AWL
YYWWG
• Low Input Bias Currents
• Internally Compensated
• Common Mode Range Extends to Negative Supply LMxxxx = Specific Device Code
A, AL = Assembly Location
• Single and Split Supply Operation WL = Wafer Lot
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Y, YY = Year
Compliant W, WW = Work Week
G or G = Pb−Free Package

PIN CONNECTIONS

Output A 1 8 VCC
2
−
7 Output B
Inputs A +
3 6
−
+ 5 Inputs B
VEE/GND 4

(Top View)

ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

October, 2014 − Rev. 0 LM358S/D
 LM358S, LM2904S

3.0 V to VCC(max)
VCC VCC

1.5 V to VCC(max)
1 1

2 2
1.5 V to VEE(max)
VEE
VEE/GND
Single Supply Split Supplies
Figure 1.

Bias Circuitry
Common to Both
Output Amplifiers
VCC
Q15
Q16 Q14 Q22
Q13
40 k
Q19

5.0 pF Q12 Q24

25 Q23

Q18 Q20
Inputs
Q11
Q9
Q17 Q21
Q6 Q7 Q25
Q2 Q5 Q1 2.4 k
Q8 Q10
Q3 Q4 Q26
2.0 k
VEE/GND

Figure 2. Representative Schematic Diagram

(One−Half of Circuit Shown)

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 LM358S, LM2904S

MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)

Rating Symbol Value Unit
Power Supply Voltages Vdc
Single Supply VCC 32
Split Supplies VCC, VEE ±16
Input Differential Voltage Range (Note 1) VIDR ±32 Vdc
Input Common Mode Voltage Range (Note 2) VICR −0.3 to 32 Vdc
Output Short Circuit Duration tSC Continuous
Junction Temperature TJ 150 °C
Thermal Resistance, Junction−to−Air (Note 3) Case 626 RJA 161 °C/W
Storage Temperature Range Tstg −65 to +150 °C
Operating Ambient Temperature Range TA °C
LM358S 0 to +70
LM2904S −40 to +105
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Split Power Supplies.
2. For supply voltages less than 32 V the absolute maximum input voltage is equal to the supply voltage.
3. All RJA measurements made on evaluation board with 1 oz. copper traces of minimum pad size. All device outputs were active.

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 LM358S, LM2904S

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.)
LM358S

Characteristic Symbol Min Typ Max Unit

Input Offset Voltage VIO mV
VCC = 5.0 V to 30 V, VIC = 0 V to VCC −1.7 V, VO ] 1.4 V, RS = 0 
TA = 25°C − 2.0 7.0
TA = Thigh (Note 4) − − 9.0
TA = Tlow (Note 4) − − 9.0
Average Temperature Coefficient of Input Offset Voltage VIO/T − 7.0 − V/°C
TA = Thigh to Tlow (Note 4)
Input Offset Current IIO − 5.0 50 nA
TA = Thigh to Tlow (Note 4) − − 150
Input Bias Current IIB − −45 −250 nA
TA = Thigh to Tlow (Note 4) − −50 −500
Average Temperature Coefficient of Input Offset Current IIO/T − 10 − pA/°C
TA = Thigh to Tlow (Note 4)
Input Common Mode Voltage Range (Note 5), VCC = 30 V VICR 0 − 28.3 V
VCC = 30 V, TA = Thigh to Tlow 0 − 28
Differential Input Voltage Range VIDR − − VCC V
Large Signal Open Loop Voltage Gain AVOL V/mV
RL = 2.0 k, VCC = 15 V, For Large VO Swing, 25 100 −
TA = Thigh to Tlow (Note 4) 15 − −
Channel Separation CS − −120 − dB
1.0 kHz ≤ f ≤ 20 kHz, Input Referenced
Common Mode Rejection CMR 65 70 − dB
RS ≤ 10 k
Power Supply Rejection PSR 65 100 − dB
Output Voltage−High Limit VOH V
VCC = 5.0 V, RL = 2.0 k, TA = 25°C 3.3 3.5 −
VCC = 30 V, RL = 2.0 k, TA = Thigh to Tlow (Note 4) 26 − −
VCC = 30 V, RL = 10 k, TA = Thigh to Tlow (Note 4) 27 28 −
Output Voltage−Low Limit VOL − 5.0 20 mV
VCC = 5.0 V, RL = 10 k, TA = Thigh to Tlow (Note 4)
Output Source Current IO + mA
VID = +1.0 V, VCC = 15 V 20 45 −
Output Sink Current IO −
VID = −1.0 V, VCC = 15 V 10 30 − mA
VID = −1.0 V, VO = 200 mV 12 40 − A
Output Short Circuit to Ground (Note 6) ISC − 45 60 mA
Power Supply Current (Total Device) ICC mA
TA = Thigh to Tlow (Note 4)
VCC = 30 V, VO = 0 V, RL = ∞ − 0.5 3.0
VCC = 5 V, VO = 0 V, RL = ∞ − 0.3 1.2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. LM358S: Tlow = 0°C, Thigh = +70°C
LM2904S: Tlow = −40°C, Thigh = +105°C
5. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of
the common mode voltage range is VCC − 1.7 V.
6. Short circuits from the output to VCC can cause excessive heating and eventual destruction. Destructive dissipation can result from
simultaneous shorts on all amplifiers.

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 LM358S, LM2904S

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.)
LM2904S

Characteristic Symbol Min Typ Max Unit

Input Offset Voltage VIO mV
VCC = 5.0 V to 30 V, VIC = 0 V to VCC −1.7 V, VO ] 1.4 V, RS = 0 
TA = 25°C − 2.0 7.0
TA = Thigh (Note 7) − − 10
TA = Tlow (Note 7) − − 10
Average Temperature Coefficient of Input Offset Voltage VIO/T − 7.0 − V/°C
TA = Thigh to Tlow (Note 7)
Input Offset Current IIO − 5.0 50 nA
TA = Thigh to Tlow (Note 7) − 45 200
Input Bias Current IIB − −45 −250 nA
TA = Thigh to Tlow (Note 7) − −50 −500
Average Temperature Coefficient of Input Offset Current IIO/T − 10 − pA/°C
TA = Thigh to Tlow (Note 7)
Input Common Mode Voltage Range (Note 8), VICR V
VCC = 30 V 0 − 28.3

VCC = 30 V, TA = Thigh to Tlow 0 − 28

Differential Input Voltage Range VIDR − − VCC V
Large Signal Open Loop Voltage Gain AVOL V/mV
RL = 2.0 k, VCC = 15 V, For Large VO Swing, 25 100 −
TA = Thigh to Tlow (Note 7) 15 − −
Channel Separation CS − −120 − dB
1.0 kHz ≤ f ≤ 20 kHz, Input Referenced
Common Mode Rejection CMR 50 70 − dB
RS ≤ 10 k
Power Supply Rejection PSR 50 100 − dB
Output Voltage−High Limit VOH V
VCC = 5.0 V, RL = 2.0 k, TA = 25°C 3.3 3.5 −
VCC = 30 V, RL = 2.0 k, TA = Thigh to Tlow (Note 7) 26 − −
VCC = 30 V, RL = 10 k, TA = Thigh to Tlow (Note 7) 27 28 −
Output Voltage−Low Limit VOL − 5.0 20 mV
VCC = 5.0 V, RL = 10 k, TA = Thigh to Tlow (Note 7)
Output Source Current IO+ 20 45 − mA
VID = +1.0 V, VCC = 15 V
Output Sink Current IO−
VID = −1.0 V, VCC = 15 V 10 30 − mA
VID = −1.0 V, VO = 200 mV − − − A
Output Short Circuit to Ground (Note 9) ISC − 45 60 mA
Power Supply Current (Total Device) ICC mA
TA = Thigh to Tlow (Note 7)
VCC = 30 V, VO = 0 V, RL = ∞ − 0.5 3.0
VCC = 5 V, VO = 0 V, RL = ∞ − 0.3 1.2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. LM358S: Tlow = 0°C, Thigh = +70°C
LM2904S: Tlow = −40°C, Thigh = +105°C
8. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of
the common mode voltage range is VCC − 1.7 V.
9. Short circuits from the output to VCC can cause excessive heating and eventual destruction. Destructive dissipation can result from
simultaneous shorts on all amplifiers.

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 LM358S, LM2904S

CIRCUIT DESCRIPTION

The LM358S and LM2904S are made using two and Q18. Another feature of this input stage is that the input
internally compensated, two−stage operational amplifiers. common mode range can include the negative supply or
The first stage of each consists of differential input devices ground, in single supply operation, without saturating either
Q20 and Q18 with input buffer transistors Q21 and Q17 and the input devices or the differential to single−ended
the differential to single ended converter Q3 and Q4. The converter. The second stage consists of a standard current
first stage performs not only the first stage gain function but source load amplifier stage.
also performs the level shifting and transconductance Each amplifier is biased from an internal−voltage
reduction functions. By reducing the transconductance, a regulator which has a low temperature coefficient thus
smaller compensation capacitor (only 5.0 pF) can be giving each amplifier good temperature characteristics as
employed, thus saving chip area. The transconductance well as excellent power supply rejection.
reduction is accomplished by splitting the collectors of Q20

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 LM358S, LM2904S

50 k
R1

VCC
VCC 5.0 k
R2 -
10 k VCC
1/2 -
VO Vref 1/2
LM358S
LM358S VO
MC1403 +
2.5 V + 1
fo =
1 2  RC
Vref = V
2 CC
For: fo = 1.0 kHz
R1 R = 16 k
VO = 2.5 V (1 + ) R C
R2 R C = 0.01 F
C

Figure 3. Voltage Reference Figure 4. Wien Bridge Oscillator

+ 1
e1
1/2 CR R
LM358S R2 Hysteresis
- VOH

R1 VO
- Vref +
a R1 1/2 1/2
R1 eo
LM358S LM358S
+ Vin - VO
b R1 VOL
1 VinL VinH
- CR R1
1/2 Vref
VinL = (V - V )+ Vref
LM358S R1 + R2 OL ref
e2 + R R1
VinH = (V - V ) + Vref
R1 + R2 OH ref
eo = C (1 + a + b) (e2 - e1) R1
H= (VOH - VOL)
R1 + R2

Figure 5. High Impedance Differential Amplifier Figure 6. Comparator with Hysteresis

1
fo = 2 
R RC
R 100 k
R1 = QR
1
Vin C1 R2 Vref = V
-
C C R2 = R1 2 CC
1/2 R TBP
LM358S - 100 k
1/2 - R3 = TN R2
+ LM358S 1/2 C1 = 10 C
+ LM358S
Vref + For: fo = 1.0 kHz
Bandpass Vref Q = 10
Vref R3 TBP =1
Output
R1 TN =1
R2 - C1
1/2
LM358S
Notch Output R = 160 k
+ C = 0.001 F
R1 = 1.6 M
Vref Where: TBP = Center Frequency Gain R2 = 1.6 M
TN = Passband Notch Gain R3 = 1.6 M

Figure 7. Bi−Quad Filter

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 LM358S, LM2904S

VCC
C R3
R1 C
Vin -
1/2
LM358S
VO
+ CO
R2
CO = 10 C
Vref 1
Vref = 2 VCC

Given: fo = center frequency

A(fo) = gain at center frequency

Choose value fo, C

Q
1 Then: R3 =
Vref = V Triangle Wave R2  fo C
2 CC Output
300 k R3
Vref + R1 =
2 A(fo)
1/2 R3
+
LM358S 1/2 R1 R3
- 75 k R2 =
R1 100 k LM358S 4Q2 R1 -R3
Square
- Qo fo
Wave
Vref For less than 10% error from operational amplifier. < 0.1
Output BW
C
Where fo and BW are expressed in Hz.
Rf
R1 + RC R2 R1 If source impedance varies, filter may be preceded with voltage
f = if, R3 =
4 CRf R1 R2 + R1 follower buffer to stabilize filter parameters.

Figure 8. Function Generator Figure 9. Multiple Feedback Bandpass Filter

ORDERING INFORMATION

Device Operating Temperature Range Package Shipping†

LM358SNG 0°C to +70°C PDIP−8 50 Units / Rail
(Pb−Free)

LM2904SNG −40°C to +105°C PDIP−8 50 Units / Rail

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
E1 NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
1 4
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN XXXXXXXXX
3. DC − IN AWL
4. AC IN
5. GROUND YYWWG
6. OUTPUT
7. AUXILIARY
8. VCC
XXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42420B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: PDIP−8 PAGE 1 OF 1

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