Chapter 1 - Logic Components Experiment 1.1 - Logic Gates Objectives: After completing this experiment explain = Thetruth table ofthe gates AND, OR, NOT, NAND, NOR and XOR, = The behavior of expanded gates. © How to use gates as blocking gates. Equipment required: Digital trainer Power supply Jumper wires 7400, 7402, 7404, 7408, 7432, 7486 Discussion: In this experiment we will use with the common gates AND, OR, NOT, NAND, NOR and XOR. TThe deseription of each component 1s given on the last pages of this book. We will identify the truth table of each gate. We will use two gates with two inputs to create on gate with three inputs. We will also examine how to block digital signals with gates. 1.1.1 Logic components “The logic components are the building blocks of the digital system and constitute their bass. Dist systems are systems required to perform an operation or sequence of operations according to sigma delivered at their inputs. A nearly unlimited number of digital systems are in existence, starting wit) switch lighting @ light up to a sophisticated computer executing an infinite number of operations. ‘These components are called logic components because their operations resemble a kind of think" and decision making. The logic component is looked " i is looked upon as a "BI having a number inputs (one, two, or more) and a single output. lack Box” having @ 1D, NOR andi, nputs to ra Figure 1-1 Logic Component Representation Iso found, but they may be as 7: Soe oe a— p—} Lx c— a— ay fy oc at aa) |e 2 ct ‘igure 1-2 3-Outputs Component Ih every logic component, the signal atthe output is a function of the signals atthe inputs, We ae Bee git topic systems; hence, the inputs and ihe oni ean airs ois Of He ulus (08 Ii}, A digital system is not necessarily only a computer system where tne e's ePrcscat different voltage levels. The digital system may be a mechanical systeth 2 clectro-mechanical system, or an electrical one. If the inputs are switches, then @ ‘closed switch may be defined as logic ‘1’, and an ‘open switch may be defined as logic 0" which we deal, logic I” state shall be defined as one voltage level tate may be defined as another voltage level (usually OV). There device “electronically”. We shall not dwelt.on In the realm of systems in (usually +5V), and the logic are several possibilities of implementing this tyPe ©! the internal (circuit wise) structure of these systems. A computer ade of thousands of logic devices, Tere ate scores of different types of Ree Sethe esi oat of them isa smal group offevies Ynown 8 i: a : ‘ch all other logic components are 4 asic logic component from whiel meanbied. They ee i the digital systems. assembled. They are the building blocks of a B . ..imple electric cir it is customary to introduce simp a hich by themselves form a kind of a similar gute, In Ibs, For the latter, the logic"! state hed light When explaining the diverse logic gates, demonstrating the operation of a logic gate, wi these circuits, the inputs are switches and the outputs are light Be is defined by a tumed on light and the logic ‘is defined by an extingus In the following presentation in this chapter, we shall discuss two-input gates, though, as stateg cearlier, various multi-inputs gates are also in use 1.1.2 "AND" gate Figure 1-4 and its operation can be understood from the (ie., will be in the logic ‘1’ state) when both state). A similar situation holds for the gate in The gate is presented by the symbol in figure 1+ circuit in figure 1-4. The light shall be tured O switches A "AND" B are closed (be in the logic figure 1-3. ¥ willbe at “45V if +5V occurs at both A "AND" B ise ‘These switches are als regular (normal) condition. Upon activation, they close and cons .o referred to as N.O. (Normally Open) switches. They are OPEN under ther tute a short circuit, er to describe the relation between Y and the A and B inputs, a "truth table” depi states is used. A truth table shows the value at the output for every possible combination of ‘open open closed closed open closed closed not alight not alight not alight alight possible states are: 232 aiee AND gate can be describe The AND gate can be described by the equation y=A AND B Ihas been already mentioned th: med that the a 4-inputs AND gate shall be logic I" Bales can posses a number of inputs larger than 2. ‘Thus, Y of numberof inputs only if al D pel sate four inputs shall be at logic state, 1.1.3 "OR" gate : c be b> | : Figure 1S Figure 6 an be 3 Toe et Figure 15 presents the symbol of the gate and figure 1-6 demonstrates its operation, Th amp is Jeg sy Fiery ON ight) when switch A "OR" switch Bs closed. It wil also be turned ON when both ion holds fori sarees are closed. Hence logic I state shal be constructed at Y when A *OR” B isinthe lope state. They are OPEN wie In conclusion, the truth table of an "OR" gates as shown: short circuit truth table” dice? sry possible comtis ssible vals ‘The OR gate can be described by the equation Y=A ORB z 1.1.4 "NOT" gate— Inverting gate Figure 1-8 Figure 1-7 pot ofthe gate and FEM 1-8 demonstrates its operation. mbol of the & Sm, Figure 1-7 presents the 89” ee we SrcAnother type of switch encountered is the N.C. (Normally closed) switch. Its regular (normal) state isthe CLOSED state. Upon activation, it opens and constitutes an open circuit. ‘Switch A is an N.C. switch. When it is not activated (it constitutes a short circuit), that is, the lamp is lit (umed ON) but when A is activated (it is an open circuit) the light is extinguished. The logic state of Y is always the reverse of the logic state of A. Note that a small circle appended to the output of the gate symbolizes an inverting gate. ‘The truth table of the "NOT" gate has two states: Aly oft 1fo ‘This situation can be described by the equation: Y=NOTA The above three gates are basic gates. We will describe three additional gates, which are used a lot Although these additional gates can be built based on the first three gates, they are also considered basic gates. 115 "“NAND" gate This gate can be constructed as an AND gate with an appended inverter at its output. ae’ Figure 1-9 A NAND gateFigure 110 ‘The truth table of the "NAND" gate is as fol Its equation is: Which ae ise Yy=NOT(A AND B) 1.1.6 "NOR" gate ‘This gate, too, can be consrcted by two gules —an “OR” ge and an appended invest at its output tput. Figure 11 ‘The truth table of this systems c=A ORB y=nor © lows: ois asf0 ‘The symbol of the “NOR” #8 |Its truth table is as presented below: divi Its equations is: y=NOT (A OR B) 11.7 "XOR" (eXclusive OR) gate This gate is symbolized as follows: =D Figure 1-13 inderstand its operation by studying its truth table, which is: when A "OR" B equals "t', but not when they are both equal '' (asin the on for its name, the "eXclusive OR". rents are the electron" is and are IC's (inte to use and the most convenient logic compons in a plastic package with two lines of pin also known by their other popular name -Bp sities Figure 1-14 A Device in a Dual In Line Packay in Line Package sere are ther types of packaging belon ging to the Sur in Te est be soldered on the Print Cet Bod EE See er components: re ais oul contin several lie devi or amply la eis, 1 ages Tesird with varying numbers of pins, There are un , ee ere are units with 8,14 16, 18, 20, 24,40, _ The manufacturing technol of these devices is complex. Each such unit ioe of bude of Theme devices’, Some units constitute a complete cigital sytem and cven # On deermrpcessor in which a few hundred thousand elestronie devices ae integrated single package. Asa result of their mass production in very large Tots, the cletronic logic componeths Ay very Grempensive. Later in the: Book, we shall lear how to read and understand the component data Sheets. At present, we will comment on two points ach electronic logic component has two pint for i's power supply. The positive terminal of the Waazee called Noo, is connected to One Fro (osualy itis a +5V voltage); and the negative omrnal of the power source, called GND. {GrouND). is connected tote oer, These lines are at tach of the components located in the pack#8e sponents located in 2 g1¥eR package, a characteristic number 18 re family" ofthis components Ihe ‘echnology by which it was idden in this number. We shall iis made of are hi veara sheets contain a aeserption of Ihe package In order to designate the logic co assigned to every package. Data on ‘manufactured, and the type of !o8ic ‘components it Beer on this subject later on. (SPeif> package _and a functional assignment of its pins.) ‘Consider 7400 is packed in @ ual in line package that includes + te tog rage pees teFigure 1-15 Description of the 7400 component igure 1- e very pin of this packay s ssigned function of each and every pin of this package th sae ee ah emcee as the "No, 1". Usually litle black dots marca Rpt the number 1 pin, Looking at a device from its upper side, the pin nue leg of the nu in ockwise from the No. I pin. Sometimes the dot is not seen, or Was not marked counterclockwise : In this case, thee i a depression on one of the lateral edges of the component Pin No, isa to the left of this depression oath ll lll Figure 1-16 Identifying leg 1 Questions and exercises: 1) How would a 2-inputs NAND gate behave when its two inputs are short circuited (0% Sp, another)? How would 2-inputs NOR gate behave when its two inputs are short circuited ® another)? How would C m @Dinput XOR gate behave when its two inputs are short circuit another)? Pt think ir ttl E fe Di tvink the following gates (a, b, and c) would behave? Write downcedure: esi tales ofthe sates of sf s} | Connect the TPS-3351 to the po ‘power supply and com ect the power supply to the Mains. Jum ON the TPS-3351 ~ oa? Connect both inputs of the AND gat see EE ‘yps-3351, and ponent in ep Wet he th be forte atin Jour notebook, = sseps: Change the state of the switehes according to the wh able and record the TEsHl of state in the table. arth table that you have obisined conform to the ixground material? mnclusion. Does the sepés Record you a -d in the theoretical theory presente ble for each gate for the following gues an complete the truth AND siep7: Repeat steps 3106 oR eS =D- as" ALY A_B ¥ 0 o 0 ; oe s m0 Be = 239 She anierreop hmExpansion of gates: Step 8: Connect inputs A, B, and C of the following circuit to three switches on TPs.q ‘rainer. A Bel AlY 0 1 ; Change th Step 9: Connect the LO LED to the output ofthe circuit (¥), a Step 10: Complete the truth table for the circuit in your notebook ‘Write you Step 11: Change the state of the switches according to the truth table. Record the result for. coe state in the table. Step 12: As a conclusion, write down whether the truth table that you have obtained conf Ropat st with the theory presented in the theoretical background material a Step 13: Repeat steps 8 to 12 for the following gate combinations and complete their truth t Bay ‘ : ee ‘ aanble. Record the resi it Step 14 Step 15: Step 16: Swp 17: Step 18: Step 19: Experiment rene and table results, Write in the table above each experiment leet all your ex! wing. rate expres ass 2) Compare the experiment loo ee 100 an 1o4 ose ta) fa Blocking gates: Connect the A and B inputs ‘fan AND gate to two switches on the TPS-3351. = a ‘Connect the output ofthe gate to the LED input. ‘Assume that the B input serves as a cont input serves as a control input. Write two truth tables in your ‘notebook ~ one for B=0 and one for B=1 ao Bei =0, Aly y 0 0 1 1 Change the state of the switches according to the truth tables: and record the results in the tables. Write your conclusions regarding the function of the gate in each of the states under the control input conditions. eps 14 to 18 forthe following gates and complete their truth tables, Repeats NAND NOR xe oe Bel Bel re Aly ALY aly ae Teo 1 1 } ‘i ’ BO 0 B=0 Eo aie Aly Aly eae . 0 a ae ‘gate inthis case. Note the special behavior ofthe XOR results withthe theory a =. .