NFC IET

Department of Computer Science

Digital Logic Design
Lab Manual

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 Contents
Lab 01......................................................................................................................................................3
Implementing Logic Gates......................................................................................................................3
Lab 02....................................................................................................................................................12
Implement Boolean expression using logic gates................................................................................12
The DE Morgan’s law............................................................................................................................13
Lab 03....................................................................................................................................................19
Implement NAND Gate as a universal gate..........................................................................................19
Lab 04....................................................................................................................................................25
Implementing Karnaugh-maps.............................................................................................................25
Lab 05....................................................................................................................................................33
Implement Binary to Gray code conversion.........................................................................................33
Implementation of Binary to Binary Coded Decimal (BCD) Conversion..............................................40
Lab 06....................................................................................................................................................43
Implement Half Adder..........................................................................................................................43
Implementing 7 – segment...................................................................................................................45
LAB 07...................................................................................................................................................49
Implementing Full Adder......................................................................................................................49
Implementing HALF SUBTRACTOR........................................................................................................51
Implementing Full Subtractor...............................................................................................................53
Lab 08....................................................................................................................................................55
Implementing N – Bit Full Adder.....................................................................................................55
Implementing BCD to Excess 3 Conversion..........................................................................................57
Lab 09....................................................................................................................................................60
Implementing Decoder.........................................................................................................................60

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Lab 10....................................................................................................................................................63
Implementing Decoder...................................................................................................................63
Implementing Multiplexer..............................................................................................................64
Lab 11....................................................................................................................................................69
Implementing Sequential Circuit..........................................................................................................69
LAB 12...................................................................................................................................................72
Implementing SR Flip Flop....................................................................................................................72
Lab 13....................................................................................................................................................74
Implementing J-K Flip Flop....................................................................................................................74
Implementation of D Flip-flop..............................................................................................................77
Lab 14....................................................................................................................................................80
Implementation of T Flip Flop..............................................................................................................80
Implementing Master-Slave JK Flip Flop..............................................................................................82
Lab 15....................................................................................................................................................83
Implementation of Registers................................................................................................................83

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 Lab 01
Implementing Logic Gates

Digital logic design

Digital logic design is a system in electrical and computer engineering that uses simple
number values to produce input and output operations. As a digital design engineer, you may
assist in developing cell phones, computers, and related personal electronic devices.

Logic gates
A logic gate is a device that acts as a building block for digital circuits. They perform
basic logical functions that are fundamental to digital circuits. Most electronic devices we use
today will have some form of logic gates in them. For example, logic gates can be used in
technologies such as smartphones, tablets or within memory devices.

1. AND Gate
The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate
acts in the same way as the logical "and" operator. The following illustration and table show the
circuit symbol and logic combinations for an AND gate. (In the symbol, the input terminals are
at left and the output terminal is at right.) The output is "true" when both inputs are "true."
Otherwise, the output is "false." In other words, the output is 1 only when both inputs one AND
two are 1.

 2 inputs
Truth Table X Y Output
0 0 0
0 1 0
X 1 0 0
1 1 1

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 3 inputs Truth Table

X Y Z Output
0 0 0 0
0 0 1 0
0 1 0 0
X 0 1 1 0
1 0 0 0
Y 1 0 1 0
Z 1 1 0 0
1 1 1 1

2. OR Gate
The OR gate gets its name from the fact that it behaves after the fashion of the logical
inclusive "or." The output is "true" if either or both of the inputs are "true." If both inputs are
"false," then the output is "false." In other words, for
the output to be 1, at least input one OR two must be X Y Output
1.
0 0 0
0 1 1
 2 inputs 1 0 1
1 1 1
Truth Table

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 3 inputs Truth Table

X Y Z Output
0 0 0 0
0 0 1 1
X 0 1 0 1
Y 0 1 1 1
1 0 0 1
Z
1 0 1 1
1 1 0 1
1 1 1 1

3. XOR Gate
The XOR ( exclusive-OR ) gate acts in the same way as the logical "either/or." The output
is "true" if either, but not both, of the inputs are "true." The output is "false" if both inputs are
"false" or if both inputs are "true." Another way of looking at this circuit is to observe that the
output is 1 if the inputs are different, but 0 if the inputs are the same.

 2 inputs

Truth Table

X Y Output
0 0 0
X
0 1 1
Y
1 0 1
1 1 0

X Y Z Output
0 0 0 0
 3 inputs 0 0 1 1
Truth Table 0 1 0 1
0 1 1 0
1 0 0 6|Page
1
1 0 1 0
1 1 0 0
1 1 1 1
 X

4. NOT Gate
A logical inverter, sometimes called a NOT gate to differentiate it from other types of
electronic inverter devices, has only one input. It reverses the logic state. If the input is 1, then
the output is 0. If the input is 0, then the output is 1.

 Single input

Truth Table

X Output
0 1
1 0

5. NAND Gate

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 The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner
of the logical operation "and" followed by negation. The output is "false" if both inputs are
"true." Otherwise, the output is "true."

 2 inputs Truth
X Y Output
0 0 1
0 1 1
1 0 1
1 1 0
Table

X Y Z Output
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
 3 inputs 1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

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6. NOR Gate
The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both
inputs are "false." Otherwise, the output is "false."

 2 inputs

Truth Table

X Y Output

X
0 0 1
0 1 0
Y
1 0 0
1 1 0

 3 inputs

X Y Z Output
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

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7. XNOR Gate
The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. Its output is
"true" if the inputs are the same, and "false" if the inputs are different.

 2 inputs

Truth Table

X Y Output
0 0 1
X
0 1 0
Y
1 0 0
1 1 0

 3 inputs

X Y Z Output
0 0 0 1
0 0 1 0
X
0 1 0 0
Y 0 1 1 0
1 0 0 0
Z
1 0 1 0
1 1 0 0
1 1 1 0

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 All Gates combined to have same inputs
 2 inputs

 3 inputs

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 Lab 02
Implement Boolean expression using logic gates

Boolean Algebra

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 The Algebra which implements Boolean expressions with logic gates. Boolean algebra is
the branch of algebra in which the values of the variables are the truth values true and false,
usually denoted 1 and 0, respectively.
In these circuits, we use a 4-bit LED Display as output which has four pins.

 F = x + y ’z
Truth Table

X Y Z Y’ Y’Z X+Y’Z
0 0 0 1 0 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 1 0 1
1 0 1 1 1 1
1 1 0 0 0 1
1 1 1 0 0 1

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 ImplementingThe DE Morgan’s law
(2 Inputs)
DE Morgan’s Law:
The DE Morgan’s theorem defines the uniformity between the gate with the same
inverted input and output. It is used for implementing the basic gate operation likes
NAND gate and NOR gate. The DE Morgan’s theorem mostly used in digital
programming and for making digital circuit diagrams. The two laws are:

1. (X+Y)’ = X’Y’
2. (XY)’ = X’+Y’

 (X+Y)’ = X’Y’
Truth Table

X Y X’ Y’ X+Y (X+Y)’ X’Y’

0 0 1 1 0 1 1
0 1 1 0 1 0 0
1 0 0 1 1 0 0
1 1 0 0 1 0 0

Circuit Diagram

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 (XY)’ = X’+Y’

Truth Table

X Y X’ Y’ XY (XY)’ X’+Y’
0 0 1 1 0 1 1
0 1 1 0 0 1 1
1 0 0 1 0 1 1
1 1 0 0 1 0 0

Combined DE Morgan’s Laws

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 y

DE Morgan’s Laws
3 inputs

1. (X+Y+Z)’ = X’Y’Z’
2. (XYZ)’ = X’+Y’+Z’

 (X+Y+Z)’ = X’Y’Z’
 Truth Table
X Y Z X’ Y’ Z’ X+Y+Z (X+Y+Z)’ X’Y’ X’Y’Z’

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 0 0 0 1 1 1 0 1 1 1
0 0 1 1 1 0 1 0 1 0
0 1 0 1 0 1 1 0 0 0
0 1 1 1 0 0 1 0 0 0
1 0 0 0 1 1 1 0 0 0
1 0 1 0 1 0 1 0 0 0
1 1 0 0 0 1 1 0 0 0
1 1 1 0 0 0 1 0 0 0

 (XYZ)’ = X’+Y’+Z’

 Truth Table

X Y Z X’ Y’ Z’ X’+Y’ X’+Y’+Z’ XYZ (XYZ)’

0 0 0 1 1 1 1 1 0 1
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0 0 1 1 1 0 1 1 0 1
0 1 0 1 0 1 1 1 0 1
0 1 1 1 0 0 1 1 0 1
1 0 0 0 1 1 1 1 0 1
1 0 1 0 1 0 1 1 0 1
1 1 0 0 0 1 0 1 0 1
1 1 1 0 0 0 0 0 1 0

Combined 3 inputs De Morgan’s Law

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 Lab 03
Implement NAND Gate as a universal gate.

NAND and NOR gates possess a special property: they are universal. That is, given enough
gates, either type of gate is able to mimic the operation of any other gate type.
For example, it is possible to build a circuit exhibiting the OR function using three
interconnected NAND gates. The ability for a single gate type to be able to mimic any other gate
type is one enjoyed only by the NAND and the NOR. In fact, digital control systems have been
designed around nothing but either NAND or NOR gates, all the necessary logic functions being
derived from collections of interconnected NANDs or NORs.

 NOT
Truth Table
X Output
0 1
1 0

 Equivalent circuit using NAND Gate

Truth Table

A A.A (A.A)’
0 1 1
1 0 0

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 AND Truth Table

X Y Output
0 0 0
X
0 1 0
1 0 0
Y 1 1 1

 Equivalent circuit using NAND Gate

Truth Table
A B A.B (A.B)’ (A.B)’’
0 0 0 1 0
0 1 0 1 0
1 0 0 1 0
1 1 1 0 1

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 OR Truth Table

X Y Output
0 0 0
X 0 1 1
Y 1 0 1
1 1 1

 Equivalent circuit using NAND Gate

Truth Table

A B A’ B’ A’.B’ (A’.B’)’ A+B

0 0 1 1 1 0 0
0 1 1 0 0 1 1
 NOR1 0 0 1 Truth
0 Table 1 1
1 1 0 0 0 1 1
X Y Output
0 0 1
X 0 1 0
Y 1 0 0 22 | P a g e

1 1 0
 Equivalent circuit using NAND Gate

Truth Table
A B A’ B’ (A+B)’ A’.B’ A+B
0 0 1 1 1 1 0
0 1 1 0 0 0 1
1 0 0 1 0 0 1
1 1 0 0 0 0 1

 XOR Truth Table

X Y Output
0 0 0
X
0 1 1
Y
1 0 1
1 1 0 23 | P a g e
 Equivalent circuit using NAND Gate
F = AB’+A’B

Truth Table
A B A’ B’ AB’ A’B AB’+A’B
0 0 1 1 0 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 1
1 1 0 0 0 0 0

 XNOR Truth Table

X Y Output
0 0 0
X 0 1 1
1 0 1
Y
1 1 0
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 Equivalent circuit using NAND Gate
F = (A’+B).(A+B’)

Truth Table
A B A’ B’ A’+B A+B’ (A’+B)(A+B’)
0 0 1 1 1 1 1
0 1 1 0 1 0 0
1 0 0 1 0 1 0
1 1 0 0 1 1 1

Lab 04
Implementing Karnaugh-maps.

Introduction of K-Map (Karnaugh Map)

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 In many digital circuits and practical problems we need to find expression with minimum
variables. We can minimize Boolean expressions of 3, 4 variables very easily using K-map
without using any Boolean algebra theorems. K-map can take two forms Sum of Product (SOP)
and Product of Sum (POS) according to the need of problem. K-map is table like representation
but it gives more information than TRUTH TABLE. We fill grid of K-map with 0’s and 1’s then
solve it by making groups.

Steps to solve expression using K-map:

1. Select K-map according to the number of variables.
2. Identify minterms or maxterms as given in problem.
3. For SOP put 1’s in blocks of K-map respective to the minterms (0’s elsewhere).
4. For POS put 0’s in blocks of K-map respective to the maxterms (1’s elsewhere).
5. Make rectangular groups containing total terms in power of two like 2, 4, 8.. (Except 1)
and try to cover as many elements as you can in one group.
6. From the groups made in step 5 find the product terms and sum them up for SOP form.

2 variables
 F= A’B+AB’+AB

K-map (2-variables):

A/B 0 1
0 1
1 1 1

 From K-map :

A’B+AB’+AB = A+B
Truth Table

A B A’ B’ A’B AB’ A+B A’B+AB’

0 0 1 1 0 0 0 0
0 1 1 0 1 0 1 1 26 | P a g e
1 0 0 1 1 1 1 1
1 1 0 0 1 0 1 1
Circuit Diagram:

3- Variables of K-map:

 F= A’B’C+A’BC’+ABC’+ABC

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 K-map:
A/BC 00 01 11 10
0 1 1
1 1 1

 From K-map :
A’B’C+A’BC’+ABC’+ABC = A’B’C+AB+BC’
Truth Table
A B C A’ B’ C’ A’B’C+A’BC’+ABC’+ABC A’B’C+AB+BC’
0 0 0 1 1 1 0 0
0 0 1 1 1 0 1 1
0 1 0 1 0 1 1 1
0 1 1 1 0 0 0 0
1 0 0 0 1 1 0 0
1 0 1 0 1 0 0 0
1 1 0 0 0 1 1 1
1 1 1 0 0 0 1 1

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Circuit Diagram:

3- Variables Of K-map:
 F= A’C+A’B+AB’C+BC
-Missing variables in terms
K - map :

A/BC 00 01 11 10

0 0 1 1 1

1 0 1 1 0

 From K-map :
A’C+A’B+AB’C+BC = C+A’B
Truth Table

A B C A’ B’ C’ A’C+A’B+AB’C+BC C+A’B
0 0 0 1 1 1 0 0

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 0 0 1 1 1 0 1 1
0 1 0 1 0 1 1 1
0 1 1 1 0 0 1 1
1 0 0 0 1 1 0 0
1 0 1 0 1 0 1 1
1 1 0 0 0 1 0 0
1 1 1 0 0 0 1 1

Circuit Diagram:

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 3- Variables Of K-map:
 F=A’B’+A’C+BC’+A’B’C
-Missing variables in terms
-Simplify using k-map
K - map :

A/BC 00 01 11 10

0 1 1 1 1

1 0 0 0 1

 From K-map :
A’B’+A’C+BC’+A’B’C = A’ + BC’

B A’B’+A’
A B C A’ C’ A’B’ A’C BC’ A’B’C BC’+A’B’C A’B’+A’C+BC’+A’B’C A’ + BC’
’ C
0 0 0 1 1 1 1 0 0 0 1 0 1 1
0 0 1 1 1 0 1 1 0 1 1 1 1 1
0 1 0 1 0 1 0 0 1 0 0 1 1 1
0 1 1 1 0 0 0 1 0 0 1 0 1 1
1 0 0 0 1 1 0 0 0 0 0 0 0 0
1 0 1 0 1 0 0 0 0 0 0 0 0 0
1 1 0 0 0 1 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0
Truth Table:

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Circuit Diagram:

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 Lab 05
Implement Binary to Gray code conversion

Binary Code
A binary code represents text, computer processor instructions, or any other data using a two-
symbol system. The two-symbol system used is often "0" and "1" from the binary number
system. The binary code assigns a pattern of binary digits, also known as bits, to each character,
instruction, etc.

Grey Code
The reflected binary code, also known just as reflected binary or Gray code after Frank Gray, is
an ordering of the binary numeral system such that two successive values differ in only one bit.
For example, the representation of the decimal value "1" in binary would normally be "001"
and "2" would be "010".

Binary to Gray Code Converter

The logical circuit which converts the binary code to equivalent gray code is known as binary to
gray code converter. An n-bit gray code can be obtained by reflecting an n-1 bit code about an
axis after 2n-1 rows and putting the MSB (Most Significant Bit) of 0 above the axis and the MSB
of 1 below the axis.

A E
B F
Binary to Gray
G
C Code Convertor

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 3 – bit
Truth Table

A B C E F G
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

K-map
A\BC 00 01 11 10

0 0 0 0 0

1 1 1 1 1

E=A

A\BC 00 01 11 10
0 0 0 1 1
1 1 1 0 0
F = A’B + AB’

A\BC 00 01 11 10

0 0 1 0 1

1 0 1 0 1

G = B’C + BC’

= B XOR C

Circuit Diagram

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 4 – bit
Truth Table
A B C D E F G H
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 1 1 1 0
0 1 0 1 1 1 1 1
0 1 1 0 1 1 0 1
0 1 1 1 1 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
2k19bscs-116
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

AB\
00 01 11 10
CD
00 0 0 0 0

01 0 0 0 0

11 1 1 1 1

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 10 1 1 1 1
E=A

AB\
00 01 11 10
CD
00 0 0 0 0

01 1 1 1 1

11 0 0 0 0

10 1 1 1 1
F = A’B + AB’ = A XOR B

AB\
00 01 11 10
CD
00 0 0 1 1

01 1 1 0 0

11 1 1 0 0

10 0 0 1 1
G = B’C + BC’ = B XOR C

AB\
00 01 11 10
CD
00 0 0 0 0

01 0 0 0 0

11 1 1 1 1

10 1 1 1 1
G = C’D + CD’ = C XOR D

Circuit diagram

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Equivalent Logic Diagram:

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 Implementation of Binary to Binary Coded Decimal (BCD)
Conversion

Binary Coded Decimal (BCD)

Binary coded decimal (BCD) is a system of writing numerals that assigns a four-digit binary
code to each digit 0 through 9 in a decimal (base-10) numeral. The four-bit BCD code for any
particular single base-10 digit is its representation in binary notation, as follows: 0 = 0000. 1 =
0001, 2 = 0010.

Truth Table
A B C D E F G H I
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1 0
0 0 1 1 0 0 0 1 1
0 1 0 0 0 0 1 0 0
0 1 0 1 0 1 1 1 1
0 1 1 0 0 0 1 0 0
0 1 1 1 0 0 1 1 1
1 0 0 0 0 0 1 1 0
1 0 0 1 0 1 0 0 1
1 0 1 0 1 0 0 0 0
1 0 1 1 1 0 0 0 1
1 1 0 0 1 0 0 1 0
1 1 0 1 1 0 0 1 1
1 1 1 0 1 0 1 0 0
1 1 1 1 1 0 1 0 1

K-maps:
AB\ 00 01 11 10
CD
00 0 0 0 0

01 0 0 0 0

11 1 1 1 1

10 0 0 1 1

E = AB + AC

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AB\ 00 01 11 10
CD
00 0 0 0 0

01 0 0 0 0

11 0 0 0 0

10 1 1 0 0

F = AB’C’

AB\ 00 01 11 10
CD
00 0 0 0 0

01 1 1 1 1

11 0 0 1 1

10 0 0 0 0

G = A’B + BC

AB\ 00 01 11 10
CD
00 0 0 1 1

01 0 0 1 1

11 1 1 0 0

10 0 0 0 0

H = A’C + ABC’

AB\ 00 01 11 10
CD
00 0 1 1 0

01 0 1 1 0

11 0 1 1 0

10 0 1 1 0

I=

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Circuit diagram

Lab 06
Implement Half Adder

Circuit needs two binary inputs and two binary outputs. The input variables designate
the augend and addend bits; the output variables produce the sum and carry. It is necessary to S
specify two output variables because the result may consist of two binary digits.
We arbitrarily assign symbols x and y to the two inputs and
S (for sum) and C (for carry) to the outputs. A
Half Adder C
Truth Table B

A B S C
0 0 0 0

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 0 1 1 0
1 0 1 0
1 1 0 1

K-map:
A\B 0 1
0 0 1
1 1 0
S = A’B + AB’

S = A xor B

A\B 0 1
0 0 0
1 0 1
C = AB

Circuit Diagram

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 Impementing 7 – segment

A BCD to Seven Segment decoder is a

combinational logic circuit that accepts a
decimal digit in BCD (input) and generates
appropriate outputs for the segments to
display the input decimal digit.

Truth Table

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 A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1

AB \ CD 00 01 11 10
00 1 0 1 1
01 0 1 1 1
11 0 0 0 0
10 1 1 0 0
a = A’C+A’B’D’+A’BD+AB’C’

AB \ CD 00 01 11 10
00 1 1 1 1
01 1 0 1 0
11 0 0 0 0

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 10 1 1 0 0
b = A’B’+B’C’+A’C’D’+A’CD

AB \ CD 00 01 11 10
00 1 1 1 0
01 1 1 1 1
11 0 0 0 0
10 1 1 0 0
c = B’C’+A’B+A’CD

AB \ CD 00 01 11 10
00 1 0 1 1
01 0 1 0 1
11 0 0 0 0
10 1 1 0 0
d = AB’C’+B’C’D’+A’B’C+A’BC’D

AB \ CD 00 01 11 10
00 1 0 0 1
01 0 0 0 1
11 0 0 0 0
10 1 0 0 0
e = B’C’D’+A’CD’

AB \ CD 00 01 11 10
00 1 0 0 1
01 1 1 0 1
11 0 0 0 0
10 1 1 0 0

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f = A’D’+AB’C’+A’BC’

AB \ CD 00 01 11 10
00 0 0 1 1
01 1 1 0 1
11 0 0 0 0
10 1 1 0 0
g = A’BC’+A’B’C+A’CD’+AB’C’

Circuit Diagram

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 LAB 07
Implementing Full Adder
A combinational circuit that performs the addition of 3 bits is called a full adder.
Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM.

Block Diagram
A
S
B Full Adder Cout

Cin

Truth Table:
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
K-map:

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 A\B Cin 00 01 11 10

0 1 1

1 1 1

S = A’B’Cin+A’BCin’ + AB’Cin’ +ABCin

S = A xor B xor Cin

Circuit Diagram

K-map:

A\B Cin 00 01

0 0 0

1 0 1

Cout = BCin +
ACin + AB

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 Implementing Half Subtractor

A half-subtractor is a combinational circuit that subtracts Block Diagram

two bits and produces their difference.

A D
B Half Subtractor b
Truth table:
A B D b
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
K-map
A\B 0 1

0 1

1 1

D = A’B + AB’

D = A xor B

Circuit Diagram

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Equivalent Circuit Diagram

K- map:
A\B 0 1

0 1

B = A’B

Circuit Diagram

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 Implementing Full Subtractor

BlockDiagram
B
A full-subtractor is a combinational circuit that performs A
a subtraction between two bits, taking into account that Full
a 1 may have been borrowed by a lower significant stage. B bout
Subtractor

bin

Truth table:
A B bin D bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-map:

A\B bin 00 01 11 10

0 1 1

1 1 1

D = A xor B xor bin

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K-map:

00 01 11 10
A\B bin

0 1 1 1

1 1

bout = A’bin + A’B + Bbin

Circuit Diagram

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 Lab 08
Implementing N – Bit Full Adder

Digital Adder is a digital device capable of adding two digital n-bit binary numbers,
where n depends on the circuit implementation. Digital adder adds two binary numbers A and B
to produce a sum S and a carry C

For A0B0: For A1B1:

S = A0 XOR B0 XOR Cin0 S = A1 XOR B1 XOR Cin1
= 1 XOR 0 XOR 0 = 0 XOR 1 XOR 0
=1 =0
Cout = A1B1 + B1Cin1 + Cin1A1
= 0.1 + 1.0 + 0.0
=0

For A2B2:
S = A1 XOR B1 XOR Cin2
= 1 XOR 0 XOR 0
=0
Cout = A2B2 + B2 Cin2+cin2 A2
= 1.0 + 0.0 + 0.1
=0

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For A3B3:
S = A3 XOR B3 XOR Cin3
= 0 XOR 1 XOR 0
=1
Cout = A3B3 + B3 Cin3 + Cin A3
= 0.1 + 1.0 + 0.0
=0

2k19-bscs-116

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 Implementing BCD to Excess 3 Conversion

The Excess-3 binary code is an example of a self-complementary BCD code.

A self-complementary binary code is a code which is always complimented in
itself. The process of converting BCD to Excess-3 is quite simple from other
conversions.

Truth Table
Decimal BCD Excess 3
B03 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0

K – map:
B3 B2 \ B1 00 01 11 10
B0
00 0 0 0 0
01 0 1 1 1
11 x x x x
10 1 1 x x
E3 = B3 + B0B2 + B2B1

B3 B2 \ B1 B0 00 01 11 10

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 00 0 1 1 1
01 1 0 0 0
11 x x x x
10 0 1 x x
E2 = B2’B0 +B2’B1 + B2B1’B0’

B3 B2 \ B1 B0 00 01 11 10

00 1 0 1 0
01 1 0 1 0
11 x x x x
10 1 0 x x
E1 = B0’B1’ + B0B1

B3 B2 \ B1 B0 00 01 11 10

00 1 0 0 1
01 1 0 0 1
11 x x x x
10 1 0 x x

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E0 = B0’
Circuit Diagram

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 Lab 09
Implementing ecoder
A decoder is a combinational circuit that converts n inputs into 2n inputs.
Block Diagram
A Decoder Y3
Y2
B 2x4 Y1
Y0
Truth Table:
E A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Circuit Diagram

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Truth Table:
E A B Y3 Y2 Y1 Y0
0 x x 1 1 1 1
1 0 0 1 1 1 0
1 0 1 1 1 0 1
1 1 0 1 0 1 1
1 1 1 0 1 1 1

Circuit Diagram:

E A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
Truth Table

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Circuit Diagram

Truth Table
E E’ A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 1 X X x 1 1 1 1 1 1 1 1
1 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 1 1 1 1 1 1 0 1 1 1
1 0 1 0 0 1 1 1 0 1 1 1 1
1 0 1 0 1 1 1 0 1 1 1 1 1
1 0 1 1 0 1 0 1 1 1 1 1 1
1 0 1 1 1 0 1 1 1 1 1 1 1

59 | P a g e
 Lab 10
Implementing Decoder

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 Implementing Multiplexer

Multiplexer is a combinational logic circuit used to select only one input among several inputs
based on selection lines. This acts as a digital switch. This is also known as data selector. For a
MUX there can be 2^n inputs, n selection lines by only one input.

 2x1

S Y

0 D0

1 D1

Y = S’D0+SD1

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 4x1
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Y = S1’S0’D0 + S’S0D1 + S1S0’D2 + S1S0D3’

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 8x1

Truth Table
S2 S1 S0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
Y = S2’S1’S0’D0 + S2’S1’S0D1 + S2’S1S0’D2 + S2’S1S0D3 + S2S1’S0’D4 + S2S1’S0D5 + S2S1S0’D6 +
S2S1S0D7

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 A XNOR B XOR C
A B C A XNOR B XOR C
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

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Circuit Diagram

65 | P a g e
 Lab 11
Implementing Sequential Circuit
Sequential circuit is a combinational circuit with memory.
 The output of sequential circuit depend upon
present input and past out(present state).
 A sequential circuit is specified by a time
sequence of inputs, outputs, and internal
states.
 The information stored in sequential circuit Feedback
represents present state.
 The present state and present input will
define output and next state.

SR Latch
SR Latch (NOR Gate)
Truth Table
S R Q Q’ State
1 0 1 0 Set
0 0 1 0 Previous
0 1 0 1 Reset
0 0 0 1 Previous
1 1 0 0 Forbidden

1. S = 0, R =1 , Q = 0 , Q’ = 1
S =0, R = 0, Q = 0 , Q’ = 1

2. S=1 , R = 0 , Q = 1 , Q’ = 0
S = 0 , R = 0 , Q = 1 , Q’ = 0

3. S = 1 , R =1 , Q = 0 , Q’ = 0 Forbidden

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Circuit Diagram

SR Latch( NAND Gate)

Truth Table
S R Q Q’ State
0 0 1 0 Forbidden
0 1 1 0 Set
1 1 0 1 Previous
1 0 0 1 Reset
1 1 0 1 Previous

1. S= 0, R =1 , Q = 1, Q’ = 0
S =1, R = 1, Q = 1, Q’ = 0

2. S = 1, R = 0, Q = 0, Q’ =1
S= 1 , R = 1 , Q = 0, Q’=1

3. S = 0, R = 0, Q = 1 , Q’ = 1

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Circuit Diagram

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 LAB 12
Implementing SR Flip Flop
Block Diagram
 Flip-Flops (FFs) are devices used in the digital field for a
variety of purposes.
 Flip-flops are used to store data temporarily.
 Flip-flops are bistable multivibrators.It is used in digital
equipment, are identified by the inputs.
 They may have from two up to five inputs depending on the
type. They are all common in one respect. They have two,
and only two, distinct output states.

NAND
0 0 1
0 1 1
1 0 1
1 1 0

SR Latch NAND Gate

S R Q Q
0 0 Invalid
0 1 1 0
1 0 0 1
1 1 Memory

SR Flip Flop Truth Table

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Clk S R Q Q’
0 x x Memory
1 0 0 Memory
1 0 1 0 1
1 1 0 1 0
1 1 1 Invalid

Characteristic Table
Clk S R Qn Qn+1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 Invalid
1 1 1 1 Invalid

Excitation Table
Q Qn+1 S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0

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 Lab 13
Implementing J-K Flip Flop

 The JK Flip-flop is the most widely used flip-flop.

 It is considered to be a universal flip-flop circuit.
 The sequential circuit of the JK Flip-flop is the same as for the RS Flip-flop with the same
SET and RESET input.
 The difference is that the JK flip-flop does not invalid input states of the RS latch (when S
and R are both 1).
 The JK Flip-flop name has been kept on the inventor name of the circuit known as JACK
KILBY.
 The basic NAND Gate RS flip-flop suffers from the two main problems.
 Firstly, the condition when S=0 and R=0 should be avoided.
 Secondly, if the state of S or R changes its state which the input which is enable is high,
the correct latching action does not occur.
 Block Diagram:

Truth Table:

CLK J K Q Q’
0 X X Memory
1 0 0 Memory
1 0 1 0 1
1 1 0 1 0
1 1 0 Toggle

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Characteristics Table:

CLK J K Qn Qn+1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

Excitation Table:
Q Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Circuit Diagram:

72 | P a g e
J-K Flip-flop IC:

73 | P a g e
 Implementation of D Flip-flop

 One of the main disadvantages of the basic SR NAND Gate bistable circuit is that the
indeterminate input condition of SET=”0” and RESET=”0” is forbidden.
 This state will force both outputs to be logics “1”, over-riding the feedback latching
action and whichever input goes to logic level “1” first will lose control, while the other
input still at logic “0” controls the resulting state of the latch.
 But in order to prevent this from happening an inventor can be connected between the
“SET” and the “RESET” inputs to produce another type of flip-flop circuit known as a
data latch. Delay flip-flop, D-type bistable, D-type flip-flop or just simply a D Flip-flop as
it is more generally called.
 The D flip-flop is by far the most important of the clocked Flip-flop as it ensures that
inputs S and R are never equal to one at the same time. The D-type flip-flop are
constructed from a gated SR Flip-flop with an inventor added between the S and the R
inputs to allow for a single D (data) input.

Truth Table Flip-flop:

CLK S R Q Q’
0 X X Memory
1 0 0 Memory
1 0 1 0 1
1 1 0 1 0
1 1 1 Invalid

Truth Table:

CLK D Q Q’
0 X Memory
1 0 0 1
1 1 1 0

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Characteristics Table:
CLK D Qn Qn+1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

Excitation table:
Q Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1

Circuit Diagram:

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D-Flipflop IC Circuit:

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 Lab 14
Implementation of T Flip Flop

The T flip flop is a single input modified version of the JK flip flop that allows it to operate in
toggling region. The “T” in “T flip-flop” stands for “toggle.” When you toggle a light switch, you
are changing from one state (on or off) to the other state (off or on). Whenever the clock signal
is LOW, the input doesn’t affect the output state. The clock signal has to be high for the inputs
to get active.
T flip-flops are handy when you need to reduce the frequency of a clock signal: If you keep
the T input at logic high and use the original clock signal as the flip-flop clock, the output will
change state once per clock period (assuming that the flip-flop is not sensitive to both clock
edges). Thus, the output clock will be half the frequency of the input clock.

Truth Table:
Clk T Q Q’
0 X Mem
1 0 Mem
1 1 Toggle

Characteristic Table
Clk T Qn Qn+1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Excitation Table
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0

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Circuit Diagram

78 | P a g e
 Implementing Master-Slave JK Flip Flop

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together

in a series configuration. Out of these, one acts as the “master” and the other as a “slave”. The
output from the master flip flop is connected to the two inputs of the slave flip flop whose
output is fed back to inputs of the master flip flop.
The circuit also includes an inverter. The inverter is connected to clock pulse in such a way
that the inverted clock pulse is given to the slave flip-flop. Therefore, if clock signal =0 for a
master flip-flop, then clock signal =1 for a slave flip-flop and if clock signal =1 for master flip flop
then it becomes 0 for slave flip flop and vice versa.

Truth Table:
Clk J K Qm Qm+1 Qn Qn+1
0->1 0 0 Hold Hold
1->0 0 0 Hold Hold
0->1 0 1 0 1 Hold
1->0 0 1 Hold 0 1
0->1 1 0 1 0 Hold
1->0 1 0 Hold 1 0
0->1 1 1 Toggle Hold
1->0 1 1 Hold Toggle

Circuit Diagram

79 | P a g e
 Lab 15
Implementation of Registers

A register is a device used to store the information from multiple bits of multiple flip
flops connected to each other. This information stored can be transferred with the help of shift
registers.
Flip-flops can be used to store a single bit of binary data. However in order to store
multiple bits of data, we need multiple flip-flops. N Flip-flops are to be connected in an order to
store n bits of data.
The information within these registers can be transferred with the help of shift registers.

1 bit 1 bit 1 bit 1 bit

4- bit register

Circuit Diagram

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Equivalent Logic Diagram

Shift Registers
Shift registers are digital memory circuitry found in devices such as calculators,
computers, and data processing systems. With the shift register, data or bits are entered into
the system in a serial or parallel manner. They enter from one direction, and as more data is
added, shift positions until they get to the output end. The two ends are referred to as the left
and right ends. Shift registers can serve as data storage spaces or data movement devices.

There are four types of Shift Registers:

1. Serial in Serial Out Shift Register
2. Serial in Parallel Out Shift Register
3. Parallel in Serial Out Shift Register
4. Parallel in Parallel Out Shift Register

81 | P a g e
Left Shift SISO
An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a
single bit of data. The registers which will shift the bits to left are called “Shift left registers”

Truth Table:
D3 D2 D1 D0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 1
0 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1

Graph:

Q0

Q1

Q2

Q3

Circuit Diagram

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Right Shift SISO

Truth Table
D3 D2 D1 D0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0
1 1 0 0 1 1 0 0
1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 1

Circuit Diagram

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