M29F800AT M29F800AB: 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Single Supply Flash Memory
M29F800AT M29F800AB: 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Single Supply Flash Memory
M29F800AT M29F800AB: 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Single Supply Flash Memory
M29F800AB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
Single Supply Flash Memory
PRELIMINARY DATA
■ ELECTRONIC SIGNATURE G RB
– Manufacturer Code: 0020h RP
– M29F800AT Device Code: 00ECh
– M29F800AB Device Code: 0058h
VSS
AI02198B
A15 1 48 A16
A14 BYTE RB 1 44 RP
A13 VSS A18 2 43 W
A12 DQ15A–1 A17 3 42 A8
A11 DQ7 A7 4 41 A9
A10 DQ14 A6 5 40 A10
A9 DQ6 A5 6 39 A11
A8 DQ13 A4 7 38 A12
NC DQ5 A3 8 37 A13
NC DQ12 A2 9 36 A14
W DQ4 A1 10 35 A15
RP 12 37 VCC A0 11 M29F800AT 34 A16
M29F800AT
NC 13 M29F800AB 36 DQ11 E 12 M29F800AB 33 BYTE
NC DQ3 VSS 13 32 VSS
RB DQ10 G 14 31 DQ15A–1
A18 DQ2 DQ0 15 30 DQ7
A17 DQ9 DQ8 16 29 DQ14
A7 DQ1 DQ1 17 28 DQ6
A6 DQ8 DQ9 18 27 DQ13
A5 DQ0 DQ2 19 26 DQ5
A4 G DQ10 20 25 DQ12
A3 VSS DQ3 21 24 DQ4
A2 E DQ11 22 23 VCC
AI02101B
A1 24 25 A0
AI02199
2/21
M29F800AT, M29F800AB
The blocks in the memory are asymmetrically ar- Data Inputs/Outputs (DQ0-DQ7). The Data In-
ranged, see Tables 3A and 3B, Block Addresses. puts/Outputs output the data stored at the selected
The first or last 64 Kbytes have been divided into address during a Bus Read operation. During Bus
four additional blocks. The 16 Kbyte Boot Block Write operations they represent the commands
can be used for small initialization code to start the sent to the Command Interface of the internal state
microprocessor, the two 8 Kbyte Parameter machine.
Blocks can be used for parameter storage and the Data Inputs/Outputs (DQ8-DQ14). The Data In-
remaining 32K is a small Main Block where the ap- puts/Outputs output the data stored at the selected
plication may be stored. address during a Bus Read operation when BYTE
Chip Enable, Output Enable and Write Enable sig- is High, VIH. When BYTE is Low, VIL, these pins
nals control the bus operation of the memory. are not used and are high impedance. During Bus
They allow simple connection to most micropro- Write operations the Command Register does not
cessors, often without additional logic. use these bits. When reading the Status Register
The memory is offered in TSOP48 (12 x 20mm) these bits should be ignored.
and SO44 packages. Access times of 70ns and Data Input/Output or Address Input (DQ15A-1).
90ns are available. The memory is supplied with When BYTE is High, V IH, this pin behaves as a
all the bits erased (set to ’1’). Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
SIGNAL DESCRIPTIONS pin; DQ15A–1 Low will select the LSB of the Word
See Figure 1, Logic Diagram, and Table 1, Signal on the other addresses, DQ15A–1 High will select
Names, for a brief overview of the signals connect- the MSB. Throughout the text consider references
ed to this device. to the Data Input/Output to include this pin when
Address Inputs (A0-A18). The Address Inputs BYTE is High and references to the Address In-
select the cells in the memory array to access dur- puts to include this pin when BYTE is Low except
ing Bus Read operations. During Bus Write opera- when stated explicitly otherwise.
tions they control the commands sent to the
Command Interface of the internal state machine.
3/21
M29F800AT, M29F800AB
Table 3A. M29F800AT Block Addresses Table 3B. M29F800AB Block Addresses
Size Address Range Address Range Size Address Range Address Range
(Kbytes) (x8) (x16) (Kbytes) (x8) (x16)
16 FC000h-FFFFFh 7E000h-7FFFFh 64 F0000h-FFFFFh 78000h-7FFFFh
8 FA000h-FBFFFh 7D000h-7DFFFh 64 E0000h-EFFFFh 70000h-77FFFh
8 F8000h-F9FFFh 7C000h-7CFFFh 64 D0000h-DFFFF h 68000h-6FFFFh
32 F0000h-F7FFFh 78000h-7BFFFh 64 C0000h-CFFFF h 60000h-67FFFh
64 E0000h-EFFFF h 70000h-77FFFh 64 B0000h-BFFFFh 58000h-5FFFFh
64 D0000h-DFFFFh 68000h-6FFFFh 64 A0000h-AFFFFh 50000h-57FFFh
64 C0000h-CFFFFh 60000h-67FFFh 64 90000h-9FFFFh 48000h-4FFFFh
64 B0000h-BFFFF h 58000h-5FFFFh 64 80000h-8FFFFh 40000h-47FFFh
64 A0000h-AFFFF h 50000h-57FFFh 64 70000h-7FFFFh 38000h-3FFFFh
64 90000h-9FFFFh 48000h-4FFFFh 64 60000h-6FFFFh 30000h-37FFFh
64 80000h-8FFFFh 40000h-47FFFh 64 50000h-5FFFFh 28000h-2FFFFh
64 70000h-7FFFFh 38000h-3FFFFh 64 40000h-4FFFFh 20000h-27FFFh
64 60000h-6FFFFh 30000h-37FFFh 64 30000h-3FFFFh 18000h-1FFFFh
64 50000h-5FFFFh 28000h-2FFFFh 64 20000h-2FFFFh 10000h-17FFFh
64 40000h-4FFFFh 20000h-27FFFh 64 10000h-1FFFFh 08000h-0FFFFh
64 30000h-3FFFFh 18000h-1FFFFh 32 08000h-0FFFFh 04000h-07FFFh
64 20000h-2FFFFh 10000h-17FFFh 8 06000h-07FFFh 03000h-03FFFh
64 10000h-1FFFFh 08000h-0FFFFh 8 04000h-05FFFh 02000h-02FFFh
64 00000h-0FFFFh 00000h-07FFFh 16 00000h-03FFFh 00000h-01FFFh
Chip Enable (E). The Chip Enable, E, activates The transition from VIH to VID must be slower than
the memory, allowing Bus Read and Bus Write op- tPHPHH.
erations to be performed. When Chip Enable is Ready/Busy Output (RB). The Ready/Busy pin
High, VIH, all other pins are ignored. is an open-drain output that can be used to identify
Output Enable (G). The Output Enable, G, con- when the memory array can be read. Ready/Busy
trols the Bus Read operation of the memory. is high-impedance during Read mode, Auto Select
Write Enable (W). The Write Enable, W, controls mode and Erase Suspend mode.
the Bus Write operation of the memory’s Com- After a Hardware Reset, Bus Read and Bus Write
mand Interface. operations cannot begin until Ready/Busy be-
Reset/Block Temporary Unprotect (RP). The Re- comes high-impedance. See Table 14 and Figure
set/Block Temporary Unprotect pin can be used to 10, Reset/Temporary Unprotect AC Characteris-
apply a Hardware Reset to the memory or to tem- tics.
porarily unprotect all blocks that have been pro- During Program or Erase operations Ready/Busy
tected. is Low, VOL. Ready/Busy will remain Low during
A Hardware Reset is achieved by holding Reset/ Read/Reset commands or Hardware Resets until
Block Temporary Unprotect Low, VIL, for at least the memory is ready to enter Read mode.
tPLPX. After Reset/Block Temporary Unprotect The use of an open-drain output allows the Ready/
goes High, V IH, the memory will be ready for Bus Busy pins from several memories to be connected
Read and Bus Write operations after tPHEL or to a single pull-up resistor. A Low will then indicate
tRHEL, whichever occurs last. See the Ready/Busy that one, or more, of the memories is busy.
Output section, Table 14 and Figure 10, Reset/ Byte/Word Organization Select (BYTE). The Byte/
Temporary Unprotect AC Characteristics for more Word Organization Select pin is used to switch be-
details. tween the 8-bit and 16-bit Bus modes of the mem-
Holding RP at V ID will temporarily unprotect the ory. When Byte/Word Organization Select is Low,
protected blocks in the memory. Program and VIL, the memory is in 8-bit mode, when it is High,
Erase operations on all blocks will be possible. VIH, the memory is in 16-bit mode.
4/21
M29F800AT, M29F800AB
Bus Write VIL VIH VIL Command Address Hi-Z Data Input
Standby V IH X X X Hi-Z
5/21
M29F800AT, M29F800AB
6/21
M29F800AT, M29F800AB
Length
Command 1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1 X F0
Read/Reset
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
quires four Bus Write operations, the final write op- the Status Register on the Data Inputs/Outputs.
eration latches the address and data in the internal See the section on the Status Register for more
state machine and starts the Program/Erase Con- details.
troller. After the program operation has completed the
If the address falls in a protected block then the memory will return to the Read mode, unless an
Program command is ignored, the data remains error has occurred. When an error occurs the
unchanged. The Status Register is never read and memory will continue to output the Status Regis-
no error condition is given. ter. A Read/Reset command must be issued to re-
During the program operation the memory will ig- set the error condition and return to Read mode.
nore all commands. It is not possible to issue any Note that the Program command cannot change a
command to abort or pause the operation. Typical bit set at ’0’ back to ’1’ and attempting to do so will
program times are given in Table 6. Bus Read op- cause an error. One of the Erase Commands must
erations during the program operation will output be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
7/21
M29F800AT, M29F800AB
Chip Erase Command. The Chip Erase com- Controller starts it is not possible to select any
mand can be used to erase the entire chip. Six Bus more blocks. Each additional block must therefore
Write operations are required to issue the Chip be selected within 50µs of the last block. The 50µs
Erase Command and start the Program/Erase timer restarts when an additional block is selected.
Controller. The Status Register can be read after the sixth
If any blocks are protected then these are ignored Bus Write operation. See the Status Register for
and all the other blocks are erased. If all of the details on how to identify if the Program/Erase
blocks are protected the Chip Erase operation ap- Controller has started the Block Erase operation.
pears to start but will terminate within about 100µs, If any selected blocks are protected then these are
leaving the data unchanged. No error condition is ignored and all the other selected blocks are
given when protected blocks are ignored. erased. If all of the selected blocks are protected
During the erase operation the memory will ignore the Block Erase operation appears to start but will
all commands. It is not possible to issue any com- terminate within about 100µs, leaving the data un-
mand to abort the operation. Typical chip erase changed. No error condition is given when protect-
times are given in Table 6. All Bus Read opera- ed blocks are ignored.
tions during the Chip Erase operation will output During the Block Erase operation the memory will
the Status Register on the Data Inputs/Outputs. ignore all commands except the Erase Suspend
See the section on the Status Register for more and Read/Reset commands. Typical block erase
details. times are given in Table 6. All Bus Read opera-
After the Chip Erase operation has completed the tions during the Block Erase operation will output
memory will return to the Read Mode, unless an the Status Register on the Data Inputs/Outputs.
error has occurred. When an error occurs the See the section on the Status Register for more
memory will continue to output the Status Regis- details.
ter. A Read/Reset command must be issued to re- After the Block Erase operation has completed the
set the error condition and return to Read Mode. memory will return to the Read Mode, unless an
The Chip Erase Command sets all of the bits in un- error has occurred. When an error occurs the
protected blocks of the memory to ’1’. All previous memory will continue to output the Status Regis-
data is lost. ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more The Block Erase Command sets all of the bits in
blocks. Six Bus Write operations are required to the unprotected selected blocks to ’1’. All previous
select the first block in the list. Each additional data in the selected blocks is lost.
block in the list can be selected by repeating the Erase Suspend Command. The Erase Suspend
sixth Bus Write operation using the address of the Command may be used to temporarily suspend a
additional block. The Block Erase operation starts Block Erase operation and return the memory to
the Program/Erase Controller about 50µs after the Read mode. The command requires one Bus
last Bus Write operation. Once the Program/Erase Write operation.
8/21
M29F800AT, M29F800AB
The Program/Erase Controller will suspend within pend when an address within a block being erased
15µs of the Erase Suspend Command being is- is accessed.
sued. Once the Program/Erase Controller has The bits in the Status Register are summarized in
stopped the memory will be set to Read mode and Table 7, Status Register Bits.
the Erase will be suspended. If the Erase Suspend
Data Polling Bit (DQ7). The Data Polling Bit can
command is issued during the period when the
be used to identify whether the Program/Erase
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
Erase is suspended immediately and will start im-
The Data Polling Bit is output on DQ7 when the
mediately when the Erase Resume Command is
Status Register is read.
issued. It will not be possible to select any further
blocks for erasure after the Erase Resume. During Program operations the Data Polling Bit
During Erase Suspend it is possible to Read and outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
Program cells in blocks that are not being erased;
the Program operation the memory returns to
both Read and Program operations behave as
normal on these blocks. Reading from blocks that Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
are being erased will output the Status Register. It
plement.
is also possible to enter the Auto Select mode: the
memory will behave as in the Auto Select mode on During Erase operations the Data Polling Bit out-
all blocks until a Read/Reset command returns the puts ’0’, the complement of the erased state of
memory to Erase Suspend mode. DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/ In Erase Suspend mode the Data Polling Bit will
Erase Controller from Erase Suspend. An erase output a ’1’ during a Bus Read operation within a
can be suspended and resumed more than once. block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
STATUS REGISTER Controller has suspended the Erase operation.
Bus Read operations from any address always Figure 3, Data Polling Flowchart, gives an exam-
read the Status Register during Program and ple of how to use the Data Polling Bit. A Valid Ad-
Erase operations. It is also read during Erase Sus- dress is the address being programmed or an
address within the block being erased.
9/21
M29F800AT, M29F800AB
START START
NO YES
NO DQ5 NO DQ5
=1 =1
YES YES
NO YES
AI01369 AI01370
Toggle Bit (DQ6). The Toggle Bit can be used to gram, Block Erase or Chip Erase operation fails to
identify whether the Program/Erase Controller has write the correct data to the memory. If the Error
successfully completed its operation or if it has re- Bit is set a Read/Reset command must be issued
sponded to an Erase Suspend. The Toggle Bit is before other commands are issued. The Error bit
output on DQ6 when the Status Register is read. is output on DQ5 when the Status Register is read.
During Program and Erase operations the Toggle Note that the Program command cannot change a
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes- bit set at ’0’ back to ’1’ and attempting to do so will
sive Bus Read operations at any address. After cause an error. One of the Erase Commands must
successful completion of the operation the memo- be used to set all the bits in a block or in the whole
ry returns to Read mode. memory from ’0’ to ’1’.
During Erase Suspend mode the Toggle Bit will Erase Timer Bit (DQ3). The Erase Timer Bit can
output when addressing a cell within a block being be used to identify the start of Program/Erase
erased. The Toggle Bit will stop toggling when the Controller operation during a Block Erase com-
Program/Erase Controller has suspended the mand. Once the Program/Erase Controller starts
Erase operation. erasing the Erase Timer Bit is set to ’1’. Before the
Figure 4, Data Toggle Flowchart, gives an exam- Program/Erase Controller starts the Erase Timer
ple of how to use the Data Toggle Bit. Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Error Bit (DQ5). The Error Bit can be used to
Erase Timer Bit is output on DQ3 when the Status
identify errors detected by the Program/Erase
Register is read.
Controller. The Error Bit is set to ’1’ when a Pro-
10/21
M29F800AT, M29F800AB
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2.0V
1.3V
High Speed
1N914
3V
1.5V
0V 3.3kΩ
DEVICE
Standard UNDER OUT
TEST
2.4V CL = 30pF or 100pF
2.0V
0.8V
0.45V
AI01275B
Table 9. Capacitance
(TA = 25 °C, f = 1 MHz)
Symbol Parameter Test Condition Min Max Unit
C IN Input Capacitance V IN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Note: Sampled only, not 100% tested.
11/21
M29F800AT, M29F800AB
E = VCC ± 0.2V,
ICC3 Supply Current (Standby) CMOS 35 150 µA
RP = VCC ± 0.2V
Program/Erase
ICC4 (1) Supply Current (Program/Erase)
Controller active
20 mA
Alternative Toggle Bit (DQ2). The Alternative blocks being erased. Bus Read operations to ad-
Toggle Bit can be used to monitor the Program/ dresses within blocks not being erased will output
Erase controller during Erase operations. The Al- the memory cell data as if in Read mode.
ternative Toggle Bit is output on DQ2 when the After an Erase operation that causes the Error Bit
Status Register is read. to be set the Alternative Toggle Bit can be used to
During Chip Erase and Block Erase operations the identify which block or blocks have caused the er-
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with ror. The Alternative Toggle Bit changes from ’0’ to
successive Bus Read operations from addresses ’1’ to ’0’, etc. with successive Bus Read Opera-
within the blocks being erased. Once the operation tions from addresses within blocks that have not
completes the memory returns to Read mode. erased correctly. The Alternative Toggle Bit does
During Erase Suspend the Alternative Toggle Bit not change if the addressed block has erased cor-
changes from ’0’ to ’1’ to ’0’, etc. with successive rectly.
Bus Read operations from addresses within the
12/21
M29F800AT, M29F800AB
E = VIL,
tAVQV tACC Address Valid to Output Valid Max 70 90 ns
G = VIL
tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns
tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns
tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 20 20 ns
tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 20 20 ns
tEHQX
Chip Enable, Output Enable or
tGHQX tOH Min 0 0 ns
Address Transition to Output Transition
tAXQX
tELBL tELFL
Chip Enable to BYTE Low or High Max 5 5 ns
tELBH tELFH
tAVAV
A0-A18/
VALID
A–1
tAVQV tAXQX
tELQV tEHQX
tELQX tEHQZ
tGLQX tGHQX
tGLQV tGHQZ
DQ0-DQ7/
VALID
DQ8-DQ15
tBHQV
BYTE
13/21
M29F800AT, M29F800AB
tAVAV
A0-A18/
VALID
A–1
tWLAX
tAVWL tWHEH
tELWL tWHGL
tGHWL tWLWH
tWHWL
tDVWH tWHDX
DQ0-DQ7/
VALID
DQ8-DQ15
VCC
tVCHEL
RB
tWHRL AI02183
14/21
M29F800AT, M29F800AB
tAVAV
A0-A18/
VALID
A–1
tELAX
tAVEL tEHWH
tWLEL tEHGL
tGHEL tELEH
tEHEL
tDVEH tEHDX
DQ0-DQ7/
VALID
DQ8-DQ15
VCC
tVCHWL
RB
tEHRL AI02184
15/21
M29F800AT, M29F800AB
tPHWL (1)
RP High to Write Enable Low, Chip Enable Low,
tPHEL tRH Min 50 50 ns
Output Enable Low
(1)
tPHGL
tRHWL (1)
RB High to Write Enable Low, Chip Enable Low,
tRHEL (1) tRB Min 0 0 ns
Output Enable Low
(1)
tRHGL
W, E, G
RB
tPLPX
RP
tPHPHH
tPLYH
AI02931
16/21
M29F800AT, M29F800AB
Example: M29F800AB 70 N 1 T
Device Type
M29
Operating Voltage
F = VCC = 5V ± 10%
Device Function
800A = 8Mbit (1Mb x8 or 512Kb x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70 ns
90 = 90 ns
Package
N = TSOP48: 12 x 20 mm
M = SO44
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Optio n
T = Tape & Reel Packing
Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factory with the memory content erased (to FFFFh).
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
17/21
M29F800AT, M29F800AB
18/21
M29F800AT, M29F800AB
Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1 N
e
B
N/2
D1 A
D CP
DIE
TSOP-a A1 α L
Drawing is not to scale.
19/21
M29F800AT, M29F800AB
Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
e 1.27 – – 0.050 – –
H 15.90 16.10 0.626 0.634
L 0.80 – – 0.031 – –
α 3° – – 3° – –
N 44 44
CP 0.10 0.004
Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2 A
C
B
e CP
E H
1
A1 α L
SO-b
20/21
M29F800AT, M29F800AB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.
21/21