M48T59

M48T59Y/M48T59V

64 Kbit (8Kb x8) TIMEKEEPER® SRAM

PRELIMINARY DATA

■ INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL SNAPHAT (SH)
CIRCUIT and BATTERY Battery/Crytstal

■ FREQUENCY TEST OUTPUT for REAL TIME

CLOCK SOFTWARE CALIBRATION
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■ WRITE PROTECT VOLTAGES 28

(VPFD = Power-fail Deselect Voltage): 28 1

– M48T59: 4.5V ≤ VPFD ≤ 4.75V 1 PCDIP28 (PC)

Battery/Crystal
– M48T59Y: 4.2V ≤ VPFD ≤ 4.5V
SOH28 (MH) CAPHAT
– M48T59V: 2.7V ≤ VPFD ≤ 3.0V
■ SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
■ PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT® TOP Figure 1. Logic Diagram
(to be Ordered Separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
■ MICROPROCESSOR POWER-ON RESET VCC
(Valid even during battery back-up mode)
■ PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACK-UP MODE 13 8

■ BATTERY LOW FLAG A0-A12 DQ0-DQ7

Table 1. Signal Names W M48T59

A0-A12 Address Inputs M48T59Y
E M48T59V IRQ/FT
DQ0-DQ7 Data Inputs / Outputs
Interrupt / Frequency Test G RST
IRQ/FT
Output (Open Drain)
Power Fail Reset Output
RST
(Open Drain)
E Chip Enable VSS
AI01380E
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground

October 1999 1/21

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

This datasheet has been downloaded from http://www.digchip.com at this page

M48T59, M48T59Y, M48T59V

Figure 2A. DIP Connections Figure 2B. SOIC Connections

RST 1 28 VCC RST 1 28 VCC

A12 2 27 W A12 2 27 W
A7 3 26 IRQ/FT A7 3 26 IRQ/FT
A6 4 25 A8 A6 4 25 A8
A5 5 24 A9 A5 5 24 A9
A4 6 23 A11 A4 6 23 A11
A3 7 M48T59 22 G A3 7 M48T59Y 22 G
A2 8 M48T59Y 21 A10 A2 8 M48T59V 21 A10
A1 9 20 E A1 9 20 E
A0 10 19 DQ7 A0 10 19 DQ7
DQ0 11 18 DQ6 DQ0 11 18 DQ6
DQ1 12 17 DQ5 DQ1 12 17 DQ5
DQ2 13 16 DQ4 DQ2 13 16 DQ4
VSS 14 15 DQ3 VSS 14 15 DQ3
AI01381D AI01382E

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
Grade 1 0 to 70
TA Ambient Operating Temperature °C
Grade 6 –40 to 85
TSTG Storage Temperature (VCC Off, Oscillator Off) –40 to 85 °C
TSLD (2) Lead Solder Temperature for 10 seconds 260 °C
VIO Input or Output Voltages –0.3 to 7 V
M48T59/M48T59Y –0.3 to 7
VCC Supply Voltage V
M48T59V –0.3 to 4.6
IO Output Current 20 mA
PD Power Dissipation 1 W
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Table 3. Operating Modes (1)

Mode VCC E G W DQ7-DQ0 Power
Deselect 4.75V to 5.5V VIH X X High Z Standby
Write or VIL X VIL DIN Active
4.5V to 5.5V
Read or VIL VIL VIH DOUT Active
Read 3.0V to 3.6V VIL VIH VIH High Z Active
Deselect (2) X X X High Z CMOS Standby
VSO to VPFD (min)
Deselect ≤ VSO X X X High Z Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.

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 M48T59, M48T59Y, M48T59V

Figure 3. Block Diagram

IRQ/FT

OSCILLATOR AND 16 x 8 BiPORT

CLOCK CHAIN SRAM ARRAY

32,768 Hz
CRYSTAL A0-A12

POWER

DQ0-DQ7
8176 x 8
SRAM ARRAY
LITHIUM
CELL E

VOLTAGE SENSE W
VPFD
AND
SWITCHING G
CIRCUITRY

VCC RST VSS

AI01383D

DESCRIPTION Table 4. AC Measurement Conditions

The M48T59/59Y/59V TIMEKEEPER ® RAM is an Input Rise and Fall Times ≤ 5ns
8Kb x8 non-volatile static RAM and real time clock.
The monolithic chip is available in two special Input Pulse Voltages 0 to 3V
packages to provide a highly integrated battery Input and Output Timing Ref. Voltages 1.5V
backed-up memory and real time clock solution.
Note that Output Hi-Z is defined as the point where data is no longer
The M48T59/59Y/59V is a non-volatile pin and driven.
function equivalent to any JEDEC standard 8Kb x8
SRAM. It also easily fits into many ROM, EPROM,
Figure 4. AC Testing Load Circuit
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed.
The 28 pin 600mil DIP CAPHAT™ houses the
645Ω
M48T59/59Y/59V silicon with a quartz crystal and DEVICE
a long life lithium button cell in a single package. UNDER
TEST
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
CL = 100pF 1.75V
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface- CL includes JIG capacitance
AI02325
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
Note: Excluding open-drain output pins.

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M48T59, M48T59Y, M48T59V

Table 5. Capacitance (1, 2)

(TA = 25 °C)
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 10 pF

CIO (3) Input / Output Capacitance VOUT = 0V 10 pF

Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.

Table 6. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
M48T59/Y M48T59V
Symbol Parameter Test Condition Unit
Min Max Min Max

ILI (1) Input Leakage Current 0V ≤ VIN ≤ VCC ±1 ±1 µA

ILO (1) Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 ±1 µA

ICC Supply Current Outputs open 50 30 mA

Supply Current (Standby)
ICC1 E = VIH 3 2 mA
TTL
Supply Current (Standby)
ICC2 E = VCC – 0.2V 3 1 mA
CMOS

VIL (2) Input Low Voltage –0.3 0.8 –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 2 VCC + 0.3 V

Output Low Voltage IOL = 2.1mA 0.4 0.4 V

VOL Output Low Voltage (IRQ/FT
IOL = 10mA 0.4 0.4 V
and RST) (3)
VOH Output High Voltage IOH = –1mA 2.4 2.4 V
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
3. The IRQ/FT and RST pins are Open Drain.

Table 7. Power Down/Up Trip Points DC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C)
Symbol Parameter Min Typ Max Unit
M48T59 4.5 4.6 4.75 V
VPFD Power-fail Deselect Voltage M48T59Y 4.2 4.35 4.5 V
M48T59V 2.7 2.9 3.0 V
M48T59/Y 3.0 V
VSO Battery Back-up Switchover Voltage
M48T59V VPFD –100mV V

Grade 1 7 YEARS
tDR ExpectedDataRetentionTime(at25°C)
Grade 6 10 (2) YEARS
Note: 1. All voltages referenced to VSS.
2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).

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 M48T59, M48T59Y, M48T59V

Table 8. Power Down/Up AC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C)
Symbol Parameter Min Max Unit
tPD E or W at VIH before Power Down 0 µs

tF (1) VPFD (max) to VPFD (min) VCC Fall Time 300 µs

M48T59/Y 10 µs
tFB (2) VPFD (min) to VSS VCC Fall Time
M48T59V 150 µs
tR VPFD (min) to VPFD (max) VCC Rise Time 10 µs

tRB VSS to VPFD (min) VCC Rise Time 1 µs

tREC (3) VPFD (max) to RST High 40 200 ms

Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
es V PFD (min).
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
3. tREC (min) = 20ms for industrial temperature grade 6 device.

Figure 5. Power Down/Up Mode AC Waveforms

VCC
VPFD (max)

VPFD (min)

VSO

tF tR
tPD tFB tRB
tDR
tREC

RST

INPUTS RECOGNIZED DON'T CARE RECOGNIZED

HIGH-Z
OUTPUTS VALID VALID
(PER CONTROL INPUT) (PER CONTROL INPUT)
AI03258

The SOIC and battery/crystal packages are The two circuits are interconnected at the upper
shipped separately in plastic anti-static tubes or in eight memory locations to provide user accessible
Tape & Reel form. For the 28 lead SOIC, the bat- BYTEWIDE™ clock information in the bytes with
tery/crystal package (i.e. SNAPHAT) part number addresses 1FF8h-1FFFh. The clock locations
is "M4T28-BR12SH" or “M4T32-BR12SH”. contain the century, year, month, date, day, hour,
Caution: Do not place the SNAPHAT battery/crys- minute, and second in 24 hour BCD format (except
tal top in conductive foam, as this will drain the lith- for the century). Corrections for 28, 29 (leap year),
ium button-cell battery. 30, and 31 day months are made automatically.
Byte 1FF8h is the clock control register. This byte
As Figure 3 shows, the static memory array and controls user access to the clock information and
the quartz controlled clock oscillator of the
also stores the clock calibration setting.
M48T59/59Y/59V are integrated on one silicon
chip.

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M48T59, M48T59Y, M48T59V

Table 9. Read Mode AC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
M48T59/M48T59Y/M48T59V
Symbol Parameter -70 Unit
Min Max
tAVAV Read Cycle Time 70 ns

tAVQV (1) Address Valid to Output Valid 70 ns

tELQV (1) Chip Enable Low to Output Valid 70 ns

tGLQV (1) Output Enable Low to Output Valid 35 ns

tELQX (2) Chip Enable Low to Output Transition 5 ns

tGLQX (2) Output Enable Low to Output Transition 5 ns

tEHQZ (2) Chip Enable High to Output Hi-Z 25 ns

tGHQZ (2) Output Enable High to Output Hi-Z 25 ns

tAXQX (1) Address Transition to Output Transition 10 ns

Note: 1. CL = 100pF (see Fig 4).
2. CL = 5pF (see Fig 4).

Figure 6. Read Mode AC Waveforms.

tAVAV

A0-A12 VALID

tAVQV tAXQX

tELQV tEHQZ

tELQX

tGLQV tGHQZ

tGLQX
DQ0-DQ7 VALID

AI01385

Note: Write Enable (W) = High.

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 M48T59, M48T59Y, M48T59V

Table 10. Write Mode AC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
M48T59/M48T59Y/M48T59V
Symbol Parameter -70 Unit
Min Max
tAVAV Write Cycle Time 70 ns

tAVWL Address Valid to Write Enable Low 0 ns

tAVEL Address Valid to Chip Enable Low 0 ns

tWLWH Write Enable Pulse Width 50 ns

tELEH Chip Enable Low to Chip Enable High 55 ns

tWHAX Write Enable High to Address Transition 0 ns

tEHAX Chip Enable High to Address Transition 0 ns

tDVWH Input Valid to Write Enable High 30 ns

tDVEH Input Valid to Chip Enable High 30 ns

tWHDX Write Enable High to Input Transition 5 ns

tEHDX Chip Enable High to Input Transition 5 ns

tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 ns

tAVWH Address Valid to Write Enable High 60 ns

tAVE1H Address Valid to Chip Enable High 60 ns

tWHQX (1, 2) Write Enable High to Output Transition 5 ns

Note: 1. CL = 5pF (see Fig 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

The eight clock bytes are not the actual clock READ MODE
counters themselves; they are memory locations The M48T59/59Y/59V is in the Read Mode when-
consisting of BiPORT™ read/write memory cells. ever W (Write Enable) is high and E (Chip Enable)
The M48T59/59Y/59V includes a clock control cir- is low. The unique address specified by the 13 Ad-
cuit which updates the clock bytes with current in- dress Inputs defines which one of the 8,192 bytes
formation once per second. The information can of data is to be accessed. Valid data will be avail-
be accessed by the user in the same manner as able at the Data I/O pins within Address Access
any other location in the static memory array. time (t AVQV) after the last address input signal is
The M48T59/59Y/59V also has its own Power-fail stable, providing that the E and G access times
Detect circuit. The control circuitry constantly mon- are also satisfied. If the E and G access times are
itors the single 5V supply for an out of tolerance not met, valid data will be available after the latter
condition. When V CC is out of tolerance, the circuit of the Chip Enable Access time (tELQV) or Output
write protects the SRAM, providing a high degree Enable Access time (tGLQV).
of data security in the midst of unpredictable sys- The state of the eight three-state Data I/O signals
tem operation brought on by low V CC. As VCC falls is controlled by E and G. If the outputs are activat-
below approximately 3V, the control circuitry con- ed before t AVQV, the data lines will be driven to an
nects the battery which maintains data and clock indeterminate state until tAVQV. If the Address In-
operation until valid power returns. puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.

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M48T59, M48T59Y, M48T59V

Figure 7. Write Enable Controlled, Write AC Waveform

tAVAV

A0-A12 VALID

tAVWH

tAVEL tWHAX

tWLWH

tAVWL

W
tWLQZ tWHQX

tWHDX

DQ0-DQ7 DATA INPUT

tDVWH
AI01386

Figure 8. Chip Enable Controlled, Write AC Waveforms

tAVAV

A0-A12 VALID

tAVEH

tAVEL tELEH tEHAX

tAVWL

tEHDX

DQ0-DQ7 DATA INPUT

tDVEH
AI01387B

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 M48T59, M48T59Y, M48T59V

WRITE MODE DATA RETENTION MODE

The M48T59/59Y/59V is in the Write Mode when- With valid V CC applied, the M48T59/59Y/59V op-
ever W and E are low. The start of a write is refer- erates as a conventional BYTEWIDE static RAM.
enced from the latter occurring falling edge of W or Should the supply voltage decay, the RAM will au-
E. A write is terminated by the earlier rising edge tomatically power-fail deselect, write protecting it-
of W or E. The addresses must be held valid self when V CC falls within the VPFD (max), VPFD
throughout the cycle. E or W must return high for (min) window. All outputs become high imped-
a minimum of tEHAX from Chip Enable or tWHAX ance, and all inputs are treated as "don’t care."
from Write Enable prior to the initiation of another Note: A power failure during a write cycle may cor-
read or write cycle. Data-in must be valid tDVWH rupt data at the currently addressed location, but
prior to the end of write and remain valid for tWHDX does not jeopardize the rest of the RAM’s content.
afterward. G should be kept high during write cy- At voltages below V PFD (min), the user can be as-
cles to avoid bus contention; although, if the output sured the memory will be in a write protected state,
bus has been activated by a low on E and G a low provided the VCC fall time is not less than tF. The
on W will disable the outputs tWLQZ after W falls. M48T59/59Y/59V may respond to transient noise
spikes on VCC that reach into the deselect window

Table 11. Register Map

Data Function/Range
Address
D7 D6 D5 D4 D3 D2 D1 D0 BCD Format

1FFFh 10 Years Year Year 00-99

1FFEh 0 0 0 10 M Month Month 01-12
1FFDh 0 0 10 Date Date Date 01-31
1FFCh 0 FT CB CEB 0 Day Century/Day 00-01/01-07
1FFBh 0 0 10 Hours Hours Hour 00-23
1FFAh 0 10 Minutes Minutes Minutes 00-59
1FF9h ST 10 Seconds Seconds Seconds 00-59
1FF8h W R S Calibration Control
1FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
1FF6h AFE Y ABE Y Y Y Y Y Interrupts
1FF5h RPT4 Y Al. 10 Date Alarm Date Alarm Date 01-31
1FF4h RPT3 Y Al. 10 Hours Alarm Hours Alarm Hours 00-23
1FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm Minutes 00-59
1FF2h RPT1 Alarm 10 Seconds Alarm Seconds Alarm Seconds 00-59
1FF1h Y Y Y Y Y Y Y Y Unused
1FF0h WDF AF Z BL Z Z Z Z Flags

Keys: S = SIGN Bit WDS = Watchdog Steering Bit

FT = FREQUENCY TEST Bit BMB0-BMB4 = Watchdog Multiplier Bits
R = READ Bit RB0-RB1 = Watchdog Resolution Bits
W = WRITE Bit AFE = Alarm Flag Enable
ST = STOP Bit ABE = Alarm in Battery Back-up Mode Enable
0 = Must be set to zero RPT1-RPT4 = Alarm Repeat Mode Bits
Y = ’1’ or ’0’ WDF = Watchdog Flag
Z = ’0’ and are Read only CEB = Century Enable Bit
AF = Alarm Flag CB = Century Bit
BL = Battery Low

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M48T59, M48T59Y, M48T59V

during the time the device is sampling V CC. There- condition reset will not occur unless the addresses
fore, decoupling of the power supply lines is rec- are stable at the flag location for at least 15ns
ommended. while the divice is in the read mode as shown in
When VCC drops below VSO, the control circuit Figure 11.
switches power to the internal battery which pre- The IRQ/FT pin is an open drain output and re-
serves data and powers the clock. The internal quires a pull-up resistor (10kΩ recommended) to
button cell will maintain data in the M48T59/59Y/ VCC. The pin remains in the high impedance state
59V for an accumulated period of at least 7 years unless an interrupt occurs or the frequency test
when VCC is less than V SO. As system power re- mode is enabled.
turns and V CC rises above VSO , the battery is dis-
connected, and the power supply is switched to CLOCK OPERATIONS
external VCC. Deselect continues for tREC after Reading the Clock
VCC reaches VPFD (max).
Updates to the TIMEKEEPER registers should be
For more information on Battery Storage Life refer halted before clock data is read to prevent reading
to the Application Note AN1012. data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
POWER-ON RESET isters, and not the actual clock counters, updating
The M48T59/59Y/59V continuously monitors VCC. the registers can be halted without disturbing the
When V CC falls to the power fail detect trip point, clock itself.
the RST pulls low (open drain) and remains low on Updating is halted when a ’1’ is written to the
power-up for 40ms to 200ms after V CC passes READ bit, D6 in the Control register (1FF8h). As
VPFD. RST is valid for all VCC conditions. The RST long as a ’1’ remains in that position, updating is
pin is an open drain output and an appropriate re- halted.
sistor to VCC should be chosen to control rise time.
After a halt is issued, the registers reflect the
PROGRAMMABLE INTERRUPTS count; that is, the day, date, and the time that were
current at the moment the halt command was is-
The M48T59/59Y/59V provides two programma- sued.
ble interrupts; an alarm and a watchdog. When an
interrupt condition occurs, the M48T59/59Y/59V All of the TIMEKEEPER registers are updated si-
sets the appropriate flag bit in the flag register multaneously. A halt will not interrupt an update in
1FF0h. The interrupt enable bits in (AFE and ABE) progress. Updating is within a second after the bit
in 1FF6h and the Watchdog Steering (WDS) bit in is reset to a ’0’.
1FF7h allow the interrupt to activate the IRQ/FT Setting the Clock
pin. Bit D7 of the Control register (1FF8h) is the
The interrupt flags and the IRQ/FT output are WRITE bit. Setting the WRITE bit to a ’1’, like the
cleared by a read to the flags register. An interrupt READ bit, halts updates to the TIMEKEEPER reg-

Figure 9. Clock Calibration

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

AI00594B

10/21
 M48T59, M48T59Y, M48T59V

isters. The user can then load them with the cor- Calibrating the Clock
rect day, date, and time data in 24 hour BCD The M48T59/59Y/59V is driven by a quartz con-
format (see Table 12). Resetting the WRITE bit to trolled oscillator with a nominal frequency of
a ’0’ then transfers the values of all time registers 32,768Hz. The devices are tested not to exceed
(1FF9h-1FFFh) to the actual TIMEKEEPER 35 ppm (parts per million) oscillator frequency er-
counters and allows normal operation to resume. ror at 25°C, which equates to about ±1.53 minutes
After the WRITE bit is reset, the next clock update per month. With the calibration bits properly set,
will occur within approximately one second. the accuracy of each M48T59/59Y/59V improves
See the Application Note AN923 "TIMEKEEPER to better than +1/–2 ppm at 25°C.
rolling into the 21st century" for information on The oscillation rate of any crystal changes with
Century Rollover. temperature (see Figure 10). Most clock chips
Note: Upon power-up following a power failure, compensate for crystal frequency and tempera-
both the WRITE bit and the READ bit will be reset ture shift error with cumbersome trim capacitors.
to ‘0’. The M48T59/59Y/59V design, however, employs
Stopping and Starting the Oscillator periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
The oscillator may be stopped at any time. If the
circuit at the divide by 256 stage, as shown in Fig-
device is going to spend a significant amount of
ure 9. The number of times pulses are blanked
time on the shelf, the oscillator can be turned off to (subtracted, negative calibration) or split (added,
minimize current drain on the battery. The STOP
positive calibration) depends upon the value load-
bit is the MSB of the seconds register. Setting it to
ed into the five bit Calibration byte found in the
a '1' stops the oscillator. The M48T59/59Y/59V in
Control Register. Adding counts speeds the clock
the DIP package, is shipped from up, subtracting counts slows the clock down.
STMicroelectronics with the STOP bit set to a '1'.
When reset to a '0', the M48T59/59Y/59V oscilla- The Calibration byte occupies the five lower order
tor starts within one second. bits (D4-D0) in the Control register (1FF8h). These
bits can be set to represent any value between 0
Note: It is not necessary to set the WRITE bit and 31 in binary form. Bit D5 is a Sign bit; '1' indi-
when setting or resetting the FREQUENCY TEST
cates positive calibration, '0' indicates negative
bit (FT), the STOP bit (ST) or the CENTURY EN-
calibration. Calibration occurs within a 64 minute
ABLE bit (CEB).

Figure 10. Crystal Accuracy Across Temperature

Frequency (ppm)
20

–20

–40

–60

–80
∆F = -0.038 ppm (T - T )2 ± 10%
0
–100 F C2

T0 = 25 °C
–120

–140

–160
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

Temperature °C
AI00999

11/21
M48T59, M48T59Y, M48T59V

cycle. The first 62 minutes in the cycle may, once error, requiring a –10 (WR001010) to be loaded
per minute, have one second either shortened by into the Calibration Byte for correction. Note that
128 or lengthened by 256 oscillator cycles. If a bi- setting or changing the Calibration Byte does not
nary ’1’ is loaded into the register, only the first 2 affect the Frequency test output frequency.
minutes in the 64 minute cycle will be modified; if The IRQ/FT pin is an open drain output which re-
a binary 6 is loaded, the first 12 will be affected, quires a pull-up resistor for proper operation. A
and so on. 500-10kΩ resistor is recommended in order to
Therefore, each calibration step has the effect of control the rise time. The FT bit is cleared on pow-
adding 512 or subtracting 256 oscillator cycles; for er-down.
every 125,829,120 actual oscillator cycles, that is For more information on calibration, see the Appli-
+4.068 or –2.034 ppm of adjustment per calibra- cation Note AN934 "TIMEKEEPER Calibration".
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz, SETTING ALARM CLOCK
each of the 31 increments in the Calibration byte
Registers 1FF5h-1FF2h contain the alarm set-
would represent +10.7 or –5.35 seconds per
tings. The alarm can be configured to go off at a
month which corresponds to a total range of +5.5
prescribed time on a specific day of the month or
or –2.75 minutes per month.
repeat every month, day, hour, minute, or second.
Two methods are available for ascertaining how It can also be programmed to go off while the
much calibration a given M48T59/59Y/59V may M48T59 is in the battery back-up mode of opera-
require. The first involves simply setting the clock, tion to serve as a system wake-up call.
letting it run for a month and comparing it to a
RPT1-RPT4 put the alarm in the repeat mode of
known accurate reference (like WWV broadcasts).
operation. Table 12 shows the possible configura-
While that may seem crude, it allows the designer
tions. Codes not listed in the table default to the
to give the end user the ability to calibrate his clock
once per second mode to quickly alert the user of
as his environment may require, even after the fi-
an incorrect alarm setting.
nal product is packaged in a non-user serviceable
enclosure. All the designer has to do is provide a
simple utility that accesses the Calibration byte.
The second approach is better suited to a manu- Table 12. Alarm Repeat Mode
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz when the RPT4 RPT3 RPT2 RPT1 Alarm Activated
Stop bit (D7 of 1FF9h) is '0', the FT bit (D6 of 1 1 1 1 Once per Second
1FFCh) is '1', the AFE bit (D7 of 1FF6h) is '0', and
the Watchdog Steering bit (D7 of 1FF7h) is '1' or 1 1 1 0 Once per Minute
the Watchdog Register is reset (1FF7h = 0). 1 1 0 0 Once per Hour
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test 1 0 0 0 Once per Day
temperature. For example, a reading of 512.01024 0 0 0 0 Once per Month
Hz would indicate a +20 ppm oscillator frequency

Figure 11. Interrupt Reset Waveforms

15ns Min

A0-A12 ADDRESS 1FF0h

ACTIVE FLAG BIT

IRQ/FT

HIGH-Z

AI01388B

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 M48T59, M48T59Y, M48T59V

Note: User must transition address (or toggle chip WATCHDOG TIMER
enable) to see Flag bit change. The watchdog timer can be used to detect an out-
When the clock information matches the alarm of-control microprocessor. The user programs the
clock settings based on the match criteria defined watchdog timer by setting the desired amount of
by RPT1-RPT4, AF (Alarm Flag) is set. If AFE time-out into the eight bit Watchdog Register (Ad-
(Alarm Flag Enable) is also set, the alarm condi- dress 1FF7h). The five bits (BMB4-BMB0) store a
tion activates the IRQ/FT pin. To disable alarm, binary multiplier and the two lower order bits (RB1-
write ‘0’ to the Alarm Date register and RPT1-4. RB0) select the resolution, where 00 = 1/16 sec-
The alarm flag and the IRQ/FT output are cleared ond, 01 = 1/4 second, 10 = 1 second, and 11 = 4
by a read to the Flags register. seconds. The amount of time-out is then deter-
The IRQ/FT pin can also be activated in the bat- mined to be the multiplication of the five bit multi-
tery back-up mode. The IRQ/FT will go low if an plier value with the resolution. (For example:
alarm occurs and both ABE (Alarm in Battery writing 00001110 in the Watchdog Register = 3 x 1
Back-up Mode Enable) and AFE are set. The ABE or 3 seconds).
and AFE bits are reset during power-up, therefore Note: Accuracy of timer is within ± the selected
an alarm generated during power-up will only set resolution.
AF. The user can read the Flag Register at system If the processor does not reset the timer within the
boot-up to determine if an alarm was generated specified period, the M48T59 sets the WDF
while the M48T59 was in the deselect mode during (Watchdog Flag) and generates a watchdog inter-
power-up. Figure 12 illustrates the back-up mode rupt or a microprocessor reset.
alarm timing.
WDF is reset by reading the Flags Register (Ad-
dress 1FFOh).

Figure 12. Back-up Mode Alarm Waveforms

tREC
VCC
VPFD (max)
VPFD (min)

VSO

ABE, AFE bit in Interrupt Register

AF bit in Flags Register

IRQ/FT

HIGH-Z HIGH-Z

AI03254B

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M48T59, M48T59Y, M48T59V

The most significant bit of the Watchdog Register power-up sequence or the next scheduled 24-hour
is the Watchdog Steering Bit. When set to a ’0’, the interval.
watchdog will activate the IRQ/FT pin when timed- If a battery low is generated during a power-up se-
out. When WDS is set to a ’1’, the watchdog will quence, this indicates that the battery voltage is
output a negative pulse on the RST pin for a dura- below 2.5V (approximately), which may be insuffi-
tion of 40ms to 200ms. The Watchdog register and cient to maintain data integrity. Data should be
the FT bit will reset to a ’0’ at the end of a watchdog considered suspect and verified as correct. A fresh
time-out when the WDS bit is set to a ’1’. battery should be installed.
The watchdog timer resets when the microproces- If a battery low indication is generated during the
sor performs a re-write of the Watchdog Register. 24-hour interval check, this indicates that the bat-
The time-out period then starts over. The watch- tery is near end of life. However, data has not been
dog timer is disabled by writing a value of compromised due to the fact that a nominal VCC
00000000 to the eight bits in the Watchdog Regis- is supplied. In order to insure data integrity during
ter. The watchdog function is automatically dis- subsequent periods of battery back-up mode, it is
abled upon power-down and the Watchdog recommended that the battery be replaced. The
Register is cleared. If the watchdog function is set SNAPHAT top may be replaced while VCC is ap-
to output to the IRQ/FT pin and the frequency test plied to the device.
function is activated, the watchdog or alarm func-
tion prevails and the frequency test function is de- Note: Battery monitoring is a useful technique only
when performed periodically. The M48T59/59Y/
nied.
59V only monitors the battery when a nominal
BATTERY LOW FLAG VCC is applied to the device. Thus applications
which require extensive durations in the battery
The M48T59/59Y/59V automatically performs pe- back-up mode should be powered-up periodically
riodic battery voltage monitoring upon power-up (at least once every few months) in order for this
and at factory-programmed time intervals of 24 technique to be beneficial. Additionally, if a battery
hours (at day rollover) as long as the device is low is indicated, data integrity should be verified
powered and the oscillator is running. The Battery upon power-up via a checksum or other technique.
Low flag (BL), Bit D4 of the flags Register 1FF0h,
will be asserted high if the internal or SNAPHAT POWER-ON DEFAULTS
battery is found to be less than approximately
Upon application of power to the device, the fol-
2.5V. The BL flag will remain active until comple-
tion of battery replacement and subsequent bat- lowing register bits are set to a ’0’ state: WDS;
tery low monitoring tests, either during the next BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT.
(See Table 13).

Table 13. Default Values

WATCHDOG
Condition W R FT AFE ABE
Register (1)
Initial Power-up
0 0 0 0 0 0
(Battery Attach for SNAPHAT) (2)

Subsequent Power-up / RESET (3) 0 0 0 0 0 0

Power-down (4) 0 0 0 1 1 0
Note: 1. WDS, BMB0-BMB4, RBO, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to ’1’ prior to power-down.

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 M48T59, M48T59Y, M48T59V

POWER SUPPLY DECOUPLING and Figure 13. Supply Voltage Protection

UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store en-
ergy, which stabilizes the V CC bus. The energy
stored in the bypass capacitors will be released as VCC
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by- VCC
pass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the need-
ed filtering. 0.1µF DEVICE

In addition to transients that are caused by normal

SRAM operation, power cycling can generate neg-
ative voltage spikes on V CC that drive it to values VSS
below V SS by as much as one Volt. These nega-
tive spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from AI02169

these voltage spikes, it is recommended to con-

nect a schottky diode from V CC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount

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M48T59, M48T59Y, M48T59V

Table 14. Ordering Information Scheme

Example: M48T59Y -70 MH 1 TR

Device Type
M48T

Supply Voltage and Write Protect Voltage

59 (1) = VCC = 4.75V to 5.5V; VPFD = 4.5V to 5.5V
59Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V
59V = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V

Speed
-70 = 70ns

Package
PC = PCDIP28
MH (2) = SOH28

Temperature Range
1 = 0 to 70 °C
6 (3) = –40 to 85 °C

Shipping Method for SOIC

blank = Tubes
TR = Tape & Reel

Note: 1. The M48T59 part is offered with the PCDIP28 (i.e. CAPHAT) package only.
2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number
"M4TXX-BR12SH1" in plastic tube or "M4TXX-BR12SH1TR" in Tape & Reel form.
3. Available in SOIC package only.
Caution: Do not place the SNAPHAT battery/crystal package "M4TXX-BR12SH1" in conductive foam since will drain the lithium button-
cell battery.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.

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 M48T59, M48T59Y, M48T59V

Table 15. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 39.37 39.88 1.550 1.570
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1.430
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0.150
N 28 28

Figure 14. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline

A2 A

A1 L C

B1 B e1
eA
e3

1 PCDIP

Drawing is not to scale.

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M48T59, M48T59Y, M48T59V

Table 16. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 1.27 – – 0.050 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N 28 28
CP 0.10 0.004

Figure 15. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline

A2 A
C
B e eB
CP

D
N

E H

A1 α L
1

SOH-A

Drawing is not to scale.

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 M48T59, M48T59Y, M48T59V

Table 17. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090

Figure 16. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline

A1 A2
A A3

eA B L
eB
D

SHTK-A

Drawing is not to scale.

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M48T59, M48T59Y, M48T59V

Table 18. M4T32-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 0.335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 0.710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090

Figure 17. M4T32-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

A1 A2
A A3

eA B L
eB
D

SHTK-A

Drawing is not to scale.

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 M48T59, M48T59Y, M48T59V

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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