PD - 97312B

IRFR3607PbF
IRFU3607PbF
Applications
l High Efficiency Synchronous Rectification in
SMPS HEXFET® Power MOSFET
l Uninterruptible Power Supply
l High Speed Power Switching
D VDSS 75V
l Hard Switched and High Frequency Circuits RDS(on) typ. 7.34mΩ
max. 9.0mΩ
Benefits
G
ID (Silicon Limited) 80A c
l Improved Gate, Avalanche and Dynamic S ID (Package Limited) 56A
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche SOA D
l Enhanced body diode dV/dt and dI/dt
Capability S S
D
G G

D-Pak I-Pak
IRFR3607PbF IRFU3607PbF

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 80 c
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 56 c A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) 56
IDM Pulsed Drain Currentd 310
PD @TC = 25°C Maximum Power Dissipation 140 W
Linear Derating Factor 0.96 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery f 27 V/ns
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy e 120 mJ
IAR Avalanche Currentd 46 A
EAR Repetitive Avalanche Energy g 14 mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Casek ––– 1.045 °C/W
RθJA Junction-to-Ambient (PCB Mount) j ––– 50
RθJA Junction-to-Ambient ––– 110

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IRFR/U3607PbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 75 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.096 ––– V/°C Reference to 25°C, ID = 5mA d
RDS(on) Static Drain-to-Source On-Resistance ––– 7.34 9.0 mΩ VGS = 10V, ID = 46A g
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 100µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 75V, VGS = 0V
––– ––– 250 VDS = 60V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 115 ––– ––– S VDS = 50V, ID = 46A
Qg Total Gate Charge ––– 56 84 nC ID = 46A
Qgs Gate-to-Source Charge ––– 13 ––– VDS = 38V
Qgd Gate-to-Drain ("Miller") Charge ––– 16 ––– VGS = 10V g
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 40 ––– ID = 46A, VDS =0V, VGS = 10V
RG(int) Internal Gate Resistance ––– 0.55 ––– Ω
td(on) Turn-On Delay Time ––– 16 ––– ns VDD = 49V
tr Rise Time ––– 110 ––– ID = 46A
td(off) Turn-Off Delay Time ––– 43 ––– RG = 6.8Ω
tf Fall Time ––– 96 ––– VGS = 10V g
Ciss Input Capacitance ––– 3070 ––– pF VGS = 0V
Coss Output Capacitance ––– 280 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 130 ––– ƒ = 1.0MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related) j ––– 380 ––– VGS = 0V, VDS = 0V to 60V j
Coss eff. (TR) Effective Output Capacitance (Time Related) h ––– 610 ––– VGS = 0V, VDS = 0V to 60V h
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 80 c A MOSFET symbol D

(Body Diode) showing the

ISM Pulsed Source Current ––– ––– 310 integral reverse G

(Body Diode) d p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 46A, VGS = 0V g
trr Reverse Recovery Time ––– 33 50 ns TJ = 25°C VR = 64V,
––– 39 59 TJ = 125°C IF = 46A
Qrr Reverse Recovery Charge ––– 32 48 nC TJ = 25°C di/dt = 100A/µs g
––– 47 71 TJ = 125°C
IRRM Reverse Recovery Current ––– 1.9 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Calculated continuous current based on maximum allowable junction „ ISD ≤ 46A, di/dt ≤ 1920A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
temperature. Bond wire current limit is 56A. Note that current
† Coss eff. (TR) is a fixed capacitance that gives the same charging time
limitations arising from heating of the device leads may occur with
as Coss while VDS is rising from 0 to 80% VDSS .
some lead mounting arrangements.
‚ Repetitive rating; pulse width limited by max. junction ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
temperature. Coss while VDS is rising from 0 to 80% VDSS.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.12mH ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom-
mended footprint and soldering techniques refer to application note #AN-994.
RG = 25Ω, IAS = 46A, VGS =10V. Part not recommended for use
‰ Rθ is measured at TJ approximately 90°C.
above this value.

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 IRFR/U3607PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
100 4.8V 4.8V
BOTTOM 4.5V BOTTOM 4.5V

100

4.5V
10
4.5V

≤60µs PULSE WIDTH ≤60µs PULSE WIDTH

Tj = 25°C Tj = 175°C
1 10
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 3.0
ID = 80A

RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (A)

2.5
100

2.0
(Normalized)

T J = 175°C
10 T J = 25°C

1.5

1
1.0
VDS = 25V
≤60µs PULSE WIDTH
0.1 0.5
2 3 4 5 6 7 8 -60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS , Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 12.0
VGS = 0V, f = 1 MHZ
ID= 46A
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd 10.0
VGS , Gate-to-Source Voltage (V)

VDS= 24V
Coss = Cds + Cgd
VDS= 15V
C, Capacitance (pF)

10000 8.0

Ciss 6.0

Coss
1000 4.0
Crss
2.0

100 0.0
1 10 100 0 10 20 30 40 50 60
VDS, Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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 IRFR/U3607PbF
1000 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

100
100µsec
T J = 175°C 100
1msec

10
T J = 25°C
10msec
10
1
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse DC

0.1 1
0.0 0.5 1.0 1.5 2.0 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

80 100
Id = 5mA
70 Limited By Package
95
60
ID, Drain Current (A)

90
50

40 85

30
80
20
75
10

0 70
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage

1.20 500
ID
EAS , Single Pulse Avalanche Energy (mJ)

450
1.00 TOP 5.6A
400 11A
BOTTOM 46A
350
0.80
300
Energy (µJ)

0.60 250

200
0.40
150

100
0.20
50
0.00 0
-10 0 10 20 30 40 50 60 70 80 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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10.00

Thermal Response ( Z thJC ) °C/W

1.00
D = 0.50

0.20
0.10 0.10 R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.05 τJ τC 0.01109 0.000003
τJ τ
τ1 0.26925 0.000130
0.02 τ1
τ2 τ3 τ4
τ2 τ3 τ4
0.01 0.49731 0.001301
0.01 Ci= τi/Ri
Ci i/Ri
0.26766 0.008693
Notes:
SINGLE PULSE
1. Duty Factor D = t1/t2
( THERMAL RESPONSE )
2. Peak Tj = P dm x Zthjc + Tc
0.00
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche
100 pulsewidth, tav, assuming ∆Tj = 150°C and
Avalanche Current (A)

Tstart =25°C (Single Pulse)

0.01

10 0.05
0.10

1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth

150 Notes on Repetitive Avalanche Curves , Figures 14, 15:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:
125 ID = 46A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
100
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
75
during avalanche).
6. Iav = Allowable avalanche current.
50 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
25 D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25 50 75 100 125 150 175
Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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IRFR/U3607PbF
4.5 20
IF = 31A
VGS(th) , Gate Threshold Voltage (V)

4.0 V R = 64V

15 TJ = 25°C
3.5
TJ = 125°C

3.0

IRR (A)
10
2.5 ID = 100µA
ID = 250µA
2.0 ID = 1.0mA
5
ID = 1.0A
1.5

1.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 200 0 200 400 600 800 1000
T J , Temperature ( °C ) diF /dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

20 560
IF = 46A IF = 31A
V R = 64V 480 V R = 64V

15 TJ = 25°C TJ = 25°C
400
TJ = 125°C TJ = 125°C

320
Q RR (A)
IRR (A)

10
240

160
5

80

0 0
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/µs) diF /dt (A/µs)

Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

560
IF = 46A
480 V R = 64V
TJ = 25°C
400
TJ = 125°C

320
Q RR (A)

240

160

80

0
0 200 400 600 800 1000
diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRFR/U3607PbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 21a. Unclamped Inductive Test Circuit Fig 21b. Unclamped Inductive Waveforms

LD
VDS VDS
90%
+
VDD -

D.U.T 10%
VGS VGS
Pulse Width < 1µs
Duty Factor < 0.1% td(on) tr td(off) tf

Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms
Id
Vds

Vgs

L
VCC
DUT Vgs(th)
0
1K

Qgs1 Qgs2 Qgd Qgodr

Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform
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IRFR/U3607PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

8 www.irf.com
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I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRFR/U3607PbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/10
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